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Merge tag 'omap-for-v3.16/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / arm / boot / dts / at91sam9x5.dtsi
CommitLineData
467f1cf5
NF		 1/*
2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
3 * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
4 * AT91SAM9X25, AT91SAM9X35 SoC
5 *
6 * Copyright (C) 2012 Atmel,
7 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
6db64d29 12#include "skeleton.dtsi"
d4ae89c8 13#include <dt-bindings/dma/at91.h>
c9d0f317 14#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 15#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 16#include <dt-bindings/gpio/gpio.h>
a80d3ec6 17#include <dt-bindings/clock/at91.h>
467f1cf5
NF		 18
19/ {
20 model = "Atmel AT91SAM9x5 family SoC";
21 compatible = "atmel,at91sam9x5";
22 interrupt-parent = <&aic>;
23
24 aliases {
25 serial0 = &dbgu;
26 serial1 = &usart0;
27 serial2 = &usart1;
28 serial3 = &usart2;
29 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 gpio3 = &pioD;
33 tcb0 = &tcb0;
34 tcb1 = &tcb1;
05dcd361
LD		 35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
099343c6 38 ssc0 = &ssc0;
f3ab0527 39 pwm0 = &pwm0;
467f1cf5
NF		 40 };
41 cpus {
e757a6ee
LP		 42 #address-cells = <0>;
43 #size-cells = <0>;
44
45 cpu {
46 compatible = "arm,arm926ej-s";
47 device_type = "cpu";
467f1cf5
NF		 48 };
49 };
50
dcce6ce8 51 memory {
467f1cf5
NF		 52 reg = <0x20000000 0x10000000>;
53 };
54
a80d3ec6
BB		 55 slow_xtal: slow_xtal {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <0>;
59 };
60
61 main_xtal: main_xtal {
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <0>;
65 };
66
67 adc_op_clk: adc_op_clk{
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <5000000>;
71 };
72
467f1cf5
NF		 73 ahb {
74 compatible = "simple-bus";
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges;
78
79 apb {
80 compatible = "simple-bus";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 ranges;
84
85 aic: interrupt-controller@fffff000 {
f8a073ee 86 #interrupt-cells = <3>;
467f1cf5
NF		 87 compatible = "atmel,at91rm9200-aic";
88 interrupt-controller;
467f1cf5 89 reg = <0xfffff000 0x200>;
c6573943 90 atmel,external-irqs = <31>;
467f1cf5
NF		 91 };
92
a7776ec6
JCPV		 93 ramc0: ramc@ffffe800 {
94 compatible = "atmel,at91sam9g45-ddramc";
95 reg = <0xffffe800 0x200>;
96 };
97
eb5e76ff 98 pmc: pmc@fffffc00 {
a80d3ec6 99 compatible = "atmel,at91sam9x5-pmc";
eb5e76ff 100 reg = <0xfffffc00 0x100>;
a80d3ec6
BB		 101 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
102 interrupt-controller;
103 #address-cells = <1>;
104 #size-cells = <0>;
105 #interrupt-cells = <1>;
106
107 main_rc_osc: main_rc_osc {
108 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
109 #clock-cells = <0>;
110 interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
111 clock-frequency = <12000000>;
112 clock-accuracy = <50000000>;
113 };
114
115 main_osc: main_osc {
116 compatible = "atmel,at91rm9200-clk-main-osc";
117 #clock-cells = <0>;
118 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
119 clocks = <&main_xtal>;
120 };
121
122 main: mainck {
123 compatible = "atmel,at91sam9x5-clk-main";
124 #clock-cells = <0>;
125 interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
126 clocks = <&main_rc_osc>, <&main_osc>;
127 };
128
129 plla: pllack {
130 compatible = "atmel,at91rm9200-clk-pll";
131 #clock-cells = <0>;
132 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
133 clocks = <&main>;
134 reg = <0>;
135 atmel,clk-input-range = <2000000 32000000>;
136 #atmel,pll-clk-output-range-cells = <4>;
137 atmel,pll-clk-output-ranges = <745000000 800000000 0 0
138 695000000 750000000 1 0
139 645000000 700000000 2 0
140 595000000 650000000 3 0
141 545000000 600000000 0 1
142 495000000 555000000 1 1
b6616f11
AB		 143 445000000 500000000 2 1
144 400000000 450000000 3 1>;
a80d3ec6
BB		 145 };
146
147 plladiv: plladivck {
148 compatible = "atmel,at91sam9x5-clk-plldiv";
149 #clock-cells = <0>;
150 clocks = <&plla>;
151 };
152
153 utmi: utmick {
154 compatible = "atmel,at91sam9x5-clk-utmi";
155 #clock-cells = <0>;
156 interrupts-extended = <&pmc AT91_PMC_LOCKU>;
157 clocks = <&main>;
158 };
159
160 mck: masterck {
161 compatible = "atmel,at91sam9x5-clk-master";
162 #clock-cells = <0>;
163 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
164 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
165 atmel,clk-output-range = <0 133333333>;
166 atmel,clk-divisors = <1 2 4 3>;
167 atmel,master-clk-have-div3-pres;
168 };
169
170 usb: usbck {
171 compatible = "atmel,at91sam9x5-clk-usb";
172 #clock-cells = <0>;
173 clocks = <&plladiv>, <&utmi>;
174 };
175
176 prog: progck {
177 compatible = "atmel,at91sam9x5-clk-programmable";
178 #address-cells = <1>;
179 #size-cells = <0>;
180 interrupt-parent = <&pmc>;
181 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
182
183 prog0: prog0 {
184 #clock-cells = <0>;
185 reg = <0>;
186 interrupts = <AT91_PMC_PCKRDY(0)>;
187 };
188
189 prog1: prog1 {
190 #clock-cells = <0>;
191 reg = <1>;
192 interrupts = <AT91_PMC_PCKRDY(1)>;
193 };
194 };
195
196 smd: smdclk {
197 compatible = "atmel,at91sam9x5-clk-smd";
198 #clock-cells = <0>;
199 clocks = <&plladiv>, <&utmi>;
200 };
201
202 systemck {
203 compatible = "atmel,at91rm9200-clk-system";
204 #address-cells = <1>;
205 #size-cells = <0>;
206
207 ddrck: ddrck {
208 #clock-cells = <0>;
209 reg = <2>;
210 clocks = <&mck>;
211 };
212
213 smdck: smdck {
214 #clock-cells = <0>;
215 reg = <4>;
216 clocks = <&smd>;
217 };
218
219 uhpck: uhpck {
220 #clock-cells = <0>;
221 reg = <6>;
222 clocks = <&usb>;
223 };
224
225 udpck: udpck {
226 #clock-cells = <0>;
227 reg = <7>;
228 clocks = <&usb>;
229 };
230
231 pck0: pck0 {
232 #clock-cells = <0>;
233 reg = <8>;
234 clocks = <&prog0>;
235 };
236
237 pck1: pck1 {
238 #clock-cells = <0>;
239 reg = <9>;
240 clocks = <&prog1>;
241 };
242 };
243
244 periphck {
245 compatible = "atmel,at91sam9x5-clk-peripheral";
246 #address-cells = <1>;
247 #size-cells = <0>;
248 clocks = <&mck>;
249
250 pioAB_clk: pioAB_clk {
251 #clock-cells = <0>;
252 reg = <2>;
253 };
254
255 pioCD_clk: pioCD_clk {
256 #clock-cells = <0>;
257 reg = <3>;
258 };
259
260 smd_clk: smd_clk {
261 #clock-cells = <0>;
262 reg = <4>;
263 };
264
265 usart0_clk: usart0_clk {
266 #clock-cells = <0>;
267 reg = <5>;
268 };
269
270 usart1_clk: usart1_clk {
271 #clock-cells = <0>;
272 reg = <6>;
273 };
274
275 usart2_clk: usart2_clk {
276 #clock-cells = <0>;
277 reg = <7>;
278 };
279
280 twi0_clk: twi0_clk {
281 reg = <9>;
282 #clock-cells = <0>;
283 };
284
285 twi1_clk: twi1_clk {
286 #clock-cells = <0>;
287 reg = <10>;
288 };
289
290 twi2_clk: twi2_clk {
291 #clock-cells = <0>;
292 reg = <11>;
293 };
294
295 mci0_clk: mci0_clk {
296 #clock-cells = <0>;
297 reg = <12>;
298 };
299
300 spi0_clk: spi0_clk {
301 #clock-cells = <0>;
302 reg = <13>;
303 };
304
305 spi1_clk: spi1_clk {
306 #clock-cells = <0>;
307 reg = <14>;
308 };
309
310 uart0_clk: uart0_clk {
311 #clock-cells = <0>;
312 reg = <15>;
313 };
314
315 uart1_clk: uart1_clk {
316 #clock-cells = <0>;
317 reg = <16>;
318 };
319
320 tcb0_clk: tcb0_clk {
321 #clock-cells = <0>;
322 reg = <17>;
323 };
324
325 pwm_clk: pwm_clk {
326 #clock-cells = <0>;
327 reg = <18>;
328 };
329
330 adc_clk: adc_clk {
331 #clock-cells = <0>;
332 reg = <19>;
333 };
334
335 dma0_clk: dma0_clk {
336 #clock-cells = <0>;
337 reg = <20>;
338 };
339
340 dma1_clk: dma1_clk {
341 #clock-cells = <0>;
342 reg = <21>;
343 };
344
345 uhphs_clk: uhphs_clk {
346 #clock-cells = <0>;
347 reg = <22>;
348 };
349
350 udphs_clk: udphs_clk {
351 #clock-cells = <0>;
352 reg = <23>;
353 };
354
355 mci1_clk: mci1_clk {
356 #clock-cells = <0>;
357 reg = <26>;
358 };
359
360 ssc0_clk: ssc0_clk {
361 #clock-cells = <0>;
362 reg = <28>;
363 };
364 };
eb5e76ff
JCPV		 365 };
366
c8082d34
JCPV		 367 rstc@fffffe00 {
368 compatible = "atmel,at91sam9g45-rstc";
369 reg = <0xfffffe00 0x10>;
370 };
371
82015c4e
JCPV		 372 shdwc@fffffe10 {
373 compatible = "atmel,at91sam9x5-shdwc";
374 reg = <0xfffffe10 0x10>;
375 };
376
467f1cf5
NF		 377 pit: timer@fffffe30 {
378 compatible = "atmel,at91sam9260-pit";
379 reg = <0xfffffe30 0xf>;
5e8b3bc3 380 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
a80d3ec6
BB		 381 clocks = <&mck>;
382 };
383
384 sckc@fffffe50 {
385 compatible = "atmel,at91sam9x5-sckc";
386 reg = <0xfffffe50 0x4>;
387
388 slow_osc: slow_osc {
389 compatible = "atmel,at91sam9x5-clk-slow-osc";
390 #clock-cells = <0>;
391 clocks = <&slow_xtal>;
392 };
393
394 slow_rc_osc: slow_rc_osc {
395 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
396 #clock-cells = <0>;
397 clock-frequency = <32768>;
398 clock-accuracy = <50000000>;
399 };
400
401 clk32k: slck {
402 compatible = "atmel,at91sam9x5-clk-slow";
403 #clock-cells = <0>;
404 clocks = <&slow_rc_osc>, <&slow_osc>;
405 };
467f1cf5
NF		 406 };
407
408 tcb0: timer@f8008000 {
409 compatible = "atmel,at91sam9x5-tcb";
410 reg = <0xf8008000 0x100>;
5e8b3bc3 411 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
a80d3ec6
BB		 412 clocks = <&tcb0_clk>;
413 clock-names = "t0_clk";
467f1cf5
NF		 414 };
415
416 tcb1: timer@f800c000 {
417 compatible = "atmel,at91sam9x5-tcb";
418 reg = <0xf800c000 0x100>;
5e8b3bc3 419 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
a80d3ec6
BB		 420 clocks = <&tcb0_clk>;
421 clock-names = "t0_clk";
467f1cf5
NF		 422 };
423
424 dma0: dma-controller@ffffec00 {
425 compatible = "atmel,at91sam9g45-dma";
426 reg = <0xffffec00 0x200>;
5e8b3bc3 427 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 428 #dma-cells = <2>;
a80d3ec6
BB		 429 clocks = <&dma0_clk>;
430 clock-names = "dma_clk";
467f1cf5
NF		 431 };
432
433 dma1: dma-controller@ffffee00 {
434 compatible = "atmel,at91sam9g45-dma";
435 reg = <0xffffee00 0x200>;
5e8b3bc3 436 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 437 #dma-cells = <2>;
a80d3ec6
BB		 438 clocks = <&dma1_clk>;
439 clock-names = "dma_clk";
467f1cf5
NF		 440 };
441
ec6754a7 442 pinctrl@fffff400 {
e4541ff2
JCPV		 443 #address-cells = <1>;
444 #size-cells = <1>;
5314ec8e 445 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
e4541ff2
JCPV		 446 ranges = <0xfffff400 0xfffff400 0x800>;
447
5314ec8e 448 /* shared pinctrl settings */
ec6754a7
JCPV		 449 dbgu {
450 pinctrl_dbgu: dbgu-0 {
451 atmel,pins =
c9d0f317
JCPV		 452 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
453 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph A with pullup */
ec6754a7
JCPV		 454 };
455 };
456
9e3129e9
JCPV		 457 usart0 {
458 pinctrl_usart0: usart0-0 {
ec6754a7 459 atmel,pins =
c9d0f317
JCPV		 460 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */
461 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA1 periph A */
ec6754a7
JCPV		 462 };
463
c58c0c5a 464 pinctrl_usart0_rts: usart0_rts-0 {
ec6754a7 465 atmel,pins =
c9d0f317 466 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
c58c0c5a
JCPV		 467 };
468
469 pinctrl_usart0_cts: usart0_cts-0 {
470 atmel,pins =
c9d0f317 471 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
ec6754a7 472 };
1bab02ec
RG		 473
474 pinctrl_usart0_sck: usart0_sck-0 {
475 atmel,pins =
c9d0f317 476 <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */
1bab02ec 477 };
ec6754a7
JCPV		 478 };
479
9e3129e9
JCPV		 480 usart1 {
481 pinctrl_usart1: usart1-0 {
ec6754a7 482 atmel,pins =
c9d0f317
JCPV		 483 <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */
484 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */
ec6754a7
JCPV		 485 };
486
c58c0c5a
JCPV		 487 pinctrl_usart1_rts: usart1_rts-0 {
488 atmel,pins =
c9d0f317 489 <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC27 periph C */
c58c0c5a
JCPV		 490 };
491
492 pinctrl_usart1_cts: usart1_cts-0 {
ec6754a7 493 atmel,pins =
c9d0f317 494 <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C */
ec6754a7 495 };
1bab02ec
RG		 496
497 pinctrl_usart1_sck: usart1_sck-0 {
498 atmel,pins =
c9d0f317 499 <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */
1bab02ec 500 };
ec6754a7
JCPV		 501 };
502
9e3129e9
JCPV		 503 usart2 {
504 pinctrl_usart2: usart2-0 {
ec6754a7 505 atmel,pins =
c9d0f317
JCPV		 506 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
507 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */
ec6754a7
JCPV		 508 };
509
df923c15 510 pinctrl_usart2_rts: usart2_rts-0 {
ec6754a7 511 atmel,pins =
c9d0f317 512 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
c58c0c5a
JCPV		 513 };
514
df923c15 515 pinctrl_usart2_cts: usart2_cts-0 {
c58c0c5a 516 atmel,pins =
c9d0f317 517 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
ec6754a7 518 };
1bab02ec
RG		 519
520 pinctrl_usart2_sck: usart2_sck-0 {
521 atmel,pins =
c9d0f317 522 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */
1bab02ec 523 };
ec6754a7
JCPV		 524 };
525
9e3129e9
JCPV		 526 uart0 {
527 pinctrl_uart0: uart0-0 {
ec6754a7 528 atmel,pins =
c9d0f317
JCPV		 529 <AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC8 periph C */
530 AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC9 periph C with pullup */
ec6754a7
JCPV		 531 };
532 };
533
9e3129e9
JCPV		 534 uart1 {
535 pinctrl_uart1: uart1-0 {
ec6754a7 536 atmel,pins =
c9d0f317
JCPV		 537 <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC16 periph C */
538 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC17 periph C with pullup */
ec6754a7
JCPV		 539 };
540 };
5314ec8e 541
7a38d450
JCPV		 542 nand {
543 pinctrl_nand: nand-0 {
544 atmel,pins =
c9d0f317
JCPV		 545 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */
546 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A Write Enable */
547 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A Address Latch Enable */
548 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A Command Latch Enable */
549 AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD4 gpio Chip Enable pin pull_up */
550 AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY/BUSY pin pull_up */
551 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */
552 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A Data bit 1 */
553 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A Data bit 2 */
554 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A Data bit 3 */
555 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A Data bit 4 */
556 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A Data bit 5 */
557 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD12 periph A Data bit 6 */
558 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */
7f06472f
RG		 559 };
560
561 pinctrl_nand_16bits: nand_16bits-0 {
562 atmel,pins =
c9d0f317
JCPV		 563 <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A Data bit 8 */
564 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A Data bit 9 */
565 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD16 periph A Data bit 10 */
566 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A Data bit 11 */
567 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD18 periph A Data bit 12 */
568 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD19 periph A Data bit 13 */
569 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */
570 AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */
7a38d450
JCPV		 571 };
572 };
573
d4fe9ac7
JCPV		 574 mmc0 {
575 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
576 atmel,pins =
c9d0f317
JCPV		 577 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
578 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
579 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
d4fe9ac7
JCPV		 580 };
581
582 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
583 atmel,pins =
c9d0f317
JCPV		 584 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
585 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
586 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
d4fe9ac7
JCPV		 587 };
588 };
589
590 mmc1 {
591 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
592 atmel,pins =
c9d0f317
JCPV		 593 <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA13 periph B */
594 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
595 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA11 periph B with pullup */
d4fe9ac7
JCPV		 596 };
597
598 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
599 atmel,pins =
c9d0f317
JCPV		 600 <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA2 periph B with pullup */
601 AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA3 periph B with pullup */
602 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA4 periph B with pullup */
d4fe9ac7
JCPV		 603 };
604 };
605
544ae6b2
BS		 606 ssc0 {
607 pinctrl_ssc0_tx: ssc0_tx-0 {
608 atmel,pins =
c9d0f317
JCPV		 609 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
610 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
611 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
544ae6b2
BS		 612 };
613
614 pinctrl_ssc0_rx: ssc0_rx-0 {
615 atmel,pins =
c9d0f317
JCPV		 616 <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
617 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
618 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
544ae6b2
BS		 619 };
620 };
621
a68b728f
WY		 622 spi0 {
623 pinctrl_spi0: spi0-0 {
624 atmel,pins =
c9d0f317
JCPV		 625 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
626 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
627 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
a68b728f
WY		 628 };
629 };
630
631 spi1 {
632 pinctrl_spi1: spi1-0 {
633 atmel,pins =
c9d0f317
JCPV		 634 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
635 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
636 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
a68b728f
WY		 637 };
638 };
639
e9a72ee8
RG		 640 i2c0 {
641 pinctrl_i2c0: i2c0-0 {
642 atmel,pins =
c9d0f317
JCPV		 643 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A I2C0 data */
644 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A I2C0 clock */
e9a72ee8
RG		 645 };
646 };
647
648 i2c1 {
649 pinctrl_i2c1: i2c1-0 {
650 atmel,pins =
c9d0f317
JCPV		 651 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */
652 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC1 periph C I2C1 clock */
e9a72ee8
RG		 653 };
654 };
655
656 i2c2 {
657 pinctrl_i2c2: i2c2-0 {
658 atmel,pins =
c9d0f317
JCPV		 659 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B I2C2 data */
660 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B I2C2 clock */
e9a72ee8
RG		 661 };
662 };
663
463c9c7b
RG		 664 i2c_gpio0 {
665 pinctrl_i2c_gpio0: i2c_gpio0-0 {
666 atmel,pins =
c9d0f317
JCPV		 667 <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA30 gpio multidrive I2C0 data */
668 AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA31 gpio multidrive I2C0 clock */
463c9c7b
RG		 669 };
670 };
671
672 i2c_gpio1 {
673 pinctrl_i2c_gpio1: i2c_gpio1-0 {
674 atmel,pins =
c9d0f317
JCPV		 675 <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */
676 AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PC1 gpio multidrive I2C1 clock */
463c9c7b
RG		 677 };
678 };
679
680 i2c_gpio2 {
681 pinctrl_i2c_gpio2: i2c_gpio2-0 {
682 atmel,pins =
c9d0f317
JCPV		 683 <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PB4 gpio multidrive I2C2 data */
684 AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB5 gpio multidrive I2C2 clock */
463c9c7b
RG		 685 };
686 };
687
028633c2
BB		 688 tcb0 {
689 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
690 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
691 };
692
693 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
694 atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
695 };
696
697 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
698 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
699 };
700
701 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
702 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
703 };
704
705 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
706 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
707 };
708
709 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
710 atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
711 };
712
713 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
714 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
715 };
716
717 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
718 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
719 };
720
721 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
722 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
723 };
724 };
725
726 tcb1 {
727 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
728 atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
729 };
730
731 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
732 atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
733 };
734
735 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
736 atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
737 };
738
739 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
740 atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
741 };
742
743 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
744 atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
745 };
746
747 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
748 atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
749 };
750
751 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
752 atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
753 };
754
755 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
756 atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
757 };
758
759 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
760 atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
761 };
762 };
763
e4541ff2
JCPV		 764 pioA: gpio@fffff400 {
765 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
766 reg = <0xfffff400 0x200>;
5e8b3bc3 767 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2
JCPV		 768 #gpio-cells = <2>;
769 gpio-controller;
770 interrupt-controller;
771 #interrupt-cells = <2>;
a80d3ec6 772 clocks = <&pioAB_clk>;
e4541ff2
JCPV		 773 };
774
775 pioB: gpio@fffff600 {
776 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
777 reg = <0xfffff600 0x200>;
5e8b3bc3 778 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2
JCPV		 779 #gpio-cells = <2>;
780 gpio-controller;
fc33ff43 781 #gpio-lines = <19>;
e4541ff2
JCPV		 782 interrupt-controller;
783 #interrupt-cells = <2>;
a80d3ec6 784 clocks = <&pioAB_clk>;
e4541ff2
JCPV		 785 };
786
787 pioC: gpio@fffff800 {
788 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
789 reg = <0xfffff800 0x200>;
5e8b3bc3 790 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2
JCPV		 791 #gpio-cells = <2>;
792 gpio-controller;
793 interrupt-controller;
794 #interrupt-cells = <2>;
a80d3ec6 795 clocks = <&pioCD_clk>;
e4541ff2
JCPV		 796 };
797
798 pioD: gpio@fffffa00 {
799 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
800 reg = <0xfffffa00 0x200>;
5e8b3bc3 801 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2
JCPV		 802 #gpio-cells = <2>;
803 gpio-controller;
fc33ff43 804 #gpio-lines = <22>;
e4541ff2
JCPV		 805 interrupt-controller;
806 #interrupt-cells = <2>;
a80d3ec6 807 clocks = <&pioCD_clk>;
e4541ff2 808 };
467f1cf5
NF		 809 };
810
544ae6b2
BS		 811 ssc0: ssc@f0010000 {
812 compatible = "atmel,at91sam9g45-ssc";
813 reg = <0xf0010000 0x4000>;
5e8b3bc3 814 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
7da49ad1
RG		 815 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>,
816 <&dma0 1 AT91_DMA_CFG_PER_ID(14)>;
817 dma-names = "tx", "rx";
544ae6b2
BS		 818 pinctrl-names = "default";
819 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
a80d3ec6
BB		 820 clocks = <&ssc0_clk>;
821 clock-names = "pclk";
544ae6b2
BS		 822 status = "disabled";
823 };
824
9873137a
LD		 825 mmc0: mmc@f0008000 {
826 compatible = "atmel,hsmci";
827 reg = <0xf0008000 0x600>;
5e8b3bc3 828 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 829 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 830 dma-names = "rxtx";
e7cca254 831 pinctrl-names = "default";
a80d3ec6
BB		 832 clocks = <&mci0_clk>;
833 clock-names = "mci_clk";
9873137a
LD		 834 #address-cells = <1>;
835 #size-cells = <0>;
836 status = "disabled";
837 };
838
839 mmc1: mmc@f000c000 {
840 compatible = "atmel,hsmci";
841 reg = <0xf000c000 0x600>;
5e8b3bc3 842 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 843 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 844 dma-names = "rxtx";
e7cca254 845 pinctrl-names = "default";
a80d3ec6
BB		 846 clocks = <&mci1_clk>;
847 clock-names = "mci_clk";
9873137a
LD		 848 #address-cells = <1>;
849 #size-cells = <0>;
850 status = "disabled";
851 };
852
467f1cf5
NF		 853 dbgu: serial@fffff200 {
854 compatible = "atmel,at91sam9260-usart";
855 reg = <0xfffff200 0x200>;
5e8b3bc3 856 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
ec6754a7
JCPV		 857 pinctrl-names = "default";
858 pinctrl-0 = <&pinctrl_dbgu>;
a80d3ec6
BB		 859 clocks = <&mck>;
860 clock-names = "usart";
467f1cf5
NF		 861 status = "disabled";
862 };
863
864 usart0: serial@f801c000 {
865 compatible = "atmel,at91sam9260-usart";
866 reg = <0xf801c000 0x200>;
5e8b3bc3 867 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
ec6754a7 868 pinctrl-names = "default";
9e3129e9 869 pinctrl-0 = <&pinctrl_usart0>;
a80d3ec6
BB		 870 clocks = <&usart0_clk>;
871 clock-names = "usart";
467f1cf5
NF		 872 status = "disabled";
873 };
874
875 usart1: serial@f8020000 {
876 compatible = "atmel,at91sam9260-usart";
877 reg = <0xf8020000 0x200>;
5e8b3bc3 878 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
ec6754a7 879 pinctrl-names = "default";
9e3129e9 880 pinctrl-0 = <&pinctrl_usart1>;
a80d3ec6
BB		 881 clocks = <&usart1_clk>;
882 clock-names = "usart";
467f1cf5
NF		 883 status = "disabled";
884 };
885
886 usart2: serial@f8024000 {
887 compatible = "atmel,at91sam9260-usart";
888 reg = <0xf8024000 0x200>;
5e8b3bc3 889 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
ec6754a7 890 pinctrl-names = "default";
9e3129e9 891 pinctrl-0 = <&pinctrl_usart2>;
a80d3ec6
BB		 892 clocks = <&usart2_clk>;
893 clock-names = "usart";
467f1cf5
NF		 894 status = "disabled";
895 };
896
05dcd361
LD		 897 i2c0: i2c@f8010000 {
898 compatible = "atmel,at91sam9x5-i2c";
899 reg = <0xf8010000 0x100>;
5e8b3bc3 900 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 901 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>,
902 <&dma0 1 AT91_DMA_CFG_PER_ID(8)>;
d9a63a45 903 dma-names = "tx", "rx";
05dcd361
LD		 904 #address-cells = <1>;
905 #size-cells = <0>;
e9a72ee8
RG		 906 pinctrl-names = "default";
907 pinctrl-0 = <&pinctrl_i2c0>;
a80d3ec6 908 clocks = <&twi0_clk>;
05dcd361
LD		 909 status = "disabled";
910 };
911
912 i2c1: i2c@f8014000 {
913 compatible = "atmel,at91sam9x5-i2c";
914 reg = <0xf8014000 0x100>;
5e8b3bc3 915 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 916 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>,
917 <&dma1 1 AT91_DMA_CFG_PER_ID(6)>;
d9a63a45 918 dma-names = "tx", "rx";
05dcd361
LD		 919 #address-cells = <1>;
920 #size-cells = <0>;
e9a72ee8
RG		 921 pinctrl-names = "default";
922 pinctrl-0 = <&pinctrl_i2c1>;
a80d3ec6 923 clocks = <&twi1_clk>;
05dcd361
LD		 924 status = "disabled";
925 };
926
927 i2c2: i2c@f8018000 {
928 compatible = "atmel,at91sam9x5-i2c";
929 reg = <0xf8018000 0x100>;
5e8b3bc3 930 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 931 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>,
932 <&dma0 1 AT91_DMA_CFG_PER_ID(10)>;
d9a63a45 933 dma-names = "tx", "rx";
05dcd361
LD		 934 #address-cells = <1>;
935 #size-cells = <0>;
e9a72ee8
RG		 936 pinctrl-names = "default";
937 pinctrl-0 = <&pinctrl_i2c2>;
a80d3ec6 938 clocks = <&twi2_clk>;
05dcd361
LD		 939 status = "disabled";
940 };
941
06723db5
NF		 942 uart0: serial@f8040000 {
943 compatible = "atmel,at91sam9260-usart";
944 reg = <0xf8040000 0x200>;
945 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
946 pinctrl-names = "default";
947 pinctrl-0 = <&pinctrl_uart0>;
a80d3ec6
BB		 948 clocks = <&uart0_clk>;
949 clock-names = "usart";
06723db5
NF		 950 status = "disabled";
951 };
952
953 uart1: serial@f8044000 {
954 compatible = "atmel,at91sam9260-usart";
955 reg = <0xf8044000 0x200>;
956 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
957 pinctrl-names = "default";
958 pinctrl-0 = <&pinctrl_uart1>;
a80d3ec6
BB		 959 clocks = <&uart1_clk>;
960 clock-names = "usart";
06723db5
NF		 961 status = "disabled";
962 };
963
d029f371 964 adc0: adc@f804c000 {
ce1e8d3d
AB		 965 #address-cells = <1>;
966 #size-cells = <0>;
d029f371
MR		 967 compatible = "atmel,at91sam9260-adc";
968 reg = <0xf804c000 0x100>;
5e8b3bc3 969 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
a80d3ec6
BB		 970 clocks = <&adc_clk>,
971 <&adc_op_clk>;
972 clock-names = "adc_clk", "adc_op_clk";
ce1e8d3d 973 atmel,adc-use-external-triggers;
d029f371
MR		 974 atmel,adc-channels-used = <0xffff>;
975 atmel,adc-vref = <3300>;
d029f371 976 atmel,adc-startup-time = <40>;
4b50da65
LD		 977 atmel,adc-res = <8 10>;
978 atmel,adc-res-names = "lowres", "highres";
979 atmel,adc-use-res = "highres";
d029f371
MR		 980
981 trigger@0 {
ce1e8d3d 982 reg = <0>;
d029f371
MR		 983 trigger-name = "external-rising";
984 trigger-value = <0x1>;
985 trigger-external;
986 };
987
988 trigger@1 {
ce1e8d3d 989 reg = <1>;
d029f371
MR		 990 trigger-name = "external-falling";
991 trigger-value = <0x2>;
992 trigger-external;
993 };
994
995 trigger@2 {
ce1e8d3d 996 reg = <2>;
d029f371
MR		 997 trigger-name = "external-any";
998 trigger-value = <0x3>;
999 trigger-external;
1000 };
1001
1002 trigger@3 {
ce1e8d3d 1003 reg = <3>;
d029f371
MR		 1004 trigger-name = "continuous";
1005 trigger-value = <0x6>;
1006 };
1007 };
d50f88a0
RG		 1008
1009 spi0: spi@f0000000 {
1010 #address-cells = <1>;
1011 #size-cells = <0>;
1012 compatible = "atmel,at91rm9200-spi";
1013 reg = <0xf0000000 0x100>;
5e8b3bc3 1014 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
6b2a9999
RG		 1015 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>,
1016 <&dma0 1 AT91_DMA_CFG_PER_ID(2)>;
1017 dma-names = "tx", "rx";
a68b728f
WY		 1018 pinctrl-names = "default";
1019 pinctrl-0 = <&pinctrl_spi0>;
a80d3ec6
BB		 1020 clocks = <&spi0_clk>;
1021 clock-names = "spi_clk";
d50f88a0
RG		 1022 status = "disabled";
1023 };
1024
1025 spi1: spi@f0004000 {
1026 #address-cells = <1>;
1027 #size-cells = <0>;
1028 compatible = "atmel,at91rm9200-spi";
1029 reg = <0xf0004000 0x100>;
5e8b3bc3 1030 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
6b2a9999
RG		 1031 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>,
1032 <&dma1 1 AT91_DMA_CFG_PER_ID(2)>;
1033 dma-names = "tx", "rx";
a68b728f
WY		 1034 pinctrl-names = "default";
1035 pinctrl-0 = <&pinctrl_spi1>;
a80d3ec6
BB		 1036 clocks = <&spi1_clk>;
1037 clock-names = "spi_clk";
d50f88a0
RG		 1038 status = "disabled";
1039 };
dfab34aa 1040
aecca65c
JCPV		 1041 usb2: gadget@f803c000 {
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1044 compatible = "atmel,at91sam9rl-udc";
1045 reg = <0x00500000 0x80000
1046 0xf803c000 0x400>;
1047 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
1048 status = "disabled";
1049
1050 ep0 {
1051 reg = <0>;
1052 atmel,fifo-size = <64>;
1053 atmel,nb-banks = <1>;
1054 };
1055
1056 ep1 {
1057 reg = <1>;
1058 atmel,fifo-size = <1024>;
1059 atmel,nb-banks = <2>;
1060 atmel,can-dma;
1061 atmel,can-isoc;
1062 };
1063
1064 ep2 {
1065 reg = <2>;
1066 atmel,fifo-size = <1024>;
1067 atmel,nb-banks = <2>;
1068 atmel,can-dma;
1069 atmel,can-isoc;
1070 };
1071
1072 ep3 {
1073 reg = <3>;
1074 atmel,fifo-size = <1024>;
1075 atmel,nb-banks = <3>;
1076 atmel,can-dma;
1077 };
1078
1079 ep4 {
1080 reg = <4>;
1081 atmel,fifo-size = <1024>;
1082 atmel,nb-banks = <3>;
1083 atmel,can-dma;
1084 };
1085
1086 ep5 {
1087 reg = <5>;
1088 atmel,fifo-size = <1024>;
1089 atmel,nb-banks = <3>;
1090 atmel,can-dma;
1091 atmel,can-isoc;
1092 };
1093
1094 ep6 {
1095 reg = <6>;
1096 atmel,fifo-size = <1024>;
1097 atmel,nb-banks = <3>;
1098 atmel,can-dma;
1099 atmel,can-isoc;
1100 };
1101 };
1102
136d3556
WY		 1103 watchdog@fffffe40 {
1104 compatible = "atmel,at91sam9260-wdt";
1105 reg = <0xfffffe40 0x10>;
fe46aa67
BB		 1106 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1107 atmel,watchdog-type = "hardware";
1108 atmel,reset-type = "all";
1109 atmel,dbg-halt;
1110 atmel,idle-halt;
136d3556
WY		 1111 status = "disabled";
1112 };
1113
b909c6c9 1114 rtc@fffffeb0 {
23fb05c6 1115 compatible = "atmel,at91sam9x5-rtc";
b909c6c9 1116 reg = <0xfffffeb0 0x40>;
5e8b3bc3 1117 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
b909c6c9
NF		 1118 status = "disabled";
1119 };
f3ab0527
BS		 1120
1121 pwm0: pwm@f8034000 {
1122 compatible = "atmel,at91sam9rl-pwm";
1123 reg = <0xf8034000 0x300>;
1124 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
1125 #pwm-cells = <3>;
1126 status = "disabled";
1127 };
467f1cf5 1128 };
86a89f4f
JCPV		 1129
1130 nand0: nand@40000000 {
1131 compatible = "atmel,at91rm9200-nand";
1132 #address-cells = <1>;
1133 #size-cells = <1>;
1134 reg = <0x40000000 0x10000000
5314bc2d
JW		 1135 0xffffe000 0x600 /* PMECC Registers */
1136 0xffffe600 0x200 /* PMECC Error Location Registers */
1137 0x00108000 0x18000 /* PMECC looup table in ROM code */
86a89f4f 1138 >;
5314bc2d 1139 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
86a89f4f
JCPV		 1140 atmel,nand-addr-offset = <21>;
1141 atmel,nand-cmd-offset = <22>;
e8b2da6e 1142 atmel,nand-has-dma;
7a38d450
JCPV		 1143 pinctrl-names = "default";
1144 pinctrl-0 = <&pinctrl_nand>;
92f8629b
JCPV		 1145 gpios = <&pioD 5 GPIO_ACTIVE_HIGH
1146 &pioD 4 GPIO_ACTIVE_HIGH
86a89f4f
JCPV		 1147 0
1148 >;
1149 status = "disabled";
1150 };
6a062459
JCPV		 1151
1152 usb0: ohci@00600000 {
1153 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1154 reg = <0x00600000 0x100000>;
5e8b3bc3 1155 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
a80d3ec6
BB		 1156 clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
1157 <&uhpck>;
1158 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
6a062459
JCPV		 1159 status = "disabled";
1160 };
62c5553a
JCPV		 1161
1162 usb1: ehci@00700000 {
1163 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1164 reg = <0x00700000 0x100000>;
5e8b3bc3 1165 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
a80d3ec6
BB		 1166 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
1167 clock-names = "usb_clk", "ehci_clk", "uhpck";
62c5553a
JCPV		 1168 status = "disabled";
1169 };
467f1cf5 1170 };
10f71c28
JCPV		 1171
1172 i2c@0 {
1173 compatible = "i2c-gpio";
92f8629b
JCPV		 1174 gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
1175 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
10f71c28
JCPV		 1176 >;
1177 i2c-gpio,sda-open-drain;
1178 i2c-gpio,scl-open-drain;
1179 i2c-gpio,delay-us = <2>; /* ~100 kHz */
1180 #address-cells = <1>;
1181 #size-cells = <0>;
463c9c7b
RG		 1182 pinctrl-names = "default";
1183 pinctrl-0 = <&pinctrl_i2c_gpio0>;
10f71c28
JCPV		 1184 status = "disabled";
1185 };
1186
1187 i2c@1 {
1188 compatible = "i2c-gpio";
92f8629b
JCPV		 1189 gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
1190 &pioC 1 GPIO_ACTIVE_HIGH /* scl */
10f71c28
JCPV		 1191 >;
1192 i2c-gpio,sda-open-drain;
1193 i2c-gpio,scl-open-drain;
1194 i2c-gpio,delay-us = <2>; /* ~100 kHz */
1195 #address-cells = <1>;
1196 #size-cells = <0>;
463c9c7b
RG		 1197 pinctrl-names = "default";
1198 pinctrl-0 = <&pinctrl_i2c_gpio1>;
10f71c28
JCPV		 1199 status = "disabled";
1200 };
1201
1202 i2c@2 {
1203 compatible = "i2c-gpio";
92f8629b
JCPV		 1204 gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
1205 &pioB 5 GPIO_ACTIVE_HIGH /* scl */
10f71c28
JCPV		 1206 >;
1207 i2c-gpio,sda-open-drain;
1208 i2c-gpio,scl-open-drain;
1209 i2c-gpio,delay-us = <2>; /* ~100 kHz */
1210 #address-cells = <1>;
1211 #size-cells = <0>;
463c9c7b
RG		 1212 pinctrl-names = "default";
1213 pinctrl-0 = <&pinctrl_i2c_gpio2>;
10f71c28
JCPV		 1214 status = "disabled";
1215 };
467f1cf5 1216};
Linux kernel - Deliverables
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