projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 5fa2f9af BS |
1 | /* |
| 2 | * DTS file for CSR SiRFatlas6 SoC | |
| 3 | * | |
| 4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | |
| 5 | * | |
| 6 | * Licensed under GPLv2 or later. | |
| 7 | */ | |
| 8 | ||
| 9 | /include/ "skeleton.dtsi" | |
| 10 | / { | |
| 11 | compatible = "sirf,atlas6"; | |
| 12 | #address-cells = <1>; | |
| 13 | #size-cells = <1>; | |
| 14 | interrupt-parent = <&intc>; | |
| 15 | ||
| 16 | cpus { | |
| 17 | #address-cells = <1>; | |
| 18 | #size-cells = <0>; | |
| 19 | ||
| 20 | cpu@0 { | |
| 21 | reg = <0x0>; | |
| 22 | d-cache-line-size = <32>; | |
| 23 | i-cache-line-size = <32>; | |
| 24 | d-cache-size = <32768>; | |
| 25 | i-cache-size = <32768>; | |
| 26 | /* from bootloader */ | |
| 27 | timebase-frequency = <0>; | |
| 28 | bus-frequency = <0>; | |
| 29 | clock-frequency = <0>; | |
| 30 | }; | |
| 31 | }; | |
| 32 | ||
| 33 | axi { | |
| 34 | compatible = "simple-bus"; | |
| 35 | #address-cells = <1>; | |
| 36 | #size-cells = <1>; | |
| 37 | ranges = <0x40000000 0x40000000 0x80000000>; | |
| 38 | ||
| 39 | intc: interrupt-controller@80020000 { | |
| 40 | #interrupt-cells = <1>; | |
| 41 | interrupt-controller; | |
| 42 | compatible = "sirf,prima2-intc"; | |
| 43 | reg = <0x80020000 0x1000>; | |
| 44 | }; | |
| 45 | ||
| 46 | sys-iobg { | |
| 47 | compatible = "simple-bus"; | |
| 48 | #address-cells = <1>; | |
| 49 | #size-cells = <1>; | |
| 50 | ranges = <0x88000000 0x88000000 0x40000>; | |
| 51 | ||
| 52 | clks: clock-controller@88000000 { | |
| 53 | compatible = "sirf,atlas6-clkc"; | |
| 54 | reg = <0x88000000 0x1000>; | |
| 55 | interrupts = <3>; | |
| 56 | #clock-cells = <1>; | |
| 57 | }; | |
| 58 | ||
| 59 | reset-controller@88010000 { | |
| 60 | compatible = "sirf,prima2-rstc"; | |
| 61 | reg = <0x88010000 0x1000>; | |
| 62 | }; | |
| 63 | ||
| 64 | rsc-controller@88020000 { | |
| 65 | compatible = "sirf,prima2-rsc"; | |
| 66 | reg = <0x88020000 0x1000>; | |
| 67 | }; | |
| 0671840c BS |
68 | |
| 69 | cphifbg@88030000 { | |
| 70 | compatible = "sirf,prima2-cphifbg"; | |
| 71 | reg = <0x88030000 0x1000>; | |
| 794f8b21 | 72 | clocks = <&clks 42>; |
| 0671840c | 73 | }; |
| 5fa2f9af BS |
74 | }; |
| 75 | ||
| 76 | mem-iobg { | |
| 77 | compatible = "simple-bus"; | |
| 78 | #address-cells = <1>; | |
| 79 | #size-cells = <1>; | |
| 80 | ranges = <0x90000000 0x90000000 0x10000>; | |
| 81 | ||
| 82 | memory-controller@90000000 { | |
| 83 | compatible = "sirf,prima2-memc"; | |
| 5fadea22 | 84 | reg = <0x90000000 0x2000>; |
| 5fa2f9af BS |
85 | interrupts = <27>; |
| 86 | clocks = <&clks 5>; | |
| 87 | }; | |
| 5fadea22 YH |
88 | |
| 89 | memc-monitor { | |
| 90 | compatible = "sirf,prima2-memcmon"; | |
| 91 | reg = <0x90002000 0x200>; | |
| 92 | interrupts = <4>; | |
| 93 | clocks = <&clks 32>; | |
| 94 | }; | |
| 5fa2f9af BS |
95 | }; |
| 96 | ||
| 97 | disp-iobg { | |
| 98 | compatible = "simple-bus"; | |
| 99 | #address-cells = <1>; | |
| 100 | #size-cells = <1>; | |
| 101 | ranges = <0x90010000 0x90010000 0x30000>; | |
| 102 | ||
| 103 | lcd@90010000 { | |
| 104 | compatible = "sirf,prima2-lcd"; | |
| 105 | reg = <0x90010000 0x20000>; | |
| 106 | interrupts = <30>; | |
| 107 | clocks = <&clks 34>; | |
| 108 | display=<&display>; | |
| 109 | /* later transfer to pwm */ | |
| 110 | bl-gpio = <&gpio 7 0>; | |
| 111 | default-panel = <&panel0>; | |
| 112 | }; | |
| 113 | ||
| 114 | vpp@90020000 { | |
| 115 | compatible = "sirf,prima2-vpp"; | |
| 116 | reg = <0x90020000 0x10000>; | |
| 117 | interrupts = <31>; | |
| 118 | clocks = <&clks 35>; | |
| 119 | }; | |
| 120 | }; | |
| 121 | ||
| 122 | graphics-iobg { | |
| 123 | compatible = "simple-bus"; | |
| 124 | #address-cells = <1>; | |
| 125 | #size-cells = <1>; | |
| 126 | ranges = <0x98000000 0x98000000 0x8000000>; | |
| 127 | ||
| 128 | graphics@98000000 { | |
| 129 | compatible = "powervr,sgx510"; | |
| 130 | reg = <0x98000000 0x8000000>; | |
| 131 | interrupts = <6>; | |
| 132 | clocks = <&clks 32>; | |
| 133 | }; | |
| 134 | }; | |
| 135 | ||
| 304ec42f JC |
136 | graphics2d-iobg { |
| 137 | compatible = "simple-bus"; | |
| 138 | #address-cells = <1>; | |
| 139 | #size-cells = <1>; | |
| 140 | ranges = <0xa0000000 0xa0000000 0x8000000>; | |
| 141 | ||
| 142 | ble@a0000000 { | |
| 143 | compatible = "sirf,atlas6-ble"; | |
| 144 | reg = <0xa0000000 0x2000>; | |
| 145 | interrupts = <5>; | |
| 146 | clocks = <&clks 33>; | |
| 147 | }; | |
| 148 | }; | |
| 149 | ||
| 5fa2f9af BS |
150 | dsp-iobg { |
| 151 | compatible = "simple-bus"; | |
| 152 | #address-cells = <1>; | |
| 153 | #size-cells = <1>; | |
| 154 | ranges = <0xa8000000 0xa8000000 0x2000000>; | |
| 155 | ||
| 156 | dspif@a8000000 { | |
| 157 | compatible = "sirf,prima2-dspif"; | |
| 158 | reg = <0xa8000000 0x10000>; | |
| 159 | interrupts = <9>; | |
| 160 | }; | |
| 161 | ||
| 162 | gps@a8010000 { | |
| 163 | compatible = "sirf,prima2-gps"; | |
| 164 | reg = <0xa8010000 0x10000>; | |
| 165 | interrupts = <7>; | |
| 166 | clocks = <&clks 9>; | |
| 167 | }; | |
| 168 | ||
| 169 | dsp@a9000000 { | |
| 170 | compatible = "sirf,prima2-dsp"; | |
| 171 | reg = <0xa9000000 0x1000000>; | |
| 172 | interrupts = <8>; | |
| 173 | clocks = <&clks 8>; | |
| 174 | }; | |
| 175 | }; | |
| 176 | ||
| 177 | peri-iobg { | |
| 178 | compatible = "simple-bus"; | |
| 179 | #address-cells = <1>; | |
| 180 | #size-cells = <1>; | |
| 181 | ranges = <0xb0000000 0xb0000000 0x180000>, | |
| 182 | <0x56000000 0x56000000 0x1b00000>; | |
| 183 | ||
| 184 | timer@b0020000 { | |
| 185 | compatible = "sirf,prima2-tick"; | |
| 186 | reg = <0xb0020000 0x1000>; | |
| 187 | interrupts = <0>; | |
| 188 | }; | |
| 189 | ||
| 190 | nand@b0030000 { | |
| 191 | compatible = "sirf,prima2-nand"; | |
| 192 | reg = <0xb0030000 0x10000>; | |
| 193 | interrupts = <41>; | |
| 194 | clocks = <&clks 26>; | |
| 195 | }; | |
| 196 | ||
| 197 | audio@b0040000 { | |
| 198 | compatible = "sirf,prima2-audio"; | |
| 199 | reg = <0xb0040000 0x10000>; | |
| 200 | interrupts = <35>; | |
| 201 | clocks = <&clks 27>; | |
| 202 | }; | |
| 203 | ||
| 204 | uart0: uart@b0050000 { | |
| 205 | cell-index = <0>; | |
| 206 | compatible = "sirf,prima2-uart"; | |
| 207 | reg = <0xb0050000 0x1000>; | |
| 208 | interrupts = <17>; | |
| 209 | fifosize = <128>; | |
| 210 | clocks = <&clks 13>; | |
| a1369978 QL |
211 | sirf,uart-dma-rx-channel = <21>; |
| 212 | sirf,uart-dma-tx-channel = <2>; | |
| 5fa2f9af BS |
213 | }; |
| 214 | ||
| 215 | uart1: uart@b0060000 { | |
| 216 | cell-index = <1>; | |
| 217 | compatible = "sirf,prima2-uart"; | |
| 218 | reg = <0xb0060000 0x1000>; | |
| 219 | interrupts = <18>; | |
| 220 | fifosize = <32>; | |
| 221 | clocks = <&clks 14>; | |
| 222 | }; | |
| 223 | ||
| 224 | uart2: uart@b0070000 { | |
| 225 | cell-index = <2>; | |
| 226 | compatible = "sirf,prima2-uart"; | |
| 227 | reg = <0xb0070000 0x1000>; | |
| 228 | interrupts = <19>; | |
| 229 | fifosize = <128>; | |
| 230 | clocks = <&clks 15>; | |
| a1369978 QL |
231 | sirf,uart-dma-rx-channel = <6>; |
| 232 | sirf,uart-dma-tx-channel = <7>; | |
| 5fa2f9af BS |
233 | }; |
| 234 | ||
| 235 | usp0: usp@b0080000 { | |
| 236 | cell-index = <0>; | |
| 237 | compatible = "sirf,prima2-usp"; | |
| 238 | reg = <0xb0080000 0x10000>; | |
| 239 | interrupts = <20>; | |
| a1369978 | 240 | fifosize = <128>; |
| 5fa2f9af | 241 | clocks = <&clks 28>; |
| a1369978 QL |
242 | sirf,usp-dma-rx-channel = <17>; |
| 243 | sirf,usp-dma-tx-channel = <18>; | |
| 5fa2f9af BS |
244 | }; |
| 245 | ||
| 246 | usp1: usp@b0090000 { | |
| 247 | cell-index = <1>; | |
| 248 | compatible = "sirf,prima2-usp"; | |
| 249 | reg = <0xb0090000 0x10000>; | |
| 250 | interrupts = <21>; | |
| a1369978 | 251 | fifosize = <128>; |
| 5fa2f9af | 252 | clocks = <&clks 29>; |
| a1369978 QL |
253 | sirf,usp-dma-rx-channel = <14>; |
| 254 | sirf,usp-dma-tx-channel = <15>; | |
| 5fa2f9af BS |
255 | }; |
| 256 | ||
| 257 | dmac0: dma-controller@b00b0000 { | |
| 258 | cell-index = <0>; | |
| 259 | compatible = "sirf,prima2-dmac"; | |
| 260 | reg = <0xb00b0000 0x10000>; | |
| 261 | interrupts = <12>; | |
| 262 | clocks = <&clks 24>; | |
| 263 | }; | |
| 264 | ||
| 265 | dmac1: dma-controller@b0160000 { | |
| 266 | cell-index = <1>; | |
| 267 | compatible = "sirf,prima2-dmac"; | |
| 268 | reg = <0xb0160000 0x10000>; | |
| 269 | interrupts = <13>; | |
| 270 | clocks = <&clks 25>; | |
| 271 | }; | |
| 272 | ||
| 273 | vip@b00C0000 { | |
| 274 | compatible = "sirf,prima2-vip"; | |
| 275 | reg = <0xb00C0000 0x10000>; | |
| 276 | clocks = <&clks 31>; | |
| 262bcc1d RW |
277 | interrupts = <14>; |
| 278 | sirf,vip-dma-rx-channel = <16>; | |
| 5fa2f9af BS |
279 | }; |
| 280 | ||
| 281 | spi0: spi@b00d0000 { | |
| 282 | cell-index = <0>; | |
| 283 | compatible = "sirf,prima2-spi"; | |
| 284 | reg = <0xb00d0000 0x10000>; | |
| 285 | interrupts = <15>; | |
| 286 | sirf,spi-num-chipselects = <1>; | |
| 287 | cs-gpios = <&gpio 0 0>; | |
| 288 | sirf,spi-dma-rx-channel = <25>; | |
| 289 | sirf,spi-dma-tx-channel = <20>; | |
| 290 | #address-cells = <1>; | |
| 291 | #size-cells = <0>; | |
| 292 | clocks = <&clks 19>; | |
| 293 | status = "disabled"; | |
| 294 | }; | |
| 295 | ||
| 296 | spi1: spi@b0170000 { | |
| 297 | cell-index = <1>; | |
| 298 | compatible = "sirf,prima2-spi"; | |
| 299 | reg = <0xb0170000 0x10000>; | |
| 300 | interrupts = <16>; | |
| 6f425115 BS |
301 | sirf,spi-num-chipselects = <1>; |
| 302 | sirf,spi-dma-rx-channel = <12>; | |
| 303 | sirf,spi-dma-tx-channel = <13>; | |
| 304 | #address-cells = <1>; | |
| 305 | #size-cells = <0>; | |
| 5fa2f9af BS |
306 | clocks = <&clks 20>; |
| 307 | status = "disabled"; | |
| 308 | }; | |
| 309 | ||
| 310 | i2c0: i2c@b00e0000 { | |
| 311 | cell-index = <0>; | |
| 312 | compatible = "sirf,prima2-i2c"; | |
| 313 | reg = <0xb00e0000 0x10000>; | |
| 314 | interrupts = <24>; | |
| 315 | #address-cells = <1>; | |
| 316 | #size-cells = <0>; | |
| 317 | clocks = <&clks 17>; | |
| 318 | }; | |
| 319 | ||
| 320 | i2c1: i2c@b00f0000 { | |
| 321 | cell-index = <1>; | |
| 322 | compatible = "sirf,prima2-i2c"; | |
| 323 | reg = <0xb00f0000 0x10000>; | |
| 324 | interrupts = <25>; | |
| 325 | #address-cells = <1>; | |
| 326 | #size-cells = <0>; | |
| 327 | clocks = <&clks 18>; | |
| 328 | }; | |
| 329 | ||
| 330 | tsc@b0110000 { | |
| 331 | compatible = "sirf,prima2-tsc"; | |
| 332 | reg = <0xb0110000 0x10000>; | |
| 333 | interrupts = <33>; | |
| 334 | clocks = <&clks 16>; | |
| 335 | }; | |
| 336 | ||
| 337 | gpio: pinctrl@b0120000 { | |
| 338 | #gpio-cells = <2>; | |
| 339 | #interrupt-cells = <2>; | |
| 340 | compatible = "sirf,atlas6-pinctrl"; | |
| 341 | reg = <0xb0120000 0x10000>; | |
| 342 | interrupts = <43 44 45 46 47>; | |
| 343 | gpio-controller; | |
| 344 | interrupt-controller; | |
| 345 | ||
| 346 | lcd_16pins_a: lcd0@0 { | |
| 347 | lcd { | |
| 348 | sirf,pins = "lcd_16bitsgrp"; | |
| 349 | sirf,function = "lcd_16bits"; | |
| 350 | }; | |
| 351 | }; | |
| 352 | lcd_18pins_a: lcd0@1 { | |
| 353 | lcd { | |
| 354 | sirf,pins = "lcd_18bitsgrp"; | |
| 355 | sirf,function = "lcd_18bits"; | |
| 356 | }; | |
| 357 | }; | |
| 358 | lcd_24pins_a: lcd0@2 { | |
| 359 | lcd { | |
| 360 | sirf,pins = "lcd_24bitsgrp"; | |
| 361 | sirf,function = "lcd_24bits"; | |
| 362 | }; | |
| 363 | }; | |
| 364 | lcdrom_pins_a: lcdrom0@0 { | |
| 365 | lcd { | |
| 366 | sirf,pins = "lcdromgrp"; | |
| 367 | sirf,function = "lcdrom"; | |
| 368 | }; | |
| 369 | }; | |
| 370 | uart0_pins_a: uart0@0 { | |
| 371 | uart { | |
| 372 | sirf,pins = "uart0grp"; | |
| 373 | sirf,function = "uart0"; | |
| 374 | }; | |
| 375 | }; | |
| 031b8ce0 QL |
376 | uart0_noflow_pins_a: uart0@1 { |
| 377 | uart { | |
| 378 | sirf,pins = "uart0_nostreamctrlgrp"; | |
| 379 | sirf,function = "uart0_nostreamctrl"; | |
| 380 | }; | |
| 381 | }; | |
| 5fa2f9af BS |
382 | uart1_pins_a: uart1@0 { |
| 383 | uart { | |
| 384 | sirf,pins = "uart1grp"; | |
| 385 | sirf,function = "uart1"; | |
| 386 | }; | |
| 387 | }; | |
| 388 | uart2_pins_a: uart2@0 { | |
| 389 | uart { | |
| 390 | sirf,pins = "uart2grp"; | |
| 391 | sirf,function = "uart2"; | |
| 392 | }; | |
| 393 | }; | |
| 394 | uart2_noflow_pins_a: uart2@1 { | |
| 395 | uart { | |
| 396 | sirf,pins = "uart2_nostreamctrlgrp"; | |
| 397 | sirf,function = "uart2_nostreamctrl"; | |
| 398 | }; | |
| 399 | }; | |
| 400 | spi0_pins_a: spi0@0 { | |
| 401 | spi { | |
| 402 | sirf,pins = "spi0grp"; | |
| 403 | sirf,function = "spi0"; | |
| 404 | }; | |
| 405 | }; | |
| 406 | spi1_pins_a: spi1@0 { | |
| 407 | spi { | |
| 408 | sirf,pins = "spi1grp"; | |
| 409 | sirf,function = "spi1"; | |
| 410 | }; | |
| 411 | }; | |
| 412 | i2c0_pins_a: i2c0@0 { | |
| 413 | i2c { | |
| 414 | sirf,pins = "i2c0grp"; | |
| 415 | sirf,function = "i2c0"; | |
| 416 | }; | |
| 417 | }; | |
| 418 | i2c1_pins_a: i2c1@0 { | |
| 419 | i2c { | |
| 420 | sirf,pins = "i2c1grp"; | |
| 421 | sirf,function = "i2c1"; | |
| 422 | }; | |
| 423 | }; | |
| 424 | pwm0_pins_a: pwm0@0 { | |
| 425 | pwm { | |
| 426 | sirf,pins = "pwm0grp"; | |
| 427 | sirf,function = "pwm0"; | |
| 428 | }; | |
| 429 | }; | |
| 430 | pwm1_pins_a: pwm1@0 { | |
| 431 | pwm { | |
| 432 | sirf,pins = "pwm1grp"; | |
| 433 | sirf,function = "pwm1"; | |
| 434 | }; | |
| 435 | }; | |
| 436 | pwm2_pins_a: pwm2@0 { | |
| 437 | pwm { | |
| 438 | sirf,pins = "pwm2grp"; | |
| 439 | sirf,function = "pwm2"; | |
| 440 | }; | |
| 441 | }; | |
| 442 | pwm3_pins_a: pwm3@0 { | |
| 443 | pwm { | |
| 444 | sirf,pins = "pwm3grp"; | |
| 445 | sirf,function = "pwm3"; | |
| 446 | }; | |
| 447 | }; | |
| 448 | pwm4_pins_a: pwm4@0 { | |
| 449 | pwm { | |
| 450 | sirf,pins = "pwm4grp"; | |
| 451 | sirf,function = "pwm4"; | |
| 452 | }; | |
| 453 | }; | |
| 454 | gps_pins_a: gps@0 { | |
| 455 | gps { | |
| 456 | sirf,pins = "gpsgrp"; | |
| 457 | sirf,function = "gps"; | |
| 458 | }; | |
| 459 | }; | |
| 460 | vip_pins_a: vip@0 { | |
| 461 | vip { | |
| 462 | sirf,pins = "vipgrp"; | |
| 463 | sirf,function = "vip"; | |
| 464 | }; | |
| 465 | }; | |
| 466 | sdmmc0_pins_a: sdmmc0@0 { | |
| 467 | sdmmc0 { | |
| 468 | sirf,pins = "sdmmc0grp"; | |
| 469 | sirf,function = "sdmmc0"; | |
| 470 | }; | |
| 471 | }; | |
| 472 | sdmmc1_pins_a: sdmmc1@0 { | |
| 473 | sdmmc1 { | |
| 474 | sirf,pins = "sdmmc1grp"; | |
| 475 | sirf,function = "sdmmc1"; | |
| 476 | }; | |
| 477 | }; | |
| 478 | sdmmc2_pins_a: sdmmc2@0 { | |
| 479 | sdmmc2 { | |
| 480 | sirf,pins = "sdmmc2grp"; | |
| 481 | sirf,function = "sdmmc2"; | |
| 482 | }; | |
| 483 | }; | |
| 484 | sdmmc2_nowp_pins_a: sdmmc2_nowp@0 { | |
| 485 | sdmmc2_nowp { | |
| 486 | sirf,pins = "sdmmc2_nowpgrp"; | |
| 487 | sirf,function = "sdmmc2_nowp"; | |
| 488 | }; | |
| 489 | }; | |
| 490 | sdmmc3_pins_a: sdmmc3@0 { | |
| 491 | sdmmc3 { | |
| 492 | sirf,pins = "sdmmc3grp"; | |
| 493 | sirf,function = "sdmmc3"; | |
| 494 | }; | |
| 495 | }; | |
| 496 | sdmmc5_pins_a: sdmmc5@0 { | |
| 497 | sdmmc5 { | |
| 498 | sirf,pins = "sdmmc5grp"; | |
| 499 | sirf,function = "sdmmc5"; | |
| 500 | }; | |
| 501 | }; | |
| 502 | i2s_pins_a: i2s@0 { | |
| 503 | i2s { | |
| 504 | sirf,pins = "i2sgrp"; | |
| 505 | sirf,function = "i2s"; | |
| 506 | }; | |
| 507 | }; | |
| 508 | i2s_no_din_pins_a: i2s_no_din@0 { | |
| 509 | i2s_no_din { | |
| 510 | sirf,pins = "i2s_no_dingrp"; | |
| 511 | sirf,function = "i2s_no_din"; | |
| 512 | }; | |
| 513 | }; | |
| 514 | i2s_6chn_pins_a: i2s_6chn@0 { | |
| 515 | i2s_6chn { | |
| 516 | sirf,pins = "i2s_6chngrp"; | |
| 517 | sirf,function = "i2s_6chn"; | |
| 518 | }; | |
| 519 | }; | |
| 520 | ac97_pins_a: ac97@0 { | |
| 521 | ac97 { | |
| 522 | sirf,pins = "ac97grp"; | |
| 523 | sirf,function = "ac97"; | |
| 524 | }; | |
| 525 | }; | |
| 526 | nand_pins_a: nand@0 { | |
| 527 | nand { | |
| 528 | sirf,pins = "nandgrp"; | |
| 529 | sirf,function = "nand"; | |
| 530 | }; | |
| 531 | }; | |
| 532 | usp0_pins_a: usp0@0 { | |
| 533 | usp0 { | |
| 534 | sirf,pins = "usp0grp"; | |
| 535 | sirf,function = "usp0"; | |
| 536 | }; | |
| 537 | }; | |
| d58e9a02 QL |
538 | usp0_uart_nostreamctrl_pins_a: usp0@1 { |
| 539 | usp0 { | |
| 540 | sirf,pins = "usp0_uart_nostreamctrl_grp"; | |
| 541 | sirf,function = "usp0_uart_nostreamctrl"; | |
| 542 | }; | |
| 543 | }; | |
| 5fa2f9af BS |
544 | usp1_pins_a: usp1@0 { |
| 545 | usp1 { | |
| 546 | sirf,pins = "usp1grp"; | |
| 547 | sirf,function = "usp1"; | |
| 548 | }; | |
| 549 | }; | |
| 550 | usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 { | |
| 551 | usb0_upli_drvbus { | |
| 552 | sirf,pins = "usb0_upli_drvbusgrp"; | |
| 553 | sirf,function = "usb0_upli_drvbus"; | |
| 554 | }; | |
| 555 | }; | |
| 556 | usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { | |
| 557 | usb1_utmi_drvbus { | |
| 558 | sirf,pins = "usb1_utmi_drvbusgrp"; | |
| 559 | sirf,function = "usb1_utmi_drvbus"; | |
| 560 | }; | |
| 561 | }; | |
| 6a08a92e RW |
562 | usb1_dp_dn_pins_a: usb1_dp_dn@0 { |
| 563 | usb1_dp_dn { | |
| 564 | sirf,pins = "usb1_dp_dngrp"; | |
| 565 | sirf,function = "usb1_dp_dn"; | |
| 566 | }; | |
| 567 | }; | |
| 568 | uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 { | |
| 569 | uart1_route_io_usb1 { | |
| 570 | sirf,pins = "uart1_route_io_usb1grp"; | |
| 571 | sirf,function = "uart1_route_io_usb1"; | |
| 572 | }; | |
| 573 | }; | |
| 5fa2f9af BS |
574 | warm_rst_pins_a: warm_rst@0 { |
| 575 | warm_rst { | |
| 576 | sirf,pins = "warm_rstgrp"; | |
| 577 | sirf,function = "warm_rst"; | |
| 578 | }; | |
| 579 | }; | |
| 580 | pulse_count_pins_a: pulse_count@0 { | |
| 581 | pulse_count { | |
| 582 | sirf,pins = "pulse_countgrp"; | |
| 583 | sirf,function = "pulse_count"; | |
| 584 | }; | |
| 585 | }; | |
| c8078de8 BS |
586 | cko0_pins_a: cko0@0 { |
| 587 | cko0 { | |
| 588 | sirf,pins = "cko0grp"; | |
| 589 | sirf,function = "cko0"; | |
| 5fa2f9af BS |
590 | }; |
| 591 | }; | |
| c8078de8 BS |
592 | cko1_pins_a: cko1@0 { |
| 593 | cko1 { | |
| 594 | sirf,pins = "cko1grp"; | |
| 595 | sirf,function = "cko1"; | |
| 5fa2f9af BS |
596 | }; |
| 597 | }; | |
| 598 | }; | |
| 599 | ||
| 600 | pwm@b0130000 { | |
| 601 | compatible = "sirf,prima2-pwm"; | |
| 602 | reg = <0xb0130000 0x10000>; | |
| 603 | clocks = <&clks 21>; | |
| 604 | }; | |
| 605 | ||
| 606 | efusesys@b0140000 { | |
| 607 | compatible = "sirf,prima2-efuse"; | |
| 608 | reg = <0xb0140000 0x10000>; | |
| 609 | clocks = <&clks 22>; | |
| 610 | }; | |
| 611 | ||
| 612 | pulsec@b0150000 { | |
| 613 | compatible = "sirf,prima2-pulsec"; | |
| 614 | reg = <0xb0150000 0x10000>; | |
| 615 | interrupts = <48>; | |
| 616 | clocks = <&clks 23>; | |
| 617 | }; | |
| 618 | ||
| 619 | pci-iobg { | |
| 620 | compatible = "sirf,prima2-pciiobg", "simple-bus"; | |
| 621 | #address-cells = <1>; | |
| 622 | #size-cells = <1>; | |
| 623 | ranges = <0x56000000 0x56000000 0x1b00000>; | |
| 624 | ||
| 625 | sd0: sdhci@56000000 { | |
| 626 | cell-index = <0>; | |
| 627 | compatible = "sirf,prima2-sdhc"; | |
| 628 | reg = <0x56000000 0x100000>; | |
| 629 | interrupts = <38>; | |
| 630 | bus-width = <8>; | |
| 631 | clocks = <&clks 36>; | |
| 632 | }; | |
| 633 | ||
| 634 | sd1: sdhci@56100000 { | |
| 635 | cell-index = <1>; | |
| 636 | compatible = "sirf,prima2-sdhc"; | |
| 637 | reg = <0x56100000 0x100000>; | |
| 638 | interrupts = <38>; | |
| 639 | status = "disabled"; | |
| 7f97c303 | 640 | bus-width = <4>; |
| 5fa2f9af BS |
641 | clocks = <&clks 36>; |
| 642 | }; | |
| 643 | ||
| 644 | sd2: sdhci@56200000 { | |
| 645 | cell-index = <2>; | |
| 646 | compatible = "sirf,prima2-sdhc"; | |
| 647 | reg = <0x56200000 0x100000>; | |
| 648 | interrupts = <23>; | |
| 649 | status = "disabled"; | |
| 7f97c303 | 650 | bus-width = <4>; |
| 5fa2f9af BS |
651 | clocks = <&clks 37>; |
| 652 | }; | |
| 653 | ||
| 654 | sd3: sdhci@56300000 { | |
| 655 | cell-index = <3>; | |
| 656 | compatible = "sirf,prima2-sdhc"; | |
| 657 | reg = <0x56300000 0x100000>; | |
| 658 | interrupts = <23>; | |
| 659 | status = "disabled"; | |
| 7f97c303 | 660 | bus-width = <4>; |
| 5fa2f9af BS |
661 | clocks = <&clks 37>; |
| 662 | }; | |
| 663 | ||
| 664 | sd5: sdhci@56500000 { | |
| 665 | cell-index = <5>; | |
| 666 | compatible = "sirf,prima2-sdhc"; | |
| 667 | reg = <0x56500000 0x100000>; | |
| 668 | interrupts = <39>; | |
| 669 | status = "disabled"; | |
| 7f97c303 | 670 | bus-width = <4>; |
| 5fa2f9af BS |
671 | clocks = <&clks 38>; |
| 672 | }; | |
| 673 | ||
| 674 | pci-copy@57900000 { | |
| 675 | compatible = "sirf,prima2-pcicp"; | |
| 676 | reg = <0x57900000 0x100000>; | |
| 677 | interrupts = <40>; | |
| 678 | }; | |
| 679 | ||
| 680 | rom-interface@57a00000 { | |
| 681 | compatible = "sirf,prima2-romif"; | |
| 682 | reg = <0x57a00000 0x100000>; | |
| 683 | }; | |
| 684 | }; | |
| 685 | }; | |
| 686 | ||
| 687 | rtc-iobg { | |
| e88b815e | 688 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; |
| 5fa2f9af BS |
689 | #address-cells = <1>; |
| 690 | #size-cells = <1>; | |
| 691 | reg = <0x80030000 0x10000>; | |
| 692 | ||
| 693 | gpsrtc@1000 { | |
| 694 | compatible = "sirf,prima2-gpsrtc"; | |
| 695 | reg = <0x1000 0x1000>; | |
| 696 | interrupts = <55 56 57>; | |
| 697 | }; | |
| 698 | ||
| 699 | sysrtc@2000 { | |
| 700 | compatible = "sirf,prima2-sysrtc"; | |
| 701 | reg = <0x2000 0x1000>; | |
| 702 | interrupts = <52 53 54>; | |
| 703 | }; | |
| 704 | ||
| 705 | pwrc@3000 { | |
| 706 | compatible = "sirf,prima2-pwrc"; | |
| 707 | reg = <0x3000 0x1000>; | |
| 708 | interrupts = <32>; | |
| 709 | }; | |
| 710 | }; | |
| 711 | ||
| 712 | uus-iobg { | |
| 713 | compatible = "simple-bus"; | |
| 714 | #address-cells = <1>; | |
| 715 | #size-cells = <1>; | |
| 716 | ranges = <0xb8000000 0xb8000000 0x40000>; | |
| 717 | ||
| 718 | usb0: usb@b00e0000 { | |
| 719 | compatible = "chipidea,ci13611a-prima2"; | |
| 720 | reg = <0xb8000000 0x10000>; | |
| 721 | interrupts = <10>; | |
| 722 | clocks = <&clks 40>; | |
| 723 | }; | |
| 724 | ||
| 725 | usb1: usb@b00f0000 { | |
| 726 | compatible = "chipidea,ci13611a-prima2"; | |
| 727 | reg = <0xb8010000 0x10000>; | |
| 728 | interrupts = <11>; | |
| 729 | clocks = <&clks 41>; | |
| 730 | }; | |
| 731 | ||
| 732 | security@b00f0000 { | |
| 733 | compatible = "sirf,prima2-security"; | |
| 734 | reg = <0xb8030000 0x10000>; | |
| 735 | interrupts = <42>; | |
| 736 | clocks = <&clks 7>; | |
| 737 | }; | |
| 738 | }; | |
| 739 | }; | |
| 740 | }; |