[deliverable/linux.git] / arch / arm / boot / dts / bcm-cygnus.dtsi

/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

#include "skeleton.dtsi"

/ {
	compatible = "brcm,cygnus";
	model = "Broadcom Cygnus SoC";
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
		};
	};

	/include/ "bcm-cygnus-clock.dtsi"

	pinctrl: pinctrl@0x0301d0c8 {
		compatible = "brcm,cygnus-pinmux";
		reg = <0x0301d0c8 0x30>,
		      <0x0301d24c 0x2c>;
	};

	gpio_crmu: gpio@03024800 {
		compatible = "brcm,cygnus-crmu-gpio";
		reg = <0x03024800 0x50>,
		      <0x03024008 0x18>;
		#gpio-cells = <2>;
		gpio-controller;
	};

	gpio_ccm: gpio@1800a000 {
		compatible = "brcm,cygnus-ccm-gpio";
		reg = <0x1800a000 0x50>,
		      <0x0301d164 0x20>;
		#gpio-cells = <2>;
		gpio-controller;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
	};

	gpio_asiu: gpio@180a5000 {
		compatible = "brcm,cygnus-asiu-gpio";
		reg = <0x180a5000 0x668>;
		#gpio-cells = <2>;
		gpio-controller;

		pinmux = <&pinctrl>;

		interrupt-controller;
		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	};

	amba {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "arm,amba-bus", "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		wdt@18009000 {
			 compatible = "arm,sp805" , "arm,primecell";
			 reg = <0x18009000 0x1000>;
			 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			 clocks = <&axi81_clk>;
			 clock-names = "apb_pclk";
		};
	};

	i2c0: i2c@18008000 {
		compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
		reg = <0x18008000 0x100>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
		clock-frequency = <100000>;
		status = "disabled";
	};

	i2c1: i2c@1800b000 {
		compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
		reg = <0x1800b000 0x100>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
		clock-frequency = <100000>;
		status = "disabled";
	};

	uart0: serial@18020000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x18020000 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&axi81_clk>;
		clock-frequency = <100000000>;
		status = "disabled";
	};

	uart1: serial@18021000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x18021000 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&axi81_clk>;
		clock-frequency = <100000000>;
		status = "disabled";
	};

	uart2: serial@18022000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x18020000 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&axi81_clk>;
		clock-frequency = <100000000>;
		status = "disabled";
	};

	uart3: serial@18023000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x18023000 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&axi81_clk>;
		clock-frequency = <100000000>;
		status = "disabled";
	};

	gic: interrupt-controller@19021000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x19021000 0x1000>,
		      <0x19020100 0x100>;
	};

	L2: l2-cache {
		compatible = "arm,pl310-cache";
		reg = <0x19022000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};

	timer@19020200 {
		compatible = "arm,cortex-a9-global-timer";
		reg = <0x19020200 0x100>;
		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&periph_clk>;
	};

};
Commit	Line	Data
c9ad7bc5 SB	1	/*
	2	* BSD LICENSE
	3	*
	4	* Copyright(c) 2014 Broadcom Corporation. All rights reserved.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	*
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in
	14	* the documentation and/or other materials provided with the
	15	* distribution.
	16	* * Neither the name of Broadcom Corporation nor the names of its
	17	* contributors may be used to endorse or promote products derived
	18	* from this software without specific prior written permission.
	19	*
	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	21	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	22	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	23	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	24	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	25	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	26	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	27	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	28	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	30	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*/
	32
	33	#include <dt-bindings/interrupt-controller/arm-gic.h>
	34	#include <dt-bindings/interrupt-controller/irq.h>
	35
	36	#include "skeleton.dtsi"
	37
	38	/ {
	39	compatible = "brcm,cygnus";
	40	model = "Broadcom Cygnus SoC";
	41	interrupt-parent = <&gic>;
	42
	43	cpus {
	44	#address-cells = <1>;
	45	#size-cells = <0>;
	46
	47	cpu@0 {
	48	device_type = "cpu";
	49	compatible = "arm,cortex-a9";
	50	next-level-cache = <&L2>;
	51	reg = <0x0>;
	52	};
	53	};
	54
	55	/include/ "bcm-cygnus-clock.dtsi"
	56
e6a4e5d5 RJ	57	pinctrl: pinctrl@0x0301d0c8 {
	58	compatible = "brcm,cygnus-pinmux";
	59	reg = <0x0301d0c8 0x30>,
	60	<0x0301d24c 0x2c>;
	61	};
	62
5fa4b29c RJ	63	gpio_crmu: gpio@03024800 {
	64	compatible = "brcm,cygnus-crmu-gpio";
	65	reg = <0x03024800 0x50>,
	66	<0x03024008 0x18>;
	67	#gpio-cells = <2>;
	68	gpio-controller;
	69	};
	70
	71	gpio_ccm: gpio@1800a000 {
	72	compatible = "brcm,cygnus-ccm-gpio";
	73	reg = <0x1800a000 0x50>,
	74	<0x0301d164 0x20>;
	75	#gpio-cells = <2>;
	76	gpio-controller;
	77	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	78	interrupt-controller;
	79	};
	80
	81	gpio_asiu: gpio@180a5000 {
	82	compatible = "brcm,cygnus-asiu-gpio";
	83	reg = <0x180a5000 0x668>;
	84	#gpio-cells = <2>;
	85	gpio-controller;
	86
	87	pinmux = <&pinctrl>;
	88
	89	interrupt-controller;
	90	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	91	};
	92
c9ad7bc5 SB	93	amba {
	94	#address-cells = <1>;
	95	#size-cells = <1>;
	96	compatible = "arm,amba-bus", "simple-bus";
	97	interrupt-parent = <&gic>;
	98	ranges;
	99
	100	wdt@18009000 {
	101	compatible = "arm,sp805" , "arm,primecell";
	102	reg = <0x18009000 0x1000>;
	103	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	104	clocks = <&axi81_clk>;
	105	clock-names = "apb_pclk";
	106	};
	107	};
	108
b51c05a3 RJ	109	i2c0: i2c@18008000 {
	110	compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
	111	reg = <0x18008000 0x100>;
	112	#address-cells = <1>;
	113	#size-cells = <0>;
	114	interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
	115	clock-frequency = <100000>;
	116	status = "disabled";
	117	};
	118
	119	i2c1: i2c@1800b000 {
	120	compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
	121	reg = <0x1800b000 0x100>;
	122	#address-cells = <1>;
	123	#size-cells = <0>;
	124	interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
	125	clock-frequency = <100000>;
	126	status = "disabled";
	127	};
	128
c9ad7bc5 SB	129	uart0: serial@18020000 {
	130	compatible = "snps,dw-apb-uart";
	131	reg = <0x18020000 0x100>;
	132	reg-shift = <2>;
	133	reg-io-width = <4>;
	134	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	135	clocks = <&axi81_clk>;
	136	clock-frequency = <100000000>;
	137	status = "disabled";
	138	};
	139
	140	uart1: serial@18021000 {
	141	compatible = "snps,dw-apb-uart";
	142	reg = <0x18021000 0x100>;
	143	reg-shift = <2>;
	144	reg-io-width = <4>;
	145	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	146	clocks = <&axi81_clk>;
	147	clock-frequency = <100000000>;
	148	status = "disabled";
	149	};
	150
	151	uart2: serial@18022000 {
	152	compatible = "snps,dw-apb-uart";
	153	reg = <0x18020000 0x100>;
	154	reg-shift = <2>;
	155	reg-io-width = <4>;
	156	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	157	clocks = <&axi81_clk>;
	158	clock-frequency = <100000000>;
	159	status = "disabled";
	160	};
	161
	162	uart3: serial@18023000 {
	163	compatible = "snps,dw-apb-uart";
	164	reg = <0x18023000 0x100>;
	165	reg-shift = <2>;
	166	reg-io-width = <4>;
	167	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	168	clocks = <&axi81_clk>;
	169	clock-frequency = <100000000>;
	170	status = "disabled";
	171	};
	172
	173	gic: interrupt-controller@19021000 {
	174	compatible = "arm,cortex-a9-gic";
	175	#interrupt-cells = <3>;
	176	#address-cells = <0>;
	177	interrupt-controller;
	178	reg = <0x19021000 0x1000>,
	179	<0x19020100 0x100>;
	180	};
	181
	182	L2: l2-cache {
	183	compatible = "arm,pl310-cache";
	184	reg = <0x19022000 0x1000>;
	185	cache-unified;
	186	cache-level = <2>;
	187	};
	188
	189	timer@19020200 {
	190	compatible = "arm,cortex-a9-global-timer";
	191	reg = <0x19020200 0x100>;
	192	interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
193	clocks = <&periph_clk>;
194	};
195
196	};