projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| c9ad7bc5 SB |
1 | /* |
| 2 | * BSD LICENSE | |
| 3 | * | |
| 4 | * Copyright(c) 2014 Broadcom Corporation. All rights reserved. | |
| 5 | * | |
| 6 | * Redistribution and use in source and binary forms, with or without | |
| 7 | * modification, are permitted provided that the following conditions | |
| 8 | * are met: | |
| 9 | * | |
| 10 | * * Redistributions of source code must retain the above copyright | |
| 11 | * notice, this list of conditions and the following disclaimer. | |
| 12 | * * Redistributions in binary form must reproduce the above copyright | |
| 13 | * notice, this list of conditions and the following disclaimer in | |
| 14 | * the documentation and/or other materials provided with the | |
| 15 | * distribution. | |
| 16 | * * Neither the name of Broadcom Corporation nor the names of its | |
| 17 | * contributors may be used to endorse or promote products derived | |
| 18 | * from this software without specific prior written permission. | |
| 19 | * | |
| 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 21 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 22 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| 23 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 24 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| 25 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| 26 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| 27 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| 28 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 30 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 31 | */ | |
| 32 | ||
| 33 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 34 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 35 | ||
| 36 | #include "skeleton.dtsi" | |
| 37 | ||
| 38 | / { | |
| 39 | compatible = "brcm,cygnus"; | |
| 40 | model = "Broadcom Cygnus SoC"; | |
| 41 | interrupt-parent = <&gic>; | |
| 42 | ||
| 43 | cpus { | |
| 44 | #address-cells = <1>; | |
| 45 | #size-cells = <0>; | |
| 46 | ||
| 47 | cpu@0 { | |
| 48 | device_type = "cpu"; | |
| 49 | compatible = "arm,cortex-a9"; | |
| 50 | next-level-cache = <&L2>; | |
| 51 | reg = <0x0>; | |
| 52 | }; | |
| 53 | }; | |
| 54 | ||
| 55 | /include/ "bcm-cygnus-clock.dtsi" | |
| 56 | ||
| e6a4e5d5 RJ |
57 | pinctrl: pinctrl@0x0301d0c8 { |
| 58 | compatible = "brcm,cygnus-pinmux"; | |
| 59 | reg = <0x0301d0c8 0x30>, | |
| 60 | <0x0301d24c 0x2c>; | |
| 61 | }; | |
| 62 | ||
| 5fa4b29c RJ |
63 | gpio_crmu: gpio@03024800 { |
| 64 | compatible = "brcm,cygnus-crmu-gpio"; | |
| 65 | reg = <0x03024800 0x50>, | |
| 66 | <0x03024008 0x18>; | |
| 67 | #gpio-cells = <2>; | |
| 68 | gpio-controller; | |
| 69 | }; | |
| 70 | ||
| 71 | gpio_ccm: gpio@1800a000 { | |
| 72 | compatible = "brcm,cygnus-ccm-gpio"; | |
| 73 | reg = <0x1800a000 0x50>, | |
| 74 | <0x0301d164 0x20>; | |
| 75 | #gpio-cells = <2>; | |
| 76 | gpio-controller; | |
| 77 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
| 78 | interrupt-controller; | |
| 79 | }; | |
| 80 | ||
| 81 | gpio_asiu: gpio@180a5000 { | |
| 82 | compatible = "brcm,cygnus-asiu-gpio"; | |
| 83 | reg = <0x180a5000 0x668>; | |
| 84 | #gpio-cells = <2>; | |
| 85 | gpio-controller; | |
| 86 | ||
| 87 | pinmux = <&pinctrl>; | |
| 88 | ||
| 89 | interrupt-controller; | |
| 90 | interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; | |
| 91 | }; | |
| 92 | ||
| c9ad7bc5 SB |
93 | amba { |
| 94 | #address-cells = <1>; | |
| 95 | #size-cells = <1>; | |
| 96 | compatible = "arm,amba-bus", "simple-bus"; | |
| 97 | interrupt-parent = <&gic>; | |
| 98 | ranges; | |
| 99 | ||
| 100 | wdt@18009000 { | |
| 101 | compatible = "arm,sp805" , "arm,primecell"; | |
| 102 | reg = <0x18009000 0x1000>; | |
| 103 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
| 104 | clocks = <&axi81_clk>; | |
| 105 | clock-names = "apb_pclk"; | |
| 106 | }; | |
| 107 | }; | |
| 108 | ||
| b51c05a3 RJ |
109 | i2c0: i2c@18008000 { |
| 110 | compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; | |
| 111 | reg = <0x18008000 0x100>; | |
| 112 | #address-cells = <1>; | |
| 113 | #size-cells = <0>; | |
| 114 | interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>; | |
| 115 | clock-frequency = <100000>; | |
| 116 | status = "disabled"; | |
| 117 | }; | |
| 118 | ||
| 119 | i2c1: i2c@1800b000 { | |
| 120 | compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; | |
| 121 | reg = <0x1800b000 0x100>; | |
| 122 | #address-cells = <1>; | |
| 123 | #size-cells = <0>; | |
| 124 | interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>; | |
| 125 | clock-frequency = <100000>; | |
| 126 | status = "disabled"; | |
| 127 | }; | |
| 128 | ||
| cd590b50 RJ |
129 | pcie0: pcie@18012000 { |
| 130 | compatible = "brcm,iproc-pcie"; | |
| 131 | reg = <0x18012000 0x1000>; | |
| 132 | ||
| 133 | #interrupt-cells = <1>; | |
| 134 | interrupt-map-mask = <0 0 0 0>; | |
| 135 | interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; | |
| 136 | ||
| 137 | linux,pci-domain = <0>; | |
| 138 | ||
| 139 | bus-range = <0x00 0xff>; | |
| 140 | ||
| 141 | #address-cells = <3>; | |
| 142 | #size-cells = <2>; | |
| 143 | device_type = "pci"; | |
| 144 | ranges = <0x81000000 0 0 0x28000000 0 0x00010000 | |
| 145 | 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; | |
| 146 | ||
| 147 | status = "disabled"; | |
| 148 | }; | |
| 149 | ||
| 150 | pcie1: pcie@18013000 { | |
| 151 | compatible = "brcm,iproc-pcie"; | |
| 152 | reg = <0x18013000 0x1000>; | |
| 153 | ||
| 154 | #interrupt-cells = <1>; | |
| 155 | interrupt-map-mask = <0 0 0 0>; | |
| 156 | interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; | |
| 157 | ||
| 158 | linux,pci-domain = <1>; | |
| 159 | ||
| 160 | bus-range = <0x00 0xff>; | |
| 161 | ||
| 162 | #address-cells = <3>; | |
| 163 | #size-cells = <2>; | |
| 164 | device_type = "pci"; | |
| 165 | ranges = <0x81000000 0 0 0x48000000 0 0x00010000 | |
| 166 | 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; | |
| 167 | ||
| 168 | status = "disabled"; | |
| 169 | }; | |
| 170 | ||
| c9ad7bc5 SB |
171 | uart0: serial@18020000 { |
| 172 | compatible = "snps,dw-apb-uart"; | |
| 173 | reg = <0x18020000 0x100>; | |
| 174 | reg-shift = <2>; | |
| 175 | reg-io-width = <4>; | |
| 176 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
| 177 | clocks = <&axi81_clk>; | |
| 178 | clock-frequency = <100000000>; | |
| 179 | status = "disabled"; | |
| 180 | }; | |
| 181 | ||
| 182 | uart1: serial@18021000 { | |
| 183 | compatible = "snps,dw-apb-uart"; | |
| 184 | reg = <0x18021000 0x100>; | |
| 185 | reg-shift = <2>; | |
| 186 | reg-io-width = <4>; | |
| 187 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
| 188 | clocks = <&axi81_clk>; | |
| 189 | clock-frequency = <100000000>; | |
| 190 | status = "disabled"; | |
| 191 | }; | |
| 192 | ||
| 193 | uart2: serial@18022000 { | |
| 194 | compatible = "snps,dw-apb-uart"; | |
| 195 | reg = <0x18020000 0x100>; | |
| 196 | reg-shift = <2>; | |
| 197 | reg-io-width = <4>; | |
| 198 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 199 | clocks = <&axi81_clk>; | |
| 200 | clock-frequency = <100000000>; | |
| 201 | status = "disabled"; | |
| 202 | }; | |
| 203 | ||
| 204 | uart3: serial@18023000 { | |
| 205 | compatible = "snps,dw-apb-uart"; | |
| 206 | reg = <0x18023000 0x100>; | |
| 207 | reg-shift = <2>; | |
| 208 | reg-io-width = <4>; | |
| 209 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | |
| 210 | clocks = <&axi81_clk>; | |
| 211 | clock-frequency = <100000000>; | |
| 212 | status = "disabled"; | |
| 213 | }; | |
| 214 | ||
| 215 | gic: interrupt-controller@19021000 { | |
| 216 | compatible = "arm,cortex-a9-gic"; | |
| 217 | #interrupt-cells = <3>; | |
| 218 | #address-cells = <0>; | |
| 219 | interrupt-controller; | |
| 220 | reg = <0x19021000 0x1000>, | |
| 221 | <0x19020100 0x100>; | |
| 222 | }; | |
| 223 | ||
| 224 | L2: l2-cache { | |
| 225 | compatible = "arm,pl310-cache"; | |
| 226 | reg = <0x19022000 0x1000>; | |
| 227 | cache-unified; | |
| 228 | cache-level = <2>; | |
| 229 | }; | |
| 230 | ||
| 231 | timer@19020200 { | |
| 232 | compatible = "arm,cortex-a9-global-timer"; | |
| 233 | reg = <0x19020200 0x100>; | |
| 234 | interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 235 | clocks = <&periph_clk>; | |
| 236 | }; | |
| 237 | ||
| 238 | }; |