projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 7b2e987d JM |
1 | /* |
| 2 | * BSD LICENSE | |
| 3 | * | |
| 4 | * Copyright(c) 2015 Broadcom Corporation. All rights reserved. | |
| 5 | * | |
| 6 | * Redistribution and use in source and binary forms, with or without | |
| 7 | * modification, are permitted provided that the following conditions | |
| 8 | * are met: | |
| 9 | * | |
| 10 | * * Redistributions of source code must retain the above copyright | |
| 11 | * notice, this list of conditions and the following disclaimer. | |
| 12 | * * Redistributions in binary form must reproduce the above copyright | |
| 13 | * notice, this list of conditions and the following disclaimer in | |
| 14 | * the documentation and/or other materials provided with the | |
| 15 | * distribution. | |
| 16 | * * Neither the name of Broadcom Corporation nor the names of its | |
| 17 | * contributors may be used to endorse or promote products derived | |
| 18 | * from this software without specific prior written permission. | |
| 19 | * | |
| 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 21 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 22 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| 23 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 24 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| 25 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| 26 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| 27 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| 28 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 30 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 31 | */ | |
| 32 | ||
| 33 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 34 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 35 | ||
| 36 | #include "skeleton.dtsi" | |
| 37 | ||
| 38 | / { | |
| 39 | compatible = "brcm,nsp"; | |
| 40 | model = "Broadcom Northstar Plus SoC"; | |
| 41 | interrupt-parent = <&gic>; | |
| 42 | ||
| 43 | mpcore { | |
| 44 | compatible = "simple-bus"; | |
| 45 | ranges = <0x00000000 0x19020000 0x00003000>; | |
| 46 | #address-cells = <1>; | |
| 47 | #size-cells = <1>; | |
| 48 | ||
| 49 | cpus { | |
| 50 | #address-cells = <1>; | |
| 51 | #size-cells = <0>; | |
| 52 | ||
| 53 | cpu@0 { | |
| 54 | device_type = "cpu"; | |
| 55 | compatible = "arm,cortex-a9"; | |
| 56 | next-level-cache = <&L2>; | |
| 57 | reg = <0x0>; | |
| 58 | }; | |
| 59 | }; | |
| 60 | ||
| 61 | L2: l2-cache { | |
| 62 | compatible = "arm,pl310-cache"; | |
| 63 | reg = <0x2000 0x1000>; | |
| 64 | cache-unified; | |
| 65 | cache-level = <2>; | |
| 66 | }; | |
| 67 | ||
| 68 | gic: interrupt-controller@19021000 { | |
| 69 | compatible = "arm,cortex-a9-gic"; | |
| 70 | #interrupt-cells = <3>; | |
| 71 | #address-cells = <0>; | |
| 72 | interrupt-controller; | |
| 73 | reg = <0x1000 0x1000>, | |
| 74 | <0x0100 0x100>; | |
| 75 | }; | |
| 76 | ||
| 77 | timer@19020200 { | |
| 78 | compatible = "arm,cortex-a9-global-timer"; | |
| 79 | reg = <0x0200 0x100>; | |
| 80 | interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 81 | clocks = <&periph_clk>; | |
| 82 | }; | |
| 1a9d53ca JM |
83 | |
| 84 | twd-timer@19020600 { | |
| 85 | compatible = "arm,cortex-a9-twd-timer"; | |
| 86 | reg = <0x0600 0x20>; | |
| 87 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | | |
| 88 | IRQ_TYPE_LEVEL_HIGH)>; | |
| 89 | clocks = <&periph_clk>; | |
| 90 | }; | |
| 91 | ||
| 92 | twd-watchdog@19020620 { | |
| 93 | compatible = "arm,cortex-a9-twd-wdt"; | |
| 94 | reg = <0x0620 0x20>; | |
| 95 | interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | | |
| 96 | IRQ_TYPE_LEVEL_HIGH)>; | |
| 97 | clocks = <&periph_clk>; | |
| 98 | }; | |
| 7b2e987d JM |
99 | }; |
| 100 | ||
| 101 | clocks { | |
| 102 | #address-cells = <1>; | |
| 103 | #size-cells = <1>; | |
| 104 | ranges; | |
| 105 | ||
| 106 | periph_clk: periph_clk { | |
| 107 | compatible = "fixed-clock"; | |
| 108 | #clock-cells = <0>; | |
| 109 | clock-frequency = <500000000>; | |
| 110 | }; | |
| 111 | }; | |
| 112 | ||
| 113 | axi { | |
| 114 | compatible = "simple-bus"; | |
| 41254754 | 115 | ranges = <0x00000000 0x18000000 0x0011ba08>; |
| 7b2e987d JM |
116 | #address-cells = <1>; |
| 117 | #size-cells = <1>; | |
| 118 | ||
| 119 | uart0: serial@18000300 { | |
| 120 | compatible = "ns16550a"; | |
| 121 | reg = <0x0300 0x100>; | |
| 122 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
| 123 | clock-frequency = <62499840>; | |
| 124 | status = "disabled"; | |
| 125 | }; | |
| 126 | ||
| 127 | uart1: serial@18000400 { | |
| 128 | compatible = "ns16550a"; | |
| 129 | reg = <0x0400 0x100>; | |
| 130 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
| 131 | clock-frequency = <62499840>; | |
| 132 | status = "disabled"; | |
| 133 | }; | |
| 1dbcfb22 JM |
134 | |
| 135 | pcie0: pcie@18012000 { | |
| 136 | compatible = "brcm,iproc-pcie"; | |
| 137 | reg = <0x12000 0x1000>; | |
| 138 | ||
| 139 | #interrupt-cells = <1>; | |
| 140 | interrupt-map-mask = <0 0 0 0>; | |
| 141 | interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>; | |
| 142 | ||
| 143 | linux,pci-domain = <0>; | |
| 144 | ||
| 145 | bus-range = <0x00 0xff>; | |
| 146 | ||
| 147 | #address-cells = <3>; | |
| 148 | #size-cells = <2>; | |
| 149 | device_type = "pci"; | |
| 150 | ||
| 151 | /* Note: The HW does not support I/O resources. So, | |
| 152 | * only the memory resource range is being specified. | |
| 153 | */ | |
| 154 | ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; | |
| 155 | ||
| 156 | status = "disabled"; | |
| 157 | }; | |
| 158 | ||
| 159 | pcie1: pcie@18013000 { | |
| 160 | compatible = "brcm,iproc-pcie"; | |
| 161 | reg = <0x13000 0x1000>; | |
| 162 | ||
| 163 | #interrupt-cells = <1>; | |
| 164 | interrupt-map-mask = <0 0 0 0>; | |
| 165 | interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>; | |
| 166 | ||
| 167 | linux,pci-domain = <1>; | |
| 168 | ||
| 169 | bus-range = <0x00 0xff>; | |
| 170 | ||
| 171 | #address-cells = <3>; | |
| 172 | #size-cells = <2>; | |
| 173 | device_type = "pci"; | |
| 174 | ||
| 175 | /* Note: The HW does not support I/O resources. So, | |
| 176 | * only the memory resource range is being specified. | |
| 177 | */ | |
| 178 | ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; | |
| 179 | ||
| 180 | status = "disabled"; | |
| 181 | }; | |
| 182 | ||
| 183 | pcie2: pcie@18014000 { | |
| 184 | compatible = "brcm,iproc-pcie"; | |
| 185 | reg = <0x14000 0x1000>; | |
| 186 | ||
| 187 | #interrupt-cells = <1>; | |
| 188 | interrupt-map-mask = <0 0 0 0>; | |
| 189 | interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>; | |
| 190 | ||
| 191 | linux,pci-domain = <2>; | |
| 192 | ||
| 193 | bus-range = <0x00 0xff>; | |
| 194 | ||
| 195 | #address-cells = <3>; | |
| 196 | #size-cells = <2>; | |
| 197 | device_type = "pci"; | |
| 198 | ||
| 199 | /* Note: The HW does not support I/O resources. So, | |
| 200 | * only the memory resource range is being specified. | |
| 201 | */ | |
| 202 | ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; | |
| 203 | ||
| 204 | status = "disabled"; | |
| 205 | }; | |
| 41254754 JM |
206 | |
| 207 | nand: nand@18026000 { | |
| 208 | compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; | |
| 209 | reg = <0x026000 0x600>, | |
| 210 | <0x11b408 0x600>, | |
| 211 | <0x026f00 0x20>; | |
| 212 | reg-names = "nand", "iproc-idm", "iproc-ext"; | |
| 213 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
| 214 | ||
| 215 | #address-cells = <1>; | |
| 216 | #size-cells = <0>; | |
| 217 | ||
| 218 | brcm,nand-has-wp; | |
| 219 | }; | |
| 7b2e987d JM |
220 | }; |
| 221 | }; |