[deliverable/linux.git] / arch / arm / boot / dts / bcm-nsp.dtsi

/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/bcm-nsp.h>

#include "skeleton.dtsi"

/ {
	compatible = "brcm,nsp";
	model = "Broadcom Northstar Plus SoC";
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			enable-method = "brcm,bcm-nsp-smp";
			secondary-boot-reg = <0xffff042c>;
			reg = <0x1>;
		};
	};

	mpcore {
		compatible = "simple-bus";
		ranges = <0x00000000 0x19000000 0x00023000>;
		#address-cells = <1>;
		#size-cells = <1>;

		a9pll: arm_clk@00000 {
			#clock-cells = <0>;
			compatible = "brcm,nsp-armpll";
			clocks = <&osc>;
			reg = <0x00000 0x1000>;
		};

		timer@20200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x20200 0x100>;
			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&periph_clk>;
		};

		twd-timer@20600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x20600 0x20>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&periph_clk>;
		};

		twd-watchdog@20620 {
			compatible = "arm,cortex-a9-twd-wdt";
			reg = <0x20620 0x20>;
			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&periph_clk>;
		};

		gic: interrupt-controller@21000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x21000 0x1000>,
			      <0x20100 0x100>;
		};

		L2: l2-cache {
			compatible = "arm,pl310-cache";
			reg = <0x22000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc: oscillator {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25000000>;
		};

		iprocmed: iprocmed {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
			clock-div = <2>;
			clock-mult = <1>;
		};

		iprocslow: iprocslow {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
			clock-div = <4>;
			clock-mult = <1>;
		};

		periph_clk: periph_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&a9pll>;
			clock-div = <2>;
			clock-mult = <1>;
		};
	};

	axi {
		compatible = "simple-bus";
		ranges = <0x00000000 0x18000000 0x0011ba08>;
		#address-cells = <1>;
		#size-cells = <1>;

		gpioa: gpio@0020 {
			compatible = "brcm,nsp-gpio-a";
			reg = <0x0020 0x70>,
			      <0x3f1c4 0x1c>;
			#gpio-cells = <2>;
			gpio-controller;
			ngpios = <32>;
			interrupt-controller;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			gpio-ranges = <&pinctrl 0 0 32>;
		};

		uart0: serial@0300 {
			compatible = "ns16550a";
			reg = <0x0300 0x100>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc>;
			status = "disabled";
		};

		uart1: serial@0400 {
			compatible = "ns16550a";
			reg = <0x0400 0x100>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc>;
			status = "disabled";
		};

		nand: nand@26000 {
			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
			reg = <0x026000 0x600>,
			      <0x11b408 0x600>,
			      <0x026f00 0x20>;
			reg-names = "nand", "iproc-idm", "iproc-ext";
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;
			#size-cells = <0>;

			brcm,nand-has-wp;
		};

		i2c0: i2c@38000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x38000 0x50>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
			clock-frequency = <100000>;
		};

		lcpll0: lcpll0@3f100 {
			#clock-cells = <1>;
			compatible = "brcm,nsp-lcpll0";
			reg = <0x3f100 0x14>;
			clocks = <&osc>;
			clock-output-names = "lcpll0", "pcie_phy", "sdio",
					     "ddr_phy";
		};

		genpll: genpll@3f140 {
			#clock-cells = <1>;
			compatible = "brcm,nsp-genpll";
			reg = <0x3f140 0x24>;
			clocks = <&osc>;
			clock-output-names = "genpll", "phy", "ethernetclk",
					     "usbclk", "iprocfast", "sata1",
					     "sata2";
		};

		pinctrl: pinctrl@3f1c0 {
			compatible = "brcm,nsp-pinmux";
			reg = <0x3f1c0 0x04>,
			      <0x30028 0x04>,
			      <0x3f408 0x04>;
		};
	};

	pcie0: pcie@18012000 {
		compatible = "brcm,iproc-pcie";
		reg = <0x18012000 0x1000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;

		linux,pci-domain = <0>;

		bus-range = <0x00 0xff>;

		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";

		/* Note: The HW does not support I/O resources.  So,
		 * only the memory resource range is being specified.
		 */
		ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;

		status = "disabled";
	};

	pcie1: pcie@18013000 {
		compatible = "brcm,iproc-pcie";
		reg = <0x18013000 0x1000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;

		linux,pci-domain = <1>;

		bus-range = <0x00 0xff>;

		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";

		/* Note: The HW does not support I/O resources.  So,
		 * only the memory resource range is being specified.
		 */
		ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;

		status = "disabled";
	};

	pcie2: pcie@18014000 {
		compatible = "brcm,iproc-pcie";
		reg = <0x18014000 0x1000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;

		linux,pci-domain = <2>;

		bus-range = <0x00 0xff>;

		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";

		/* Note: The HW does not support I/O resources.  So,
		 * only the memory resource range is being specified.
		 */
		ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;

		status = "disabled";
	};
};
Commit	Line	Data
7b2e987d JM	1	/*
	2	* BSD LICENSE
	3	*
	4	* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	*
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in
	14	* the documentation and/or other materials provided with the
	15	* distribution.
	16	* * Neither the name of Broadcom Corporation nor the names of its
	17	* contributors may be used to endorse or promote products derived
	18	* from this software without specific prior written permission.
	19	*
	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	21	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	22	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	23	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	24	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	25	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	26	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	27	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	28	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	30	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*/
	32
	33	#include <dt-bindings/interrupt-controller/arm-gic.h>
	34	#include <dt-bindings/interrupt-controller/irq.h>
da3f9742	35	#include <dt-bindings/clock/bcm-nsp.h>
7b2e987d JM	36
	37	#include "skeleton.dtsi"
	38
	39	/ {
	40	compatible = "brcm,nsp";
	41	model = "Broadcom Northstar Plus SoC";
	42	interrupt-parent = <&gic>;
	43
944725fc KH	44	cpus {
	45	#address-cells = <1>;
	46	#size-cells = <0>;
	47
	48	cpu@0 {
	49	device_type = "cpu";
	50	compatible = "arm,cortex-a9";
	51	next-level-cache = <&L2>;
	52	reg = <0x0>;
	53	};
	54
	55	cpu@1 {
	56	device_type = "cpu";
	57	compatible = "arm,cortex-a9";
	58	next-level-cache = <&L2>;
	59	enable-method = "brcm,bcm-nsp-smp";
	60	secondary-boot-reg = <0xffff042c>;
	61	reg = <0x1>;
	62	};
	63	};
	64
7b2e987d JM	65	mpcore {
7b2e987d JM	66	compatible = "simple-bus";
da3f9742	67	ranges = <0x00000000 0x19000000 0x00023000>;
7b2e987d JM	68	#address-cells = <1>;
	69	#size-cells = <1>;
	70
da3f9742 JM	71	a9pll: arm_clk@00000 {
	72	#clock-cells = <0>;
	73	compatible = "brcm,nsp-armpll";
	74	clocks = <&osc>;
	75	reg = <0x00000 0x1000>;
	76	};
	77
	78	timer@20200 {
7b2e987d	79	compatible = "arm,cortex-a9-global-timer";
da3f9742	80	reg = <0x20200 0x100>;
7b2e987d JM	81	interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
	82	clocks = <&periph_clk>;
	83	};
1a9d53ca	84
da3f9742	85	twd-timer@20600 {
1a9d53ca	86	compatible = "arm,cortex-a9-twd-timer";
da3f9742	87	reg = <0x20600 0x20>;
1a9d53ca JM	88	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \|
	89	IRQ_TYPE_LEVEL_HIGH)>;
	90	clocks = <&periph_clk>;
	91	};
	92
da3f9742	93	twd-watchdog@20620 {
1a9d53ca	94	compatible = "arm,cortex-a9-twd-wdt";
da3f9742	95	reg = <0x20620 0x20>;
1a9d53ca JM	96	interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \|
	97	IRQ_TYPE_LEVEL_HIGH)>;
	98	clocks = <&periph_clk>;
	99	};
7ba8cd8b	100
da3f9742	101	gic: interrupt-controller@21000 {
7ba8cd8b JM	102	compatible = "arm,cortex-a9-gic";
	103	#interrupt-cells = <3>;
	104	#address-cells = <0>;
	105	interrupt-controller;
da3f9742 JM	106	reg = <0x21000 0x1000>,
da3f9742 JM	107	<0x20100 0x100>;
7ba8cd8b JM	108	};
	109
	110	L2: l2-cache {
	111	compatible = "arm,pl310-cache";
da3f9742	112	reg = <0x22000 0x1000>;
7ba8cd8b JM	113	cache-unified;
	114	cache-level = <2>;
	115	};
7b2e987d JM	116	};
	117
	118	clocks {
	119	#address-cells = <1>;
	120	#size-cells = <1>;
	121	ranges;
	122
da3f9742 JM	123	osc: oscillator {
da3f9742 JM	124	#clock-cells = <0>;
7b2e987d	125	compatible = "fixed-clock";
da3f9742 JM	126	clock-frequency = <25000000>;
	127	};
	128
	129	iprocmed: iprocmed {
	130	#clock-cells = <0>;
	131	compatible = "fixed-factor-clock";
	132	clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
	133	clock-div = <2>;
	134	clock-mult = <1>;
	135	};
	136
	137	iprocslow: iprocslow {
	138	#clock-cells = <0>;
	139	compatible = "fixed-factor-clock";
	140	clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
	141	clock-div = <4>;
	142	clock-mult = <1>;
	143	};
	144
	145	periph_clk: periph_clk {
7b2e987d	146	#clock-cells = <0>;
da3f9742 JM	147	compatible = "fixed-factor-clock";
	148	clocks = <&a9pll>;
	149	clock-div = <2>;
	150	clock-mult = <1>;
7b2e987d JM	151	};
	152	};
	153
	154	axi {
	155	compatible = "simple-bus";
41254754	156	ranges = <0x00000000 0x18000000 0x0011ba08>;
7b2e987d JM	157	#address-cells = <1>;
	158	#size-cells = <1>;
	159
018e4feb YRDR	160	gpioa: gpio@0020 {
	161	compatible = "brcm,nsp-gpio-a";
	162	reg = <0x0020 0x70>,
	163	<0x3f1c4 0x1c>;
	164	#gpio-cells = <2>;
	165	gpio-controller;
	166	ngpios = <32>;
	167	interrupt-controller;
	168	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	169	gpio-ranges = <&pinctrl 0 0 32>;
	170	};
	171
7ba8cd8b	172	uart0: serial@0300 {
7b2e987d JM	173	compatible = "ns16550a";
	174	reg = <0x0300 0x100>;
	175	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
da3f9742	176	clocks = <&osc>;
7b2e987d JM	177	status = "disabled";
	178	};
	179
7ba8cd8b	180	uart1: serial@0400 {
7b2e987d JM	181	compatible = "ns16550a";
	182	reg = <0x0400 0x100>;
	183	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
da3f9742	184	clocks = <&osc>;
7b2e987d JM	185	status = "disabled";
7b2e987d JM	186	};
1dbcfb22	187
7ba8cd8b	188	nand: nand@26000 {
41254754 JM	189	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
	190	reg = <0x026000 0x600>,
	191	<0x11b408 0x600>,
	192	<0x026f00 0x20>;
	193	reg-names = "nand", "iproc-idm", "iproc-ext";
	194	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
	195
	196	#address-cells = <1>;
	197	#size-cells = <0>;
	198
	199	brcm,nand-has-wp;
	200	};
0f9f27a3 JM	201
	202	i2c0: i2c@38000 {
	203	compatible = "brcm,iproc-i2c";
	204	reg = <0x38000 0x50>;
	205	#address-cells = <1>;
	206	#size-cells = <0>;
	207	interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
	208	clock-frequency = <100000>;
	209	};
da3f9742 JM	210
	211	lcpll0: lcpll0@3f100 {
	212	#clock-cells = <1>;
	213	compatible = "brcm,nsp-lcpll0";
	214	reg = <0x3f100 0x14>;
	215	clocks = <&osc>;
	216	clock-output-names = "lcpll0", "pcie_phy", "sdio",
	217	"ddr_phy";
	218	};
	219
	220	genpll: genpll@3f140 {
	221	#clock-cells = <1>;
	222	compatible = "brcm,nsp-genpll";
	223	reg = <0x3f140 0x24>;
	224	clocks = <&osc>;
	225	clock-output-names = "genpll", "phy", "ethernetclk",
	226	"usbclk", "iprocfast", "sata1",
	227	"sata2";
	228	};
ea2d8975 YRDR	229
	230	pinctrl: pinctrl@3f1c0 {
	231	compatible = "brcm,nsp-pinmux";
	232	reg = <0x3f1c0 0x04>,
	233	<0x30028 0x04>,
	234	<0x3f408 0x04>;
	235	};
7b2e987d	236	};
52219902 JM	237
	238	pcie0: pcie@18012000 {
	239	compatible = "brcm,iproc-pcie";
	240	reg = <0x18012000 0x1000>;
	241
	242	#interrupt-cells = <1>;
	243	interrupt-map-mask = <0 0 0 0>;
	244	interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;
	245
	246	linux,pci-domain = <0>;
	247
	248	bus-range = <0x00 0xff>;
	249
	250	#address-cells = <3>;
	251	#size-cells = <2>;
	252	device_type = "pci";
	253
	254	/* Note: The HW does not support I/O resources. So,
	255	* only the memory resource range is being specified.
	256	*/
	257	ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
	258
	259	status = "disabled";
	260	};
	261
	262	pcie1: pcie@18013000 {
	263	compatible = "brcm,iproc-pcie";
	264	reg = <0x18013000 0x1000>;
	265
	266	#interrupt-cells = <1>;
	267	interrupt-map-mask = <0 0 0 0>;
	268	interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;
	269
	270	linux,pci-domain = <1>;
	271
	272	bus-range = <0x00 0xff>;
	273
	274	#address-cells = <3>;
	275	#size-cells = <2>;
	276	device_type = "pci";
	277
	278	/* Note: The HW does not support I/O resources. So,
	279	* only the memory resource range is being specified.
	280	*/
	281	ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
	282
	283	status = "disabled";
	284	};
	285
	286	pcie2: pcie@18014000 {
	287	compatible = "brcm,iproc-pcie";
	288	reg = <0x18014000 0x1000>;
	289
	290	#interrupt-cells = <1>;
	291	interrupt-map-mask = <0 0 0 0>;
	292	interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;
	293
	294	linux,pci-domain = <2>;
	295
	296	bus-range = <0x00 0xff>;
	297
	298	#address-cells = <3>;
	299	#size-cells = <2>;
	300	device_type = "pci";
301
302	/* Note: The HW does not support I/O resources. So,
303	* only the memory resource range is being specified.
304	*/
305	ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
306
307	status = "disabled";
308	};
7b2e987d	309	};