[deliverable/linux.git] / arch / arm / boot / dts / bcm-nsp.dtsi

/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/bcm-nsp.h>

#include "skeleton.dtsi"

/ {
	compatible = "brcm,nsp";
	model = "Broadcom Northstar Plus SoC";
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			enable-method = "brcm,bcm-nsp-smp";
			secondary-boot-reg = <0xffff042c>;
			reg = <0x1>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	mpcore {
		compatible = "simple-bus";
		ranges = <0x00000000 0x19000000 0x00023000>;
		#address-cells = <1>;
		#size-cells = <1>;

		a9pll: arm_clk@00000 {
			#clock-cells = <0>;
			compatible = "brcm,nsp-armpll";
			clocks = <&osc>;
			reg = <0x00000 0x1000>;
		};

		timer@20200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x20200 0x100>;
			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&periph_clk>;
		};

		twd-timer@20600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x20600 0x20>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&periph_clk>;
		};

		twd-watchdog@20620 {
			compatible = "arm,cortex-a9-twd-wdt";
			reg = <0x20620 0x20>;
			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&periph_clk>;
		};

		gic: interrupt-controller@21000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x21000 0x1000>,
			      <0x20100 0x100>;
		};

		L2: l2-cache {
			compatible = "arm,pl310-cache";
			reg = <0x22000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc: oscillator {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25000000>;
		};

		iprocmed: iprocmed {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
			clock-div = <2>;
			clock-mult = <1>;
		};

		iprocslow: iprocslow {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
			clock-div = <4>;
			clock-mult = <1>;
		};

		periph_clk: periph_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&a9pll>;
			clock-div = <2>;
			clock-mult = <1>;
		};
	};

	axi {
		compatible = "simple-bus";
		ranges = <0x00000000 0x18000000 0x0011ba08>;
		#address-cells = <1>;
		#size-cells = <1>;

		gpioa: gpio@0020 {
			compatible = "brcm,nsp-gpio-a";
			reg = <0x0020 0x70>,
			      <0x3f1c4 0x1c>;
			#gpio-cells = <2>;
			gpio-controller;
			ngpios = <32>;
			interrupt-controller;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			gpio-ranges = <&pinctrl 0 0 32>;
		};

		uart0: serial@0300 {
			compatible = "ns16550a";
			reg = <0x0300 0x100>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc>;
			status = "disabled";
		};

		uart1: serial@0400 {
			compatible = "ns16550a";
			reg = <0x0400 0x100>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc>;
			status = "disabled";
		};

		nand: nand@26000 {
			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
			reg = <0x026000 0x600>,
			      <0x11b408 0x600>,
			      <0x026f00 0x20>;
			reg-names = "nand", "iproc-idm", "iproc-ext";
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;
			#size-cells = <0>;

			brcm,nand-has-wp;
		};

		i2c0: i2c@38000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x38000 0x50>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
			clock-frequency = <100000>;
		};

		lcpll0: lcpll0@3f100 {
			#clock-cells = <1>;
			compatible = "brcm,nsp-lcpll0";
			reg = <0x3f100 0x14>;
			clocks = <&osc>;
			clock-output-names = "lcpll0", "pcie_phy", "sdio",
					     "ddr_phy";
		};

		genpll: genpll@3f140 {
			#clock-cells = <1>;
			compatible = "brcm,nsp-genpll";
			reg = <0x3f140 0x24>;
			clocks = <&osc>;
			clock-output-names = "genpll", "phy", "ethernetclk",
					     "usbclk", "iprocfast", "sata1",
					     "sata2";
		};

		pinctrl: pinctrl@3f1c0 {
			compatible = "brcm,nsp-pinmux";
			reg = <0x3f1c0 0x04>,
			      <0x30028 0x04>,
			      <0x3f408 0x04>;
		};
	};

	pcie0: pcie@18012000 {
		compatible = "brcm,iproc-pcie";
		reg = <0x18012000 0x1000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;

		linux,pci-domain = <0>;

		bus-range = <0x00 0xff>;

		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";

		/* Note: The HW does not support I/O resources.  So,
		 * only the memory resource range is being specified.
		 */
		ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;

		status = "disabled";
	};

	pcie1: pcie@18013000 {
		compatible = "brcm,iproc-pcie";
		reg = <0x18013000 0x1000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;

		linux,pci-domain = <1>;

		bus-range = <0x00 0xff>;

		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";

		/* Note: The HW does not support I/O resources.  So,
		 * only the memory resource range is being specified.
		 */
		ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;

		status = "disabled";
	};

	pcie2: pcie@18014000 {
		compatible = "brcm,iproc-pcie";
		reg = <0x18014000 0x1000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;

		linux,pci-domain = <2>;

		bus-range = <0x00 0xff>;

		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";

		/* Note: The HW does not support I/O resources.  So,
		 * only the memory resource range is being specified.
		 */
		ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;

		status = "disabled";
	};
};
Commit	Line	Data
7b2e987d JM	1	/*
	2	* BSD LICENSE
	3	*
	4	* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	*
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in
	14	* the documentation and/or other materials provided with the
	15	* distribution.
	16	* * Neither the name of Broadcom Corporation nor the names of its
	17	* contributors may be used to endorse or promote products derived
	18	* from this software without specific prior written permission.
	19	*
	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	21	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	22	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	23	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	24	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	25	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	26	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	27	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	28	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	30	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*/
	32
	33	#include <dt-bindings/interrupt-controller/arm-gic.h>
	34	#include <dt-bindings/interrupt-controller/irq.h>
da3f9742	35	#include <dt-bindings/clock/bcm-nsp.h>
7b2e987d JM	36
	37	#include "skeleton.dtsi"
	38
	39	/ {
	40	compatible = "brcm,nsp";
	41	model = "Broadcom Northstar Plus SoC";
	42	interrupt-parent = <&gic>;
	43
944725fc KH	44	cpus {
	45	#address-cells = <1>;
	46	#size-cells = <0>;
	47
9d57f60c	48	cpu0: cpu@0 {
944725fc KH	49	device_type = "cpu";
	50	compatible = "arm,cortex-a9";
	51	next-level-cache = <&L2>;
	52	reg = <0x0>;
	53	};
	54
9d57f60c	55	cpu1: cpu@1 {
944725fc KH	56	device_type = "cpu";
	57	compatible = "arm,cortex-a9";
	58	next-level-cache = <&L2>;
	59	enable-method = "brcm,bcm-nsp-smp";
	60	secondary-boot-reg = <0xffff042c>;
	61	reg = <0x1>;
	62	};
	63	};
	64
9d57f60c JM	65	pmu {
	66	compatible = "arm,cortex-a9-pmu";
	67	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
	68	GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	69	interrupt-affinity = <&cpu0>, <&cpu1>;
	70	};
	71
7b2e987d JM	72	mpcore {
7b2e987d JM	73	compatible = "simple-bus";
da3f9742	74	ranges = <0x00000000 0x19000000 0x00023000>;
7b2e987d JM	75	#address-cells = <1>;
	76	#size-cells = <1>;
	77
da3f9742 JM	78	a9pll: arm_clk@00000 {
	79	#clock-cells = <0>;
	80	compatible = "brcm,nsp-armpll";
	81	clocks = <&osc>;
	82	reg = <0x00000 0x1000>;
	83	};
	84
	85	timer@20200 {
7b2e987d	86	compatible = "arm,cortex-a9-global-timer";
da3f9742	87	reg = <0x20200 0x100>;
7b2e987d JM	88	interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
	89	clocks = <&periph_clk>;
	90	};
1a9d53ca	91
da3f9742	92	twd-timer@20600 {
1a9d53ca	93	compatible = "arm,cortex-a9-twd-timer";
da3f9742	94	reg = <0x20600 0x20>;
1a9d53ca JM	95	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \|
	96	IRQ_TYPE_LEVEL_HIGH)>;
	97	clocks = <&periph_clk>;
	98	};
	99
da3f9742	100	twd-watchdog@20620 {
1a9d53ca	101	compatible = "arm,cortex-a9-twd-wdt";
da3f9742	102	reg = <0x20620 0x20>;
1a9d53ca JM	103	interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \|
	104	IRQ_TYPE_LEVEL_HIGH)>;
	105	clocks = <&periph_clk>;
	106	};
7ba8cd8b	107
da3f9742	108	gic: interrupt-controller@21000 {
7ba8cd8b JM	109	compatible = "arm,cortex-a9-gic";
	110	#interrupt-cells = <3>;
	111	#address-cells = <0>;
	112	interrupt-controller;
da3f9742 JM	113	reg = <0x21000 0x1000>,
da3f9742 JM	114	<0x20100 0x100>;
7ba8cd8b JM	115	};
	116
	117	L2: l2-cache {
	118	compatible = "arm,pl310-cache";
da3f9742	119	reg = <0x22000 0x1000>;
7ba8cd8b JM	120	cache-unified;
	121	cache-level = <2>;
	122	};
7b2e987d JM	123	};
	124
	125	clocks {
	126	#address-cells = <1>;
	127	#size-cells = <1>;
	128	ranges;
	129
da3f9742 JM	130	osc: oscillator {
da3f9742 JM	131	#clock-cells = <0>;
7b2e987d	132	compatible = "fixed-clock";
da3f9742 JM	133	clock-frequency = <25000000>;
	134	};
	135
	136	iprocmed: iprocmed {
	137	#clock-cells = <0>;
	138	compatible = "fixed-factor-clock";
	139	clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
	140	clock-div = <2>;
	141	clock-mult = <1>;
	142	};
	143
	144	iprocslow: iprocslow {
	145	#clock-cells = <0>;
	146	compatible = "fixed-factor-clock";
	147	clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
	148	clock-div = <4>;
	149	clock-mult = <1>;
	150	};
	151
	152	periph_clk: periph_clk {
7b2e987d	153	#clock-cells = <0>;
da3f9742 JM	154	compatible = "fixed-factor-clock";
	155	clocks = <&a9pll>;
	156	clock-div = <2>;
	157	clock-mult = <1>;
7b2e987d JM	158	};
	159	};
	160
	161	axi {
	162	compatible = "simple-bus";
41254754	163	ranges = <0x00000000 0x18000000 0x0011ba08>;
7b2e987d JM	164	#address-cells = <1>;
	165	#size-cells = <1>;
	166
018e4feb YRDR	167	gpioa: gpio@0020 {
	168	compatible = "brcm,nsp-gpio-a";
	169	reg = <0x0020 0x70>,
	170	<0x3f1c4 0x1c>;
	171	#gpio-cells = <2>;
	172	gpio-controller;
	173	ngpios = <32>;
	174	interrupt-controller;
	175	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	176	gpio-ranges = <&pinctrl 0 0 32>;
	177	};
	178
7ba8cd8b	179	uart0: serial@0300 {
7b2e987d JM	180	compatible = "ns16550a";
	181	reg = <0x0300 0x100>;
	182	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
da3f9742	183	clocks = <&osc>;
7b2e987d JM	184	status = "disabled";
	185	};
	186
7ba8cd8b	187	uart1: serial@0400 {
7b2e987d JM	188	compatible = "ns16550a";
	189	reg = <0x0400 0x100>;
	190	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
da3f9742	191	clocks = <&osc>;
7b2e987d JM	192	status = "disabled";
7b2e987d JM	193	};
1dbcfb22	194
7ba8cd8b	195	nand: nand@26000 {
41254754 JM	196	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
	197	reg = <0x026000 0x600>,
	198	<0x11b408 0x600>,
	199	<0x026f00 0x20>;
	200	reg-names = "nand", "iproc-idm", "iproc-ext";
	201	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
	202
	203	#address-cells = <1>;
	204	#size-cells = <0>;
	205
	206	brcm,nand-has-wp;
	207	};
0f9f27a3 JM	208
	209	i2c0: i2c@38000 {
	210	compatible = "brcm,iproc-i2c";
	211	reg = <0x38000 0x50>;
	212	#address-cells = <1>;
	213	#size-cells = <0>;
	214	interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
	215	clock-frequency = <100000>;
	216	};
da3f9742 JM	217
	218	lcpll0: lcpll0@3f100 {
	219	#clock-cells = <1>;
	220	compatible = "brcm,nsp-lcpll0";
	221	reg = <0x3f100 0x14>;
	222	clocks = <&osc>;
	223	clock-output-names = "lcpll0", "pcie_phy", "sdio",
	224	"ddr_phy";
	225	};
	226
	227	genpll: genpll@3f140 {
	228	#clock-cells = <1>;
	229	compatible = "brcm,nsp-genpll";
	230	reg = <0x3f140 0x24>;
	231	clocks = <&osc>;
	232	clock-output-names = "genpll", "phy", "ethernetclk",
	233	"usbclk", "iprocfast", "sata1",
	234	"sata2";
	235	};
ea2d8975 YRDR	236
	237	pinctrl: pinctrl@3f1c0 {
	238	compatible = "brcm,nsp-pinmux";
	239	reg = <0x3f1c0 0x04>,
	240	<0x30028 0x04>,
	241	<0x3f408 0x04>;
	242	};
7b2e987d	243	};
52219902 JM	244
	245	pcie0: pcie@18012000 {
	246	compatible = "brcm,iproc-pcie";
	247	reg = <0x18012000 0x1000>;
	248
	249	#interrupt-cells = <1>;
	250	interrupt-map-mask = <0 0 0 0>;
	251	interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;
	252
	253	linux,pci-domain = <0>;
	254
	255	bus-range = <0x00 0xff>;
	256
	257	#address-cells = <3>;
	258	#size-cells = <2>;
	259	device_type = "pci";
	260
	261	/* Note: The HW does not support I/O resources. So,
	262	* only the memory resource range is being specified.
	263	*/
	264	ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
	265
	266	status = "disabled";
	267	};
	268
	269	pcie1: pcie@18013000 {
	270	compatible = "brcm,iproc-pcie";
	271	reg = <0x18013000 0x1000>;
	272
	273	#interrupt-cells = <1>;
	274	interrupt-map-mask = <0 0 0 0>;
	275	interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;
	276
	277	linux,pci-domain = <1>;
	278
	279	bus-range = <0x00 0xff>;
	280
	281	#address-cells = <3>;
	282	#size-cells = <2>;
	283	device_type = "pci";
	284
	285	/* Note: The HW does not support I/O resources. So,
	286	* only the memory resource range is being specified.
	287	*/
	288	ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
	289
	290	status = "disabled";
	291	};
	292
	293	pcie2: pcie@18014000 {
	294	compatible = "brcm,iproc-pcie";
	295	reg = <0x18014000 0x1000>;
	296
	297	#interrupt-cells = <1>;
	298	interrupt-map-mask = <0 0 0 0>;
	299	interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;
	300
	301	linux,pci-domain = <2>;
	302
	303	bus-range = <0x00 0xff>;
	304
	305	#address-cells = <3>;
	306	#size-cells = <2>;
	307	device_type = "pci";
308
309	/* Note: The HW does not support I/O resources. So,
310	* only the memory resource range is being specified.
311	*/
312	ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
313
314	status = "disabled";
315	};
7b2e987d	316	};