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8ac49e04 CD |
1 | /* |
2 | * Copyright (C) 2012 Broadcom Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation version 2. | |
7 | * | |
8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
9 | * kind, whether express or implied; without even the implied warranty | |
10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
5401cc43 MP |
14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
15 | #include <dt-bindings/interrupt-controller/irq.h> | |
16 | ||
74375653 | 17 | #include "skeleton.dtsi" |
8ac49e04 CD |
18 | |
19 | / { | |
20 | model = "BCM11351 SoC"; | |
21 | compatible = "bcm,bcm11351"; | |
22 | interrupt-parent = <&gic>; | |
23 | ||
24 | chosen { | |
25 | bootargs = "console=ttyS0,115200n8"; | |
26 | }; | |
27 | ||
28 | gic: interrupt-controller@3ff00100 { | |
29 | compatible = "arm,cortex-a9-gic"; | |
30 | #interrupt-cells = <3>; | |
31 | #address-cells = <0>; | |
32 | interrupt-controller; | |
33 | reg = <0x3ff01000 0x1000>, | |
34 | <0x3ff00100 0x100>; | |
35 | }; | |
36 | ||
7f6c62e2 CD |
37 | smc@0x3404c000 { |
38 | compatible = "bcm,bcm11351-smc", "bcm,kona-smc"; | |
d22dc5ed | 39 | reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ |
7f6c62e2 CD |
40 | }; |
41 | ||
8ac49e04 CD |
42 | uart@3e000000 { |
43 | compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; | |
44 | status = "disabled"; | |
45 | reg = <0x3e000000 0x1000>; | |
46 | clock-frequency = <13000000>; | |
5401cc43 | 47 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
8ac49e04 CD |
48 | reg-shift = <2>; |
49 | reg-io-width = <4>; | |
50 | }; | |
51 | ||
52 | L2: l2-cache { | |
3b656fed CD |
53 | compatible = "bcm,bcm11351-a2-pl310-cache"; |
54 | reg = <0x3ff20000 0x1000>; | |
55 | cache-unified; | |
56 | cache-level = <2>; | |
8ac49e04 | 57 | }; |
5f03dc20 CD |
58 | |
59 | timer@35006000 { | |
60 | compatible = "bcm,kona-timer"; | |
61 | reg = <0x35006000 0x1000>; | |
5401cc43 | 62 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
5f03dc20 CD |
63 | clock-frequency = <32768>; |
64 | }; | |
65 | ||
2dbfe748 CD |
66 | sdio0: sdio@0x3f180000 { |
67 | compatible = "bcm,kona-sdhci"; | |
68 | reg = <0x3f180000 0x10000>; | |
69 | interrupts = <0x0 77 0x4>; | |
70 | status = "disabled"; | |
71 | }; | |
72 | ||
73 | sdio1: sdio@0x3f190000 { | |
74 | compatible = "bcm,kona-sdhci"; | |
75 | reg = <0x3f190000 0x10000>; | |
76 | interrupts = <0x0 76 0x4>; | |
77 | status = "disabled"; | |
78 | }; | |
79 | ||
80 | sdio2: sdio@0x3f1a0000 { | |
81 | compatible = "bcm,kona-sdhci"; | |
82 | reg = <0x3f1a0000 0x10000>; | |
83 | interrupts = <0x0 74 0x4>; | |
84 | status = "disabled"; | |
85 | }; | |
86 | ||
87 | sdio3: sdio@0x3f1b0000 { | |
88 | compatible = "bcm,kona-sdhci"; | |
89 | reg = <0x3f1b0000 0x10000>; | |
90 | interrupts = <0x0 73 0x4>; | |
91 | status = "disabled"; | |
92 | }; | |
93 | ||
8ac49e04 | 94 | }; |