projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 8ac49e04 CD |
1 | /* |
| 2 | * Copyright (C) 2012 Broadcom Corporation | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or | |
| 5 | * modify it under the terms of the GNU General Public License as | |
| 6 | * published by the Free Software Foundation version 2. | |
| 7 | * | |
| 8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
| 9 | * kind, whether express or implied; without even the implied warranty | |
| 10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 11 | * GNU General Public License for more details. | |
| 12 | */ | |
| 13 | ||
| 14 | /include/ "skeleton.dtsi" | |
| 15 | ||
| 16 | / { | |
| 17 | model = "BCM11351 SoC"; | |
| 18 | compatible = "bcm,bcm11351"; | |
| 19 | interrupt-parent = <&gic>; | |
| 20 | ||
| 21 | chosen { | |
| 22 | bootargs = "console=ttyS0,115200n8"; | |
| 23 | }; | |
| 24 | ||
| 25 | gic: interrupt-controller@3ff00100 { | |
| 26 | compatible = "arm,cortex-a9-gic"; | |
| 27 | #interrupt-cells = <3>; | |
| 28 | #address-cells = <0>; | |
| 29 | interrupt-controller; | |
| 30 | reg = <0x3ff01000 0x1000>, | |
| 31 | <0x3ff00100 0x100>; | |
| 32 | }; | |
| 33 | ||
| 34 | uart@3e000000 { | |
| 35 | compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; | |
| 36 | status = "disabled"; | |
| 37 | reg = <0x3e000000 0x1000>; | |
| 38 | clock-frequency = <13000000>; | |
| 39 | interrupts = <0x0 67 0x4>; | |
| 40 | reg-shift = <2>; | |
| 41 | reg-io-width = <4>; | |
| 42 | }; | |
| 43 | ||
| 44 | L2: l2-cache { | |
| 45 | compatible = "arm,pl310-cache"; | |
| 46 | reg = <0x3ff20000 0x1000>; | |
| 47 | cache-unified; | |
| 48 | cache-level = <2>; | |
| 49 | }; | |
| 50 | }; |