Commit | Line | Data |
---|---|---|
12091112 | 1 | #include <dt-bindings/pinctrl/bcm2835.h> |
94cb7f76 | 2 | #include <dt-bindings/clock/bcm2835.h> |
12091112 | 3 | #include "skeleton.dtsi" |
ec9653b8 SA |
4 | |
5 | / { | |
6 | compatible = "brcm,bcm2835"; | |
7 | model = "BCM2835"; | |
89214f00 | 8 | interrupt-parent = <&intc>; |
ec9653b8 SA |
9 | |
10 | chosen { | |
407f9be4 | 11 | bootargs = "earlyprintk console=ttyAMA0"; |
ec9653b8 SA |
12 | }; |
13 | ||
14 | soc { | |
15 | compatible = "simple-bus"; | |
16 | #address-cells = <1>; | |
17 | #size-cells = <1>; | |
18 | ranges = <0x7e000000 0x20000000 0x02000000>; | |
1215baa7 | 19 | dma-ranges = <0x40000000 0x00000000 0x20000000>; |
89214f00 | 20 | |
25b2f1bd | 21 | timer@7e003000 { |
ee4af569 SA |
22 | compatible = "brcm,bcm2835-system-timer"; |
23 | reg = <0x7e003000 0x1000>; | |
24 | interrupts = <1 0>, <1 1>, <1 2>, <1 3>; | |
94cb7f76 EA |
25 | /* This could be a reference to BCM2835_CLOCK_TIMER, |
26 | * but we don't have the driver using the common clock | |
27 | * support yet. | |
28 | */ | |
ee4af569 SA |
29 | clock-frequency = <1000000>; |
30 | }; | |
31 | ||
89072339 FM |
32 | dma: dma@7e007000 { |
33 | compatible = "brcm,bcm2835-dma"; | |
34 | reg = <0x7e007000 0xf00>; | |
35 | interrupts = <1 16>, | |
36 | <1 17>, | |
37 | <1 18>, | |
38 | <1 19>, | |
39 | <1 20>, | |
40 | <1 21>, | |
41 | <1 22>, | |
42 | <1 23>, | |
43 | <1 24>, | |
44 | <1 25>, | |
45 | <1 26>, | |
46 | <1 27>, | |
47 | <1 28>; | |
48 | ||
49 | #dma-cells = <1>; | |
50 | brcm,dma-channel-mask = <0x7f35>; | |
51 | }; | |
52 | ||
25b2f1bd | 53 | intc: interrupt-controller@7e00b200 { |
89214f00 SA |
54 | compatible = "brcm,bcm2835-armctrl-ic"; |
55 | reg = <0x7e00b200 0x200>; | |
56 | interrupt-controller; | |
57 | #interrupt-cells = <2>; | |
58 | }; | |
407f9be4 | 59 | |
25b2f1bd | 60 | watchdog@7e100000 { |
d0f1c7ff SW |
61 | compatible = "brcm,bcm2835-pm-wdt"; |
62 | reg = <0x7e100000 0x28>; | |
63 | }; | |
64 | ||
94cb7f76 EA |
65 | clocks: cprman@7e101000 { |
66 | compatible = "brcm,bcm2835-cprman"; | |
67 | #clock-cells = <1>; | |
68 | reg = <0x7e101000 0x2000>; | |
69 | ||
70 | /* CPRMAN derives everything from the platform's | |
71 | * oscillator. | |
72 | */ | |
73 | clocks = <&clk_osc>; | |
74 | }; | |
75 | ||
25b2f1bd | 76 | rng@7e104000 { |
a1bf7082 LR |
77 | compatible = "brcm,bcm2835-rng"; |
78 | reg = <0x7e104000 0x10>; | |
79 | }; | |
80 | ||
05b682b7 EA |
81 | mailbox: mailbox@7e00b800 { |
82 | compatible = "brcm,bcm2835-mbox"; | |
83 | reg = <0x7e00b880 0x40>; | |
84 | interrupts = <0 1>; | |
85 | #mbox-cells = <0>; | |
86 | }; | |
87 | ||
25b2f1bd | 88 | gpio: gpio@7e200000 { |
805504ab SW |
89 | compatible = "brcm,bcm2835-gpio"; |
90 | reg = <0x7e200000 0xb4>; | |
91 | /* | |
92 | * The GPIO IP block is designed for 3 banks of GPIOs. | |
93 | * Each bank has a GPIO interrupt for itself. | |
94 | * There is an overall "any bank" interrupt. | |
95 | * In order, these are GIC interrupts 17, 18, 19, 20. | |
96 | * Since the BCM2835 only has 2 banks, the 2nd bank | |
97 | * interrupt output appears to be mirrored onto the | |
98 | * 3rd bank's interrupt signal. | |
99 | * So, a bank0 interrupt shows up on 17, 20, and | |
100 | * a bank1 interrupt shows up on 18, 19, 20! | |
101 | */ | |
102 | interrupts = <2 17>, <2 18>, <2 19>, <2 20>; | |
103 | ||
104 | gpio-controller; | |
105 | #gpio-cells = <2>; | |
106 | ||
107 | interrupt-controller; | |
108 | #interrupt-cells = <2>; | |
109 | }; | |
5186bf28 | 110 | |
755f121e | 111 | uart0: uart@7e201000 { |
ef3c690c SW |
112 | compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; |
113 | reg = <0x7e201000 0x1000>; | |
114 | interrupts = <2 25>; | |
94cb7f76 EA |
115 | clocks = <&clocks BCM2835_CLOCK_UART>, |
116 | <&clocks BCM2835_CLOCK_VPU>; | |
117 | clock-names = "uartclk", "apb_pclk"; | |
ef3c690c SW |
118 | arm,primecell-periphid = <0x00241011>; |
119 | }; | |
120 | ||
9511cc4d FM |
121 | i2s: i2s@7e203000 { |
122 | compatible = "brcm,bcm2835-i2s"; | |
123 | reg = <0x7e203000 0x20>, | |
124 | <0x7e101098 0x02>; | |
125 | ||
126 | dmas = <&dma 2>, | |
127 | <&dma 3>; | |
128 | dma-names = "tx", "rx"; | |
667bbd53 | 129 | status = "disabled"; |
9511cc4d FM |
130 | }; |
131 | ||
25b2f1bd | 132 | spi: spi@7e204000 { |
6ce5f02e SW |
133 | compatible = "brcm,bcm2835-spi"; |
134 | reg = <0x7e204000 0x1000>; | |
135 | interrupts = <2 22>; | |
94cb7f76 | 136 | clocks = <&clocks BCM2835_CLOCK_VPU>; |
6ce5f02e SW |
137 | #address-cells = <1>; |
138 | #size-cells = <0>; | |
139 | status = "disabled"; | |
140 | }; | |
141 | ||
64146f20 | 142 | i2c0: i2c@7e205000 { |
232fed48 SW |
143 | compatible = "brcm,bcm2835-i2c"; |
144 | reg = <0x7e205000 0x1000>; | |
145 | interrupts = <2 21>; | |
94cb7f76 | 146 | clocks = <&clocks BCM2835_CLOCK_VPU>; |
a31ab44e SW |
147 | #address-cells = <1>; |
148 | #size-cells = <0>; | |
232fed48 SW |
149 | status = "disabled"; |
150 | }; | |
151 | ||
25b2f1bd | 152 | sdhci: sdhci@7e300000 { |
ef3c690c SW |
153 | compatible = "brcm,bcm2835-sdhci"; |
154 | reg = <0x7e300000 0x100>; | |
155 | interrupts = <2 30>; | |
94cb7f76 | 156 | clocks = <&clocks BCM2835_CLOCK_EMMC>; |
ef3c690c SW |
157 | status = "disabled"; |
158 | }; | |
159 | ||
25b2f1bd | 160 | i2c1: i2c@7e804000 { |
232fed48 SW |
161 | compatible = "brcm,bcm2835-i2c"; |
162 | reg = <0x7e804000 0x1000>; | |
163 | interrupts = <2 21>; | |
94cb7f76 | 164 | clocks = <&clocks BCM2835_CLOCK_VPU>; |
a31ab44e SW |
165 | #address-cells = <1>; |
166 | #size-cells = <0>; | |
232fed48 SW |
167 | status = "disabled"; |
168 | }; | |
169 | ||
121432c7 EA |
170 | i2c2: i2c@7e805000 { |
171 | compatible = "brcm,bcm2835-i2c"; | |
172 | reg = <0x7e805000 0x1000>; | |
173 | interrupts = <2 21>; | |
174 | clocks = <&clocks BCM2835_CLOCK_VPU>; | |
175 | #address-cells = <1>; | |
176 | #size-cells = <0>; | |
177 | status = "disabled"; | |
178 | }; | |
179 | ||
25b2f1bd | 180 | usb@7e980000 { |
5631e7f4 SW |
181 | compatible = "brcm,bcm2835-usb"; |
182 | reg = <0x7e980000 0x10000>; | |
183 | interrupts = <1 9>; | |
184 | }; | |
14ac652b VW |
185 | |
186 | arm-pmu { | |
187 | compatible = "arm,arm1176-pmu"; | |
188 | }; | |
5186bf28 SW |
189 | }; |
190 | ||
9692c191 SW |
191 | clocks { |
192 | compatible = "simple-bus"; | |
193 | #address-cells = <1>; | |
194 | #size-cells = <0>; | |
232fed48 | 195 | |
94cb7f76 EA |
196 | /* The oscillator is the root of the clock tree. */ |
197 | clk_osc: clock@3 { | |
9692c191 | 198 | compatible = "fixed-clock"; |
94cb7f76 | 199 | reg = <3>; |
9692c191 | 200 | #clock-cells = <0>; |
94cb7f76 EA |
201 | clock-output-names = "osc"; |
202 | clock-frequency = <19200000>; | |
9692c191 | 203 | }; |
6ce5f02e | 204 | |
ec9653b8 SA |
205 | }; |
206 | }; |