Commit | Line | Data |
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d27509f1 HM |
1 | /* |
2 | * Broadcom BCM470X / BCM5301X ARM platform code. | |
3 | * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, | |
4 | * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs | |
5 | * | |
6 | * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> | |
7 | * | |
8 | * Licensed under the GNU/GPL. See COPYING for details. | |
9 | */ | |
10 | ||
cdc36b22 | 11 | #include <dt-bindings/clock/bcm-nsp.h> |
fb026d3d | 12 | #include <dt-bindings/gpio/gpio.h> |
f6f82344 | 13 | #include <dt-bindings/input/input.h> |
d27509f1 HM |
14 | #include <dt-bindings/interrupt-controller/irq.h> |
15 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
16 | #include "skeleton.dtsi" | |
17 | ||
18 | / { | |
19 | interrupt-parent = <&gic>; | |
20 | ||
5a6516ff RM |
21 | chosen { |
22 | stdout-path = &uart0; | |
23 | }; | |
24 | ||
d27509f1 HM |
25 | chipcommonA { |
26 | compatible = "simple-bus"; | |
27 | ranges = <0x00000000 0x18000000 0x00001000>; | |
28 | #address-cells = <1>; | |
29 | #size-cells = <1>; | |
30 | ||
31 | uart0: serial@0300 { | |
32 | compatible = "ns16550"; | |
33 | reg = <0x0300 0x100>; | |
34 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
cdc36b22 | 35 | clocks = <&iprocslow>; |
d27509f1 HM |
36 | status = "disabled"; |
37 | }; | |
38 | ||
39 | uart1: serial@0400 { | |
40 | compatible = "ns16550"; | |
41 | reg = <0x0400 0x100>; | |
42 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
cdc36b22 | 43 | clocks = <&iprocslow>; |
d27509f1 HM |
44 | status = "disabled"; |
45 | }; | |
46 | }; | |
47 | ||
48 | mpcore { | |
49 | compatible = "simple-bus"; | |
cdc36b22 | 50 | ranges = <0x00000000 0x19000000 0x00023000>; |
d27509f1 HM |
51 | #address-cells = <1>; |
52 | #size-cells = <1>; | |
53 | ||
cdc36b22 JM |
54 | a9pll: arm_clk@00000 { |
55 | #clock-cells = <0>; | |
56 | compatible = "brcm,nsp-armpll"; | |
57 | clocks = <&osc>; | |
58 | reg = <0x00000 0x1000>; | |
59 | }; | |
60 | ||
61 | scu@20000 { | |
d27509f1 | 62 | compatible = "arm,cortex-a9-scu"; |
cdc36b22 | 63 | reg = <0x20000 0x100>; |
d27509f1 HM |
64 | }; |
65 | ||
cdc36b22 | 66 | timer@20200 { |
d27509f1 | 67 | compatible = "arm,cortex-a9-global-timer"; |
cdc36b22 | 68 | reg = <0x20200 0x100>; |
d27509f1 | 69 | interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; |
cdc36b22 | 70 | clocks = <&periph_clk>; |
d27509f1 HM |
71 | }; |
72 | ||
cdc36b22 | 73 | local-timer@20600 { |
d27509f1 | 74 | compatible = "arm,cortex-a9-twd-timer"; |
cdc36b22 | 75 | reg = <0x20600 0x100>; |
d27509f1 | 76 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; |
cdc36b22 | 77 | clocks = <&periph_clk>; |
d27509f1 HM |
78 | }; |
79 | ||
cdc36b22 | 80 | gic: interrupt-controller@21000 { |
d27509f1 HM |
81 | compatible = "arm,cortex-a9-gic"; |
82 | #interrupt-cells = <3>; | |
83 | #address-cells = <0>; | |
84 | interrupt-controller; | |
cdc36b22 JM |
85 | reg = <0x21000 0x1000>, |
86 | <0x20100 0x100>; | |
d27509f1 HM |
87 | }; |
88 | ||
cdc36b22 | 89 | L2: cache-controller@22000 { |
d27509f1 | 90 | compatible = "arm,pl310-cache"; |
cdc36b22 | 91 | reg = <0x22000 0x1000>; |
d27509f1 | 92 | cache-unified; |
db44f134 HM |
93 | arm,shared-override; |
94 | prefetch-data = <1>; | |
95 | prefetch-instr = <1>; | |
d27509f1 HM |
96 | cache-level = <2>; |
97 | }; | |
98 | }; | |
99 | ||
1ff80363 FF |
100 | pmu { |
101 | compatible = "arm,cortex-a9-pmu"; | |
102 | interrupts = | |
103 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
104 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
105 | }; | |
106 | ||
d27509f1 HM |
107 | clocks { |
108 | #address-cells = <1>; | |
cdc36b22 JM |
109 | #size-cells = <1>; |
110 | ranges; | |
d27509f1 | 111 | |
cdc36b22 JM |
112 | osc: oscillator { |
113 | #clock-cells = <0>; | |
d27509f1 | 114 | compatible = "fixed-clock"; |
cdc36b22 JM |
115 | clock-frequency = <25000000>; |
116 | }; | |
117 | ||
118 | iprocmed: iprocmed { | |
119 | #clock-cells = <0>; | |
120 | compatible = "fixed-factor-clock"; | |
121 | clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; | |
122 | clock-div = <2>; | |
123 | clock-mult = <1>; | |
124 | }; | |
125 | ||
126 | iprocslow: iprocslow { | |
127 | #clock-cells = <0>; | |
128 | compatible = "fixed-factor-clock"; | |
129 | clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; | |
130 | clock-div = <4>; | |
131 | clock-mult = <1>; | |
132 | }; | |
133 | ||
134 | periph_clk: periph_clk { | |
d27509f1 | 135 | #clock-cells = <0>; |
cdc36b22 JM |
136 | compatible = "fixed-factor-clock"; |
137 | clocks = <&a9pll>; | |
138 | clock-div = <2>; | |
139 | clock-mult = <1>; | |
d27509f1 HM |
140 | }; |
141 | }; | |
fb026d3d RM |
142 | |
143 | axi@18000000 { | |
144 | compatible = "brcm,bus-axi"; | |
145 | reg = <0x18000000 0x1000>; | |
146 | ranges = <0x00000000 0x18000000 0x00100000>; | |
147 | #address-cells = <1>; | |
148 | #size-cells = <1>; | |
149 | ||
dec37882 HM |
150 | #interrupt-cells = <1>; |
151 | interrupt-map-mask = <0x000fffff 0xffff>; | |
152 | interrupt-map = | |
153 | /* ChipCommon */ | |
154 | <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, | |
155 | ||
1f80de68 HM |
156 | /* PCIe Controller 0 */ |
157 | <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, | |
158 | <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, | |
159 | <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
160 | <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | |
161 | <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | |
162 | <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
163 | ||
164 | /* PCIe Controller 1 */ | |
165 | <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, | |
166 | <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, | |
167 | <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
168 | <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
169 | <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
170 | <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
171 | ||
172 | /* PCIe Controller 2 */ | |
173 | <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
174 | <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
175 | <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, | |
176 | <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, | |
177 | <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
178 | <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, | |
179 | ||
dec37882 HM |
180 | /* USB 2.0 Controller */ |
181 | <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, | |
182 | ||
183 | /* USB 3.0 Controller */ | |
184 | <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, | |
185 | ||
186 | /* Ethernet Controller 0 */ | |
187 | <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, | |
188 | ||
189 | /* Ethernet Controller 1 */ | |
190 | <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, | |
191 | ||
192 | /* Ethernet Controller 2 */ | |
193 | <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, | |
194 | ||
195 | /* Ethernet Controller 3 */ | |
196 | <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, | |
197 | ||
198 | /* NAND Controller */ | |
199 | <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, | |
200 | <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, | |
201 | <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, | |
202 | <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | |
203 | <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
204 | <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, | |
205 | <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, | |
206 | <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
207 | ||
fb026d3d RM |
208 | chipcommon: chipcommon@0 { |
209 | reg = <0x00000000 0x1000>; | |
210 | ||
211 | gpio-controller; | |
212 | #gpio-cells = <2>; | |
213 | }; | |
dd70ccfa RM |
214 | |
215 | usb2: usb2@21000 { | |
216 | reg = <0x00021000 0x1000>; | |
217 | ||
218 | #address-cells = <1>; | |
219 | #size-cells = <1>; | |
220 | }; | |
221 | ||
222 | usb3: usb3@23000 { | |
223 | reg = <0x00023000 0x1000>; | |
224 | ||
225 | #address-cells = <1>; | |
226 | #size-cells = <1>; | |
227 | }; | |
fb026d3d | 228 | }; |
9faa5960 | 229 | |
cdc36b22 JM |
230 | lcpll0: lcpll0@1800c100 { |
231 | #clock-cells = <1>; | |
232 | compatible = "brcm,nsp-lcpll0"; | |
233 | reg = <0x1800c100 0x14>; | |
234 | clocks = <&osc>; | |
235 | clock-output-names = "lcpll0", "pcie_phy", "sdio", | |
236 | "ddr_phy"; | |
237 | }; | |
238 | ||
239 | genpll: genpll@1800c140 { | |
240 | #clock-cells = <1>; | |
241 | compatible = "brcm,nsp-genpll"; | |
242 | reg = <0x1800c140 0x24>; | |
243 | clocks = <&osc>; | |
244 | clock-output-names = "genpll", "phy", "ethernetclk", | |
245 | "usbclk", "iprocfast", "sata1", | |
246 | "sata2"; | |
247 | }; | |
248 | ||
9faa5960 HM |
249 | nand: nand@18028000 { |
250 | compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; | |
251 | reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; | |
252 | reg-names = "nand", "iproc-idm", "iproc-ext"; | |
253 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
254 | ||
255 | #address-cells = <1>; | |
256 | #size-cells = <0>; | |
257 | ||
258 | brcm,nand-has-wp; | |
259 | }; | |
d27509f1 | 260 | }; |