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2440946c SH |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC | |
3 | * | |
4 | * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | |
5 | * | |
6 | * based on GPL'ed 2.6 kernel sources | |
7 | * (c) Marvell International Ltd. | |
8 | * | |
267f9107 AT |
9 | * This file is dual-licensed: you can use it either under the terms |
10 | * of the GPL or the X11 license, at your option. Note that this dual | |
11 | * licensing only applies to this file, and not this project as a | |
12 | * whole. | |
13 | * | |
14 | * a) This file is licensed under the terms of the GNU General Public | |
15 | * License version 2. This program is licensed "as is" without any | |
16 | * warranty of any kind, whether express or implied. | |
17 | * | |
18 | * Or, alternatively, | |
19 | * | |
20 | * b) Permission is hereby granted, free of charge, to any person | |
21 | * obtaining a copy of this software and associated documentation | |
22 | * files (the "Software"), to deal in the Software without | |
23 | * restriction, including without limitation the rights to use, | |
24 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
25 | * sell copies of the Software, and to permit persons to whom the | |
26 | * Software is furnished to do so, subject to the following | |
27 | * conditions: | |
28 | * | |
29 | * The above copyright notice and this permission notice shall be | |
30 | * included in all copies or substantial portions of the Software. | |
31 | * | |
32 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
33 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
34 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
35 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
36 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
37 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
38 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
39 | * OTHER DEALINGS IN THE SOFTWARE. | |
2440946c SH |
40 | */ |
41 | ||
42 | #include "skeleton.dtsi" | |
36601dbf | 43 | #include <dt-bindings/clock/berlin2.h> |
2440946c SH |
44 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
45 | ||
46 | / { | |
47 | model = "Marvell Armada 1500 (BG2) SoC"; | |
48 | compatible = "marvell,berlin2", "marvell,berlin"; | |
49 | ||
487eacb9 JZ |
50 | aliases { |
51 | serial0 = &uart0; | |
52 | serial1 = &uart1; | |
53 | serial2 = &uart2; | |
54 | }; | |
55 | ||
2440946c SH |
56 | cpus { |
57 | #address-cells = <1>; | |
58 | #size-cells = <0>; | |
460d02ac | 59 | enable-method = "marvell,berlin-smp"; |
2440946c SH |
60 | |
61 | cpu@0 { | |
62 | compatible = "marvell,pj4b"; | |
63 | device_type = "cpu"; | |
64 | next-level-cache = <&l2>; | |
65 | reg = <0>; | |
2e1782ad AT |
66 | |
67 | clocks = <&chip_clk CLKID_CPU>; | |
68 | clock-latency = <100000>; | |
69 | operating-points = < | |
70 | /* kHz uV */ | |
71 | 1200000 1200000 | |
72 | 1000000 1200000 | |
73 | 800000 1200000 | |
74 | 600000 1200000 | |
75 | >; | |
2440946c SH |
76 | }; |
77 | ||
78 | cpu@1 { | |
79 | compatible = "marvell,pj4b"; | |
80 | device_type = "cpu"; | |
81 | next-level-cache = <&l2>; | |
82 | reg = <1>; | |
83 | }; | |
84 | }; | |
85 | ||
36601dbf SH |
86 | refclk: oscillator { |
87 | compatible = "fixed-clock"; | |
88 | #clock-cells = <0>; | |
89 | clock-frequency = <25000000>; | |
2440946c SH |
90 | }; |
91 | ||
92 | soc { | |
93 | compatible = "simple-bus"; | |
94 | #address-cells = <1>; | |
95 | #size-cells = <1>; | |
96 | interrupt-parent = <&gic>; | |
97 | ||
98 | ranges = <0 0xf7000000 0x1000000>; | |
99 | ||
652538c4 SH |
100 | sdhci0: sdhci@ab0000 { |
101 | compatible = "mrvl,pxav3-mmc"; | |
102 | reg = <0xab0000 0x200>; | |
18df8165 | 103 | clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; |
652538c4 SH |
104 | clock-names = "io", "core"; |
105 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
106 | status = "disabled"; | |
107 | }; | |
108 | ||
109 | sdhci1: sdhci@ab0800 { | |
110 | compatible = "mrvl,pxav3-mmc"; | |
111 | reg = <0xab0800 0x200>; | |
18df8165 | 112 | clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>; |
652538c4 SH |
113 | clock-names = "io", "core"; |
114 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
115 | status = "disabled"; | |
116 | }; | |
117 | ||
118 | sdhci2: sdhci@ab1000 { | |
119 | compatible = "mrvl,pxav3-mmc"; | |
120 | reg = <0xab1000 0x200>; | |
121 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
18df8165 | 122 | clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>; |
652538c4 SH |
123 | clock-names = "io", "core"; |
124 | pinctrl-0 = <&emmc_pmux>; | |
125 | pinctrl-names = "default"; | |
126 | status = "disabled"; | |
127 | }; | |
128 | ||
2440946c SH |
129 | l2: l2-cache-controller@ac0000 { |
130 | compatible = "marvell,tauros3-cache", "arm,pl310-cache"; | |
131 | reg = <0xac0000 0x1000>; | |
132 | cache-unified; | |
133 | cache-level = <2>; | |
134 | }; | |
135 | ||
0bd4b346 SH |
136 | scu: snoop-control-unit@ad0000 { |
137 | compatible = "arm,cortex-a9-scu"; | |
138 | reg = <0xad0000 0x58>; | |
139 | }; | |
140 | ||
2440946c SH |
141 | gic: interrupt-controller@ad1000 { |
142 | compatible = "arm,cortex-a9-gic"; | |
143 | reg = <0xad1000 0x1000>, <0xad0100 0x0100>; | |
144 | interrupt-controller; | |
145 | #interrupt-cells = <3>; | |
146 | }; | |
147 | ||
148 | local-timer@ad0600 { | |
149 | compatible = "arm,cortex-a9-twd-timer"; | |
150 | reg = <0xad0600 0x20>; | |
2356d2f3 | 151 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
18df8165 | 152 | clocks = <&chip_clk CLKID_TWD>; |
2440946c SH |
153 | }; |
154 | ||
ae01f64b SH |
155 | eth1: ethernet@b90000 { |
156 | compatible = "marvell,pxa168-eth"; | |
157 | reg = <0xb90000 0x10000>; | |
18df8165 | 158 | clocks = <&chip_clk CLKID_GETH1>; |
ae01f64b SH |
159 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
160 | /* set by bootloader */ | |
161 | local-mac-address = [00 00 00 00 00 00]; | |
162 | #address-cells = <1>; | |
163 | #size-cells = <0>; | |
164 | phy-connection-type = "mii"; | |
165 | phy-handle = <ðphy1>; | |
166 | status = "disabled"; | |
167 | ||
168 | ethphy1: ethernet-phy@0 { | |
169 | reg = <0>; | |
170 | }; | |
171 | }; | |
172 | ||
460d02ac AT |
173 | cpu-ctrl@dd0000 { |
174 | compatible = "marvell,berlin-cpu-ctrl"; | |
175 | reg = <0xdd0000 0x10000>; | |
176 | }; | |
177 | ||
ae01f64b SH |
178 | eth0: ethernet@e50000 { |
179 | compatible = "marvell,pxa168-eth"; | |
180 | reg = <0xe50000 0x10000>; | |
18df8165 | 181 | clocks = <&chip_clk CLKID_GETH0>; |
ae01f64b SH |
182 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
183 | /* set by bootloader */ | |
184 | local-mac-address = [00 00 00 00 00 00]; | |
185 | #address-cells = <1>; | |
186 | #size-cells = <0>; | |
187 | phy-connection-type = "mii"; | |
188 | phy-handle = <ðphy0>; | |
189 | status = "disabled"; | |
190 | ||
191 | ethphy0: ethernet-phy@0 { | |
192 | reg = <0>; | |
193 | }; | |
194 | }; | |
195 | ||
2440946c SH |
196 | apb@e80000 { |
197 | compatible = "simple-bus"; | |
198 | #address-cells = <1>; | |
199 | #size-cells = <1>; | |
200 | ||
201 | ranges = <0 0xe80000 0x10000>; | |
202 | interrupt-parent = <&aic>; | |
203 | ||
6d3da018 AT |
204 | gpio0: gpio@0400 { |
205 | compatible = "snps,dw-apb-gpio"; | |
206 | reg = <0x0400 0x400>; | |
207 | #address-cells = <1>; | |
208 | #size-cells = <0>; | |
209 | ||
210 | porta: gpio-port@0 { | |
211 | compatible = "snps,dw-apb-gpio-port"; | |
212 | gpio-controller; | |
213 | #gpio-cells = <2>; | |
214 | snps,nr-gpios = <8>; | |
215 | reg = <0>; | |
216 | interrupt-controller; | |
217 | #interrupt-cells = <2>; | |
218 | interrupts = <0>; | |
219 | }; | |
220 | }; | |
221 | ||
222 | gpio1: gpio@0800 { | |
223 | compatible = "snps,dw-apb-gpio"; | |
224 | reg = <0x0800 0x400>; | |
225 | #address-cells = <1>; | |
226 | #size-cells = <0>; | |
227 | ||
228 | portb: gpio-port@1 { | |
229 | compatible = "snps,dw-apb-gpio-port"; | |
230 | gpio-controller; | |
231 | #gpio-cells = <2>; | |
232 | snps,nr-gpios = <8>; | |
233 | reg = <0>; | |
234 | interrupt-controller; | |
235 | #interrupt-cells = <2>; | |
236 | interrupts = <1>; | |
237 | }; | |
238 | }; | |
239 | ||
240 | gpio2: gpio@0c00 { | |
241 | compatible = "snps,dw-apb-gpio"; | |
242 | reg = <0x0c00 0x400>; | |
243 | #address-cells = <1>; | |
244 | #size-cells = <0>; | |
245 | ||
246 | portc: gpio-port@2 { | |
247 | compatible = "snps,dw-apb-gpio-port"; | |
248 | gpio-controller; | |
249 | #gpio-cells = <2>; | |
250 | snps,nr-gpios = <8>; | |
251 | reg = <0>; | |
252 | interrupt-controller; | |
253 | #interrupt-cells = <2>; | |
254 | interrupts = <2>; | |
255 | }; | |
256 | }; | |
257 | ||
258 | gpio3: gpio@1000 { | |
259 | compatible = "snps,dw-apb-gpio"; | |
260 | reg = <0x1000 0x400>; | |
261 | #address-cells = <1>; | |
262 | #size-cells = <0>; | |
263 | ||
264 | portd: gpio-port@3 { | |
265 | compatible = "snps,dw-apb-gpio-port"; | |
266 | gpio-controller; | |
267 | #gpio-cells = <2>; | |
268 | snps,nr-gpios = <8>; | |
269 | reg = <0>; | |
270 | interrupt-controller; | |
271 | #interrupt-cells = <2>; | |
272 | interrupts = <3>; | |
273 | }; | |
274 | }; | |
275 | ||
2440946c SH |
276 | timer0: timer@2c00 { |
277 | compatible = "snps,dw-apb-timer"; | |
278 | reg = <0x2c00 0x14>; | |
279 | interrupts = <8>; | |
18df8165 | 280 | clocks = <&chip_clk CLKID_CFG>; |
2440946c SH |
281 | clock-names = "timer"; |
282 | status = "okay"; | |
283 | }; | |
284 | ||
285 | timer1: timer@2c14 { | |
286 | compatible = "snps,dw-apb-timer"; | |
287 | reg = <0x2c14 0x14>; | |
288 | interrupts = <9>; | |
18df8165 | 289 | clocks = <&chip_clk CLKID_CFG>; |
2440946c SH |
290 | clock-names = "timer"; |
291 | status = "okay"; | |
292 | }; | |
293 | ||
294 | timer2: timer@2c28 { | |
295 | compatible = "snps,dw-apb-timer"; | |
296 | reg = <0x2c28 0x14>; | |
297 | interrupts = <10>; | |
18df8165 | 298 | clocks = <&chip_clk CLKID_CFG>; |
2440946c SH |
299 | clock-names = "timer"; |
300 | status = "disabled"; | |
301 | }; | |
302 | ||
303 | timer3: timer@2c3c { | |
304 | compatible = "snps,dw-apb-timer"; | |
305 | reg = <0x2c3c 0x14>; | |
306 | interrupts = <11>; | |
18df8165 | 307 | clocks = <&chip_clk CLKID_CFG>; |
2440946c SH |
308 | clock-names = "timer"; |
309 | status = "disabled"; | |
310 | }; | |
311 | ||
312 | timer4: timer@2c50 { | |
313 | compatible = "snps,dw-apb-timer"; | |
314 | reg = <0x2c50 0x14>; | |
315 | interrupts = <12>; | |
18df8165 | 316 | clocks = <&chip_clk CLKID_CFG>; |
2440946c SH |
317 | clock-names = "timer"; |
318 | status = "disabled"; | |
319 | }; | |
320 | ||
321 | timer5: timer@2c64 { | |
322 | compatible = "snps,dw-apb-timer"; | |
323 | reg = <0x2c64 0x14>; | |
324 | interrupts = <13>; | |
18df8165 | 325 | clocks = <&chip_clk CLKID_CFG>; |
2440946c SH |
326 | clock-names = "timer"; |
327 | status = "disabled"; | |
328 | }; | |
329 | ||
330 | timer6: timer@2c78 { | |
331 | compatible = "snps,dw-apb-timer"; | |
332 | reg = <0x2c78 0x14>; | |
333 | interrupts = <14>; | |
18df8165 | 334 | clocks = <&chip_clk CLKID_CFG>; |
2440946c SH |
335 | clock-names = "timer"; |
336 | status = "disabled"; | |
337 | }; | |
338 | ||
339 | timer7: timer@2c8c { | |
340 | compatible = "snps,dw-apb-timer"; | |
341 | reg = <0x2c8c 0x14>; | |
342 | interrupts = <15>; | |
18df8165 | 343 | clocks = <&chip_clk CLKID_CFG>; |
2440946c SH |
344 | clock-names = "timer"; |
345 | status = "disabled"; | |
346 | }; | |
347 | ||
348 | aic: interrupt-controller@3000 { | |
349 | compatible = "snps,dw-apb-ictl"; | |
350 | reg = <0x3000 0xc00>; | |
351 | interrupt-controller; | |
352 | #interrupt-cells = <1>; | |
353 | interrupt-parent = <&gic>; | |
354 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
355 | }; | |
356 | }; | |
357 | ||
878a3ee3 SH |
358 | ahci: sata@e90000 { |
359 | compatible = "marvell,berlin2-ahci", "generic-ahci"; | |
360 | reg = <0xe90000 0x1000>; | |
361 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
18df8165 | 362 | clocks = <&chip_clk CLKID_SATA>; |
878a3ee3 SH |
363 | #address-cells = <1>; |
364 | #size-cells = <0>; | |
365 | ||
366 | sata0: sata-port@0 { | |
367 | reg = <0>; | |
368 | phys = <&sata_phy 0>; | |
369 | status = "disabled"; | |
370 | }; | |
371 | ||
372 | sata1: sata-port@1 { | |
373 | reg = <1>; | |
374 | phys = <&sata_phy 1>; | |
375 | status = "disabled"; | |
376 | }; | |
377 | }; | |
378 | ||
379 | sata_phy: phy@e900a0 { | |
380 | compatible = "marvell,berlin2-sata-phy"; | |
381 | reg = <0xe900a0 0x200>; | |
18df8165 | 382 | clocks = <&chip_clk CLKID_SATA>; |
878a3ee3 SH |
383 | #address-cells = <1>; |
384 | #size-cells = <0>; | |
385 | #phy-cells = <1>; | |
386 | status = "disabled"; | |
387 | ||
388 | sata-phy@0 { | |
389 | reg = <0>; | |
390 | }; | |
391 | ||
392 | sata-phy@1 { | |
393 | reg = <1>; | |
394 | }; | |
395 | }; | |
396 | ||
36601dbf | 397 | chip: chip-control@ea0000 { |
f3f94f71 | 398 | compatible = "simple-mfd", "syscon"; |
36601dbf | 399 | reg = <0xea0000 0x400>; |
652538c4 | 400 | |
18df8165 AT |
401 | chip_clk: clock { |
402 | compatible = "marvell,berlin2-clk"; | |
403 | #clock-cells = <1>; | |
404 | clocks = <&refclk>; | |
405 | clock-names = "refclk"; | |
406 | }; | |
652538c4 | 407 | |
630c986b AT |
408 | soc_pinctrl: pin-controller { |
409 | compatible = "marvell,berlin2-soc-pinctrl"; | |
410 | ||
411 | emmc_pmux: emmc-pmux { | |
412 | groups = "G26"; | |
413 | function = "emmc"; | |
414 | }; | |
652538c4 | 415 | }; |
43225728 AT |
416 | |
417 | chip_rst: reset { | |
418 | compatible = "marvell,berlin2-reset"; | |
419 | #reset-cells = <2>; | |
652538c4 | 420 | }; |
0bd4b346 SH |
421 | }; |
422 | ||
8eaaaa6f AT |
423 | pwm: pwm@f20000 { |
424 | compatible = "marvell,berlin-pwm"; | |
425 | reg = <0xf20000 0x40>; | |
426 | clocks = <&chip_clk CLKID_CFG>; | |
427 | #pwm-cells = <3>; | |
428 | }; | |
429 | ||
2440946c SH |
430 | apb@fc0000 { |
431 | compatible = "simple-bus"; | |
432 | #address-cells = <1>; | |
433 | #size-cells = <1>; | |
434 | ||
435 | ranges = <0 0xfc0000 0x10000>; | |
436 | interrupt-parent = <&sic>; | |
437 | ||
4b6c390b JZ |
438 | wdt0: watchdog@1000 { |
439 | compatible = "snps,dw-wdt"; | |
440 | reg = <0x1000 0x100>; | |
441 | clocks = <&refclk>; | |
442 | interrupts = <0>; | |
443 | }; | |
444 | ||
445 | wdt1: watchdog@2000 { | |
446 | compatible = "snps,dw-wdt"; | |
447 | reg = <0x2000 0x100>; | |
448 | clocks = <&refclk>; | |
449 | interrupts = <1>; | |
450 | status = "disabled"; | |
451 | }; | |
452 | ||
453 | wdt2: watchdog@3000 { | |
454 | compatible = "snps,dw-wdt"; | |
455 | reg = <0x3000 0x100>; | |
456 | clocks = <&refclk>; | |
457 | interrupts = <2>; | |
458 | status = "disabled"; | |
459 | }; | |
460 | ||
6d3da018 AT |
461 | sm_gpio1: gpio@5000 { |
462 | compatible = "snps,dw-apb-gpio"; | |
463 | reg = <0x5000 0x400>; | |
464 | #address-cells = <1>; | |
465 | #size-cells = <0>; | |
466 | ||
467 | portf: gpio-port@5 { | |
468 | compatible = "snps,dw-apb-gpio-port"; | |
469 | gpio-controller; | |
470 | #gpio-cells = <2>; | |
471 | snps,nr-gpios = <8>; | |
472 | reg = <0>; | |
473 | }; | |
474 | }; | |
475 | ||
476 | sm_gpio0: gpio@c000 { | |
477 | compatible = "snps,dw-apb-gpio"; | |
478 | reg = <0xc000 0x400>; | |
479 | #address-cells = <1>; | |
480 | #size-cells = <0>; | |
481 | ||
482 | porte: gpio-port@4 { | |
483 | compatible = "snps,dw-apb-gpio-port"; | |
484 | gpio-controller; | |
485 | #gpio-cells = <2>; | |
486 | snps,nr-gpios = <8>; | |
487 | reg = <0>; | |
488 | interrupt-controller; | |
489 | #interrupt-cells = <2>; | |
490 | interrupts = <11>; | |
491 | }; | |
492 | }; | |
493 | ||
2440946c SH |
494 | uart0: serial@9000 { |
495 | compatible = "snps,dw-apb-uart"; | |
496 | reg = <0x9000 0x100>; | |
497 | reg-shift = <2>; | |
498 | reg-io-width = <1>; | |
499 | interrupts = <8>; | |
36601dbf | 500 | clocks = <&refclk>; |
50cc24ff AT |
501 | pinctrl-0 = <&uart0_pmux>; |
502 | pinctrl-names = "default"; | |
2440946c SH |
503 | status = "disabled"; |
504 | }; | |
505 | ||
506 | uart1: serial@a000 { | |
507 | compatible = "snps,dw-apb-uart"; | |
508 | reg = <0xa000 0x100>; | |
509 | reg-shift = <2>; | |
510 | reg-io-width = <1>; | |
511 | interrupts = <9>; | |
36601dbf | 512 | clocks = <&refclk>; |
50cc24ff AT |
513 | pinctrl-0 = <&uart1_pmux>; |
514 | pinctrl-names = "default"; | |
2440946c SH |
515 | status = "disabled"; |
516 | }; | |
517 | ||
518 | uart2: serial@b000 { | |
519 | compatible = "snps,dw-apb-uart"; | |
520 | reg = <0xb000 0x100>; | |
521 | reg-shift = <2>; | |
522 | reg-io-width = <1>; | |
523 | interrupts = <10>; | |
36601dbf | 524 | clocks = <&refclk>; |
50cc24ff AT |
525 | pinctrl-0 = <&uart2_pmux>; |
526 | pinctrl-names = "default"; | |
2440946c SH |
527 | status = "disabled"; |
528 | }; | |
529 | ||
50cc24ff | 530 | sysctrl: system-controller@d000 { |
f3f94f71 | 531 | compatible = "simple-mfd", "syscon"; |
50cc24ff AT |
532 | reg = <0xd000 0x100>; |
533 | ||
630c986b AT |
534 | sys_pinctrl: pin-controller { |
535 | compatible = "marvell,berlin2-system-pinctrl"; | |
536 | uart0_pmux: uart0-pmux { | |
537 | groups = "GSM4"; | |
538 | function = "uart0"; | |
539 | }; | |
540 | ||
541 | uart1_pmux: uart1-pmux { | |
542 | groups = "GSM5"; | |
543 | function = "uart1"; | |
544 | }; | |
545 | uart2_pmux: uart2-pmux { | |
546 | groups = "GSM3"; | |
547 | function = "uart2"; | |
548 | }; | |
50cc24ff AT |
549 | }; |
550 | }; | |
551 | ||
2440946c SH |
552 | sic: interrupt-controller@e000 { |
553 | compatible = "snps,dw-apb-ictl"; | |
554 | reg = <0xe000 0x400>; | |
555 | interrupt-controller; | |
556 | #interrupt-cells = <1>; | |
557 | interrupt-parent = <&gic>; | |
558 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
559 | }; | |
560 | }; | |
561 | }; | |
562 | }; |