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2440946c SH |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC | |
3 | * | |
4 | * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | |
5 | * | |
6 | * based on GPL'ed 2.6 kernel sources | |
7 | * (c) Marvell International Ltd. | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include "skeleton.dtsi" | |
36601dbf | 15 | #include <dt-bindings/clock/berlin2.h> |
2440946c SH |
16 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
17 | ||
18 | / { | |
19 | model = "Marvell Armada 1500 (BG2) SoC"; | |
20 | compatible = "marvell,berlin2", "marvell,berlin"; | |
21 | ||
22 | cpus { | |
23 | #address-cells = <1>; | |
24 | #size-cells = <0>; | |
460d02ac | 25 | enable-method = "marvell,berlin-smp"; |
2440946c SH |
26 | |
27 | cpu@0 { | |
28 | compatible = "marvell,pj4b"; | |
29 | device_type = "cpu"; | |
30 | next-level-cache = <&l2>; | |
31 | reg = <0>; | |
32 | }; | |
33 | ||
34 | cpu@1 { | |
35 | compatible = "marvell,pj4b"; | |
36 | device_type = "cpu"; | |
37 | next-level-cache = <&l2>; | |
38 | reg = <1>; | |
39 | }; | |
40 | }; | |
41 | ||
36601dbf SH |
42 | refclk: oscillator { |
43 | compatible = "fixed-clock"; | |
44 | #clock-cells = <0>; | |
45 | clock-frequency = <25000000>; | |
2440946c SH |
46 | }; |
47 | ||
48 | soc { | |
49 | compatible = "simple-bus"; | |
50 | #address-cells = <1>; | |
51 | #size-cells = <1>; | |
52 | interrupt-parent = <&gic>; | |
53 | ||
54 | ranges = <0 0xf7000000 0x1000000>; | |
55 | ||
56 | l2: l2-cache-controller@ac0000 { | |
57 | compatible = "marvell,tauros3-cache", "arm,pl310-cache"; | |
58 | reg = <0xac0000 0x1000>; | |
59 | cache-unified; | |
60 | cache-level = <2>; | |
61 | }; | |
62 | ||
0bd4b346 SH |
63 | scu: snoop-control-unit@ad0000 { |
64 | compatible = "arm,cortex-a9-scu"; | |
65 | reg = <0xad0000 0x58>; | |
66 | }; | |
67 | ||
2440946c SH |
68 | gic: interrupt-controller@ad1000 { |
69 | compatible = "arm,cortex-a9-gic"; | |
70 | reg = <0xad1000 0x1000>, <0xad0100 0x0100>; | |
71 | interrupt-controller; | |
72 | #interrupt-cells = <3>; | |
73 | }; | |
74 | ||
75 | local-timer@ad0600 { | |
76 | compatible = "arm,cortex-a9-twd-timer"; | |
77 | reg = <0xad0600 0x20>; | |
78 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
36601dbf | 79 | clocks = <&chip CLKID_TWD>; |
2440946c SH |
80 | }; |
81 | ||
460d02ac AT |
82 | cpu-ctrl@dd0000 { |
83 | compatible = "marvell,berlin-cpu-ctrl"; | |
84 | reg = <0xdd0000 0x10000>; | |
85 | }; | |
86 | ||
2440946c SH |
87 | apb@e80000 { |
88 | compatible = "simple-bus"; | |
89 | #address-cells = <1>; | |
90 | #size-cells = <1>; | |
91 | ||
92 | ranges = <0 0xe80000 0x10000>; | |
93 | interrupt-parent = <&aic>; | |
94 | ||
6d3da018 AT |
95 | gpio0: gpio@0400 { |
96 | compatible = "snps,dw-apb-gpio"; | |
97 | reg = <0x0400 0x400>; | |
98 | #address-cells = <1>; | |
99 | #size-cells = <0>; | |
100 | ||
101 | porta: gpio-port@0 { | |
102 | compatible = "snps,dw-apb-gpio-port"; | |
103 | gpio-controller; | |
104 | #gpio-cells = <2>; | |
105 | snps,nr-gpios = <8>; | |
106 | reg = <0>; | |
107 | interrupt-controller; | |
108 | #interrupt-cells = <2>; | |
109 | interrupts = <0>; | |
110 | }; | |
111 | }; | |
112 | ||
113 | gpio1: gpio@0800 { | |
114 | compatible = "snps,dw-apb-gpio"; | |
115 | reg = <0x0800 0x400>; | |
116 | #address-cells = <1>; | |
117 | #size-cells = <0>; | |
118 | ||
119 | portb: gpio-port@1 { | |
120 | compatible = "snps,dw-apb-gpio-port"; | |
121 | gpio-controller; | |
122 | #gpio-cells = <2>; | |
123 | snps,nr-gpios = <8>; | |
124 | reg = <0>; | |
125 | interrupt-controller; | |
126 | #interrupt-cells = <2>; | |
127 | interrupts = <1>; | |
128 | }; | |
129 | }; | |
130 | ||
131 | gpio2: gpio@0c00 { | |
132 | compatible = "snps,dw-apb-gpio"; | |
133 | reg = <0x0c00 0x400>; | |
134 | #address-cells = <1>; | |
135 | #size-cells = <0>; | |
136 | ||
137 | portc: gpio-port@2 { | |
138 | compatible = "snps,dw-apb-gpio-port"; | |
139 | gpio-controller; | |
140 | #gpio-cells = <2>; | |
141 | snps,nr-gpios = <8>; | |
142 | reg = <0>; | |
143 | interrupt-controller; | |
144 | #interrupt-cells = <2>; | |
145 | interrupts = <2>; | |
146 | }; | |
147 | }; | |
148 | ||
149 | gpio3: gpio@1000 { | |
150 | compatible = "snps,dw-apb-gpio"; | |
151 | reg = <0x1000 0x400>; | |
152 | #address-cells = <1>; | |
153 | #size-cells = <0>; | |
154 | ||
155 | portd: gpio-port@3 { | |
156 | compatible = "snps,dw-apb-gpio-port"; | |
157 | gpio-controller; | |
158 | #gpio-cells = <2>; | |
159 | snps,nr-gpios = <8>; | |
160 | reg = <0>; | |
161 | interrupt-controller; | |
162 | #interrupt-cells = <2>; | |
163 | interrupts = <3>; | |
164 | }; | |
165 | }; | |
166 | ||
2440946c SH |
167 | timer0: timer@2c00 { |
168 | compatible = "snps,dw-apb-timer"; | |
169 | reg = <0x2c00 0x14>; | |
170 | interrupts = <8>; | |
36601dbf | 171 | clocks = <&chip CLKID_CFG>; |
2440946c SH |
172 | clock-names = "timer"; |
173 | status = "okay"; | |
174 | }; | |
175 | ||
176 | timer1: timer@2c14 { | |
177 | compatible = "snps,dw-apb-timer"; | |
178 | reg = <0x2c14 0x14>; | |
179 | interrupts = <9>; | |
36601dbf | 180 | clocks = <&chip CLKID_CFG>; |
2440946c SH |
181 | clock-names = "timer"; |
182 | status = "okay"; | |
183 | }; | |
184 | ||
185 | timer2: timer@2c28 { | |
186 | compatible = "snps,dw-apb-timer"; | |
187 | reg = <0x2c28 0x14>; | |
188 | interrupts = <10>; | |
36601dbf | 189 | clocks = <&chip CLKID_CFG>; |
2440946c SH |
190 | clock-names = "timer"; |
191 | status = "disabled"; | |
192 | }; | |
193 | ||
194 | timer3: timer@2c3c { | |
195 | compatible = "snps,dw-apb-timer"; | |
196 | reg = <0x2c3c 0x14>; | |
197 | interrupts = <11>; | |
36601dbf | 198 | clocks = <&chip CLKID_CFG>; |
2440946c SH |
199 | clock-names = "timer"; |
200 | status = "disabled"; | |
201 | }; | |
202 | ||
203 | timer4: timer@2c50 { | |
204 | compatible = "snps,dw-apb-timer"; | |
205 | reg = <0x2c50 0x14>; | |
206 | interrupts = <12>; | |
36601dbf | 207 | clocks = <&chip CLKID_CFG>; |
2440946c SH |
208 | clock-names = "timer"; |
209 | status = "disabled"; | |
210 | }; | |
211 | ||
212 | timer5: timer@2c64 { | |
213 | compatible = "snps,dw-apb-timer"; | |
214 | reg = <0x2c64 0x14>; | |
215 | interrupts = <13>; | |
36601dbf | 216 | clocks = <&chip CLKID_CFG>; |
2440946c SH |
217 | clock-names = "timer"; |
218 | status = "disabled"; | |
219 | }; | |
220 | ||
221 | timer6: timer@2c78 { | |
222 | compatible = "snps,dw-apb-timer"; | |
223 | reg = <0x2c78 0x14>; | |
224 | interrupts = <14>; | |
36601dbf | 225 | clocks = <&chip CLKID_CFG>; |
2440946c SH |
226 | clock-names = "timer"; |
227 | status = "disabled"; | |
228 | }; | |
229 | ||
230 | timer7: timer@2c8c { | |
231 | compatible = "snps,dw-apb-timer"; | |
232 | reg = <0x2c8c 0x14>; | |
233 | interrupts = <15>; | |
36601dbf | 234 | clocks = <&chip CLKID_CFG>; |
2440946c SH |
235 | clock-names = "timer"; |
236 | status = "disabled"; | |
237 | }; | |
238 | ||
239 | aic: interrupt-controller@3000 { | |
240 | compatible = "snps,dw-apb-ictl"; | |
241 | reg = <0x3000 0xc00>; | |
242 | interrupt-controller; | |
243 | #interrupt-cells = <1>; | |
244 | interrupt-parent = <&gic>; | |
245 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
246 | }; | |
247 | }; | |
248 | ||
36601dbf SH |
249 | chip: chip-control@ea0000 { |
250 | compatible = "marvell,berlin2-chip-ctrl"; | |
251 | #clock-cells = <1>; | |
1e27a261 | 252 | #reset-cells = <2>; |
36601dbf SH |
253 | reg = <0xea0000 0x400>; |
254 | clocks = <&refclk>; | |
255 | clock-names = "refclk"; | |
0bd4b346 SH |
256 | }; |
257 | ||
2440946c SH |
258 | apb@fc0000 { |
259 | compatible = "simple-bus"; | |
260 | #address-cells = <1>; | |
261 | #size-cells = <1>; | |
262 | ||
263 | ranges = <0 0xfc0000 0x10000>; | |
264 | interrupt-parent = <&sic>; | |
265 | ||
6d3da018 AT |
266 | sm_gpio1: gpio@5000 { |
267 | compatible = "snps,dw-apb-gpio"; | |
268 | reg = <0x5000 0x400>; | |
269 | #address-cells = <1>; | |
270 | #size-cells = <0>; | |
271 | ||
272 | portf: gpio-port@5 { | |
273 | compatible = "snps,dw-apb-gpio-port"; | |
274 | gpio-controller; | |
275 | #gpio-cells = <2>; | |
276 | snps,nr-gpios = <8>; | |
277 | reg = <0>; | |
278 | }; | |
279 | }; | |
280 | ||
281 | sm_gpio0: gpio@c000 { | |
282 | compatible = "snps,dw-apb-gpio"; | |
283 | reg = <0xc000 0x400>; | |
284 | #address-cells = <1>; | |
285 | #size-cells = <0>; | |
286 | ||
287 | porte: gpio-port@4 { | |
288 | compatible = "snps,dw-apb-gpio-port"; | |
289 | gpio-controller; | |
290 | #gpio-cells = <2>; | |
291 | snps,nr-gpios = <8>; | |
292 | reg = <0>; | |
293 | interrupt-controller; | |
294 | #interrupt-cells = <2>; | |
295 | interrupts = <11>; | |
296 | }; | |
297 | }; | |
298 | ||
2440946c SH |
299 | uart0: serial@9000 { |
300 | compatible = "snps,dw-apb-uart"; | |
301 | reg = <0x9000 0x100>; | |
302 | reg-shift = <2>; | |
303 | reg-io-width = <1>; | |
304 | interrupts = <8>; | |
36601dbf | 305 | clocks = <&refclk>; |
50cc24ff AT |
306 | pinctrl-0 = <&uart0_pmux>; |
307 | pinctrl-names = "default"; | |
2440946c SH |
308 | status = "disabled"; |
309 | }; | |
310 | ||
311 | uart1: serial@a000 { | |
312 | compatible = "snps,dw-apb-uart"; | |
313 | reg = <0xa000 0x100>; | |
314 | reg-shift = <2>; | |
315 | reg-io-width = <1>; | |
316 | interrupts = <9>; | |
36601dbf | 317 | clocks = <&refclk>; |
50cc24ff AT |
318 | pinctrl-0 = <&uart1_pmux>; |
319 | pinctrl-names = "default"; | |
2440946c SH |
320 | status = "disabled"; |
321 | }; | |
322 | ||
323 | uart2: serial@b000 { | |
324 | compatible = "snps,dw-apb-uart"; | |
325 | reg = <0xb000 0x100>; | |
326 | reg-shift = <2>; | |
327 | reg-io-width = <1>; | |
328 | interrupts = <10>; | |
36601dbf | 329 | clocks = <&refclk>; |
50cc24ff AT |
330 | pinctrl-0 = <&uart2_pmux>; |
331 | pinctrl-names = "default"; | |
2440946c SH |
332 | status = "disabled"; |
333 | }; | |
334 | ||
50cc24ff AT |
335 | sysctrl: system-controller@d000 { |
336 | compatible = "marvell,berlin2-system-ctrl"; | |
337 | reg = <0xd000 0x100>; | |
338 | ||
339 | uart0_pmux: uart0-pmux { | |
340 | groups = "GSM4"; | |
341 | function = "uart0"; | |
342 | }; | |
343 | ||
344 | uart1_pmux: uart1-pmux { | |
345 | groups = "GSM5"; | |
346 | function = "uart1"; | |
347 | }; | |
348 | ||
349 | uart2_pmux: uart2-pmux { | |
350 | groups = "GSM3"; | |
351 | function = "uart2"; | |
352 | }; | |
353 | }; | |
354 | ||
2440946c SH |
355 | sic: interrupt-controller@e000 { |
356 | compatible = "snps,dw-apb-ictl"; | |
357 | reg = <0xe000 0x400>; | |
358 | interrupt-controller; | |
359 | #interrupt-cells = <1>; | |
360 | interrupt-parent = <&gic>; | |
361 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
362 | }; | |
363 | }; | |
364 | }; | |
365 | }; |