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ARM: dts: berlin: convert BG2CD to DT clock nodes
[deliverable/linux.git] / arch / arm / boot / dts / berlin2.dtsi
CommitLineData
2440946c
SH		 1/*
2 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
3 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include "skeleton.dtsi"
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16
17/ {
18 model = "Marvell Armada 1500 (BG2) SoC";
19 compatible = "marvell,berlin2", "marvell,berlin";
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu@0 {
26 compatible = "marvell,pj4b";
27 device_type = "cpu";
28 next-level-cache = <&l2>;
29 reg = <0>;
30 };
31
32 cpu@1 {
33 compatible = "marvell,pj4b";
34 device_type = "cpu";
35 next-level-cache = <&l2>;
36 reg = <1>;
37 };
38 };
39
40 clocks {
41 smclk: sysmgr-clock {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <25000000>;
45 };
46
47 cfgclk: cfg-clock {
48 compatible = "fixed-clock";
49 #clock-cells = <0>;
50 clock-frequency = <100000000>;
51 };
52
53 sysclk: system-clock {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <400000000>;
57 };
58 };
59
60 soc {
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
64 interrupt-parent = <&gic>;
65
66 ranges = <0 0xf7000000 0x1000000>;
67
68 l2: l2-cache-controller@ac0000 {
69 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
70 reg = <0xac0000 0x1000>;
71 cache-unified;
72 cache-level = <2>;
73 };
74
0bd4b346
SH		 75 scu: snoop-control-unit@ad0000 {
76 compatible = "arm,cortex-a9-scu";
77 reg = <0xad0000 0x58>;
78 };
79
2440946c
SH		 80 gic: interrupt-controller@ad1000 {
81 compatible = "arm,cortex-a9-gic";
82 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
83 interrupt-controller;
84 #interrupt-cells = <3>;
85 };
86
87 local-timer@ad0600 {
88 compatible = "arm,cortex-a9-twd-timer";
89 reg = <0xad0600 0x20>;
90 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
91 clocks = <&sysclk>;
92 };
93
94 apb@e80000 {
95 compatible = "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98
99 ranges = <0 0xe80000 0x10000>;
100 interrupt-parent = <&aic>;
101
6d3da018
AT		 102 gpio0: gpio@0400 {
103 compatible = "snps,dw-apb-gpio";
104 reg = <0x0400 0x400>;
105 #address-cells = <1>;
106 #size-cells = <0>;
107
108 porta: gpio-port@0 {
109 compatible = "snps,dw-apb-gpio-port";
110 gpio-controller;
111 #gpio-cells = <2>;
112 snps,nr-gpios = <8>;
113 reg = <0>;
114 interrupt-controller;
115 #interrupt-cells = <2>;
116 interrupts = <0>;
117 };
118 };
119
120 gpio1: gpio@0800 {
121 compatible = "snps,dw-apb-gpio";
122 reg = <0x0800 0x400>;
123 #address-cells = <1>;
124 #size-cells = <0>;
125
126 portb: gpio-port@1 {
127 compatible = "snps,dw-apb-gpio-port";
128 gpio-controller;
129 #gpio-cells = <2>;
130 snps,nr-gpios = <8>;
131 reg = <0>;
132 interrupt-controller;
133 #interrupt-cells = <2>;
134 interrupts = <1>;
135 };
136 };
137
138 gpio2: gpio@0c00 {
139 compatible = "snps,dw-apb-gpio";
140 reg = <0x0c00 0x400>;
141 #address-cells = <1>;
142 #size-cells = <0>;
143
144 portc: gpio-port@2 {
145 compatible = "snps,dw-apb-gpio-port";
146 gpio-controller;
147 #gpio-cells = <2>;
148 snps,nr-gpios = <8>;
149 reg = <0>;
150 interrupt-controller;
151 #interrupt-cells = <2>;
152 interrupts = <2>;
153 };
154 };
155
156 gpio3: gpio@1000 {
157 compatible = "snps,dw-apb-gpio";
158 reg = <0x1000 0x400>;
159 #address-cells = <1>;
160 #size-cells = <0>;
161
162 portd: gpio-port@3 {
163 compatible = "snps,dw-apb-gpio-port";
164 gpio-controller;
165 #gpio-cells = <2>;
166 snps,nr-gpios = <8>;
167 reg = <0>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 interrupts = <3>;
171 };
172 };
173
2440946c
SH		 174 timer0: timer@2c00 {
175 compatible = "snps,dw-apb-timer";
176 reg = <0x2c00 0x14>;
177 interrupts = <8>;
178 clocks = <&cfgclk>;
179 clock-names = "timer";
180 status = "okay";
181 };
182
183 timer1: timer@2c14 {
184 compatible = "snps,dw-apb-timer";
185 reg = <0x2c14 0x14>;
186 interrupts = <9>;
187 clocks = <&cfgclk>;
188 clock-names = "timer";
189 status = "okay";
190 };
191
192 timer2: timer@2c28 {
193 compatible = "snps,dw-apb-timer";
194 reg = <0x2c28 0x14>;
195 interrupts = <10>;
196 clocks = <&cfgclk>;
197 clock-names = "timer";
198 status = "disabled";
199 };
200
201 timer3: timer@2c3c {
202 compatible = "snps,dw-apb-timer";
203 reg = <0x2c3c 0x14>;
204 interrupts = <11>;
205 clocks = <&cfgclk>;
206 clock-names = "timer";
207 status = "disabled";
208 };
209
210 timer4: timer@2c50 {
211 compatible = "snps,dw-apb-timer";
212 reg = <0x2c50 0x14>;
213 interrupts = <12>;
214 clocks = <&cfgclk>;
215 clock-names = "timer";
216 status = "disabled";
217 };
218
219 timer5: timer@2c64 {
220 compatible = "snps,dw-apb-timer";
221 reg = <0x2c64 0x14>;
222 interrupts = <13>;
223 clocks = <&cfgclk>;
224 clock-names = "timer";
225 status = "disabled";
226 };
227
228 timer6: timer@2c78 {
229 compatible = "snps,dw-apb-timer";
230 reg = <0x2c78 0x14>;
231 interrupts = <14>;
232 clocks = <&cfgclk>;
233 clock-names = "timer";
234 status = "disabled";
235 };
236
237 timer7: timer@2c8c {
238 compatible = "snps,dw-apb-timer";
239 reg = <0x2c8c 0x14>;
240 interrupts = <15>;
241 clocks = <&cfgclk>;
242 clock-names = "timer";
243 status = "disabled";
244 };
245
246 aic: interrupt-controller@3000 {
247 compatible = "snps,dw-apb-ictl";
248 reg = <0x3000 0xc00>;
249 interrupt-controller;
250 #interrupt-cells = <1>;
251 interrupt-parent = <&gic>;
252 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
253 };
254 };
255
0bd4b346
SH		 256 generic-regs@ea0184 {
257 compatible = "marvell,berlin-generic-regs", "syscon";
258 reg = <0xea0184 0x10>;
259 };
260
2440946c
SH		 261 apb@fc0000 {
262 compatible = "simple-bus";
263 #address-cells = <1>;
264 #size-cells = <1>;
265
266 ranges = <0 0xfc0000 0x10000>;
267 interrupt-parent = <&sic>;
268
6d3da018
AT		 269 sm_gpio1: gpio@5000 {
270 compatible = "snps,dw-apb-gpio";
271 reg = <0x5000 0x400>;
272 #address-cells = <1>;
273 #size-cells = <0>;
274
275 portf: gpio-port@5 {
276 compatible = "snps,dw-apb-gpio-port";
277 gpio-controller;
278 #gpio-cells = <2>;
279 snps,nr-gpios = <8>;
280 reg = <0>;
281 };
282 };
283
284 sm_gpio0: gpio@c000 {
285 compatible = "snps,dw-apb-gpio";
286 reg = <0xc000 0x400>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289
290 porte: gpio-port@4 {
291 compatible = "snps,dw-apb-gpio-port";
292 gpio-controller;
293 #gpio-cells = <2>;
294 snps,nr-gpios = <8>;
295 reg = <0>;
296 interrupt-controller;
297 #interrupt-cells = <2>;
298 interrupts = <11>;
299 };
300 };
301
2440946c
SH		 302 uart0: serial@9000 {
303 compatible = "snps,dw-apb-uart";
304 reg = <0x9000 0x100>;
305 reg-shift = <2>;
306 reg-io-width = <1>;
307 interrupts = <8>;
308 clocks = <&smclk>;
309 status = "disabled";
310 };
311
312 uart1: serial@a000 {
313 compatible = "snps,dw-apb-uart";
314 reg = <0xa000 0x100>;
315 reg-shift = <2>;
316 reg-io-width = <1>;
317 interrupts = <9>;
318 clocks = <&smclk>;
319 status = "disabled";
320 };
321
322 uart2: serial@b000 {
323 compatible = "snps,dw-apb-uart";
324 reg = <0xb000 0x100>;
325 reg-shift = <2>;
326 reg-io-width = <1>;
327 interrupts = <10>;
328 clocks = <&smclk>;
329 status = "disabled";
330 };
331
332 sic: interrupt-controller@e000 {
333 compatible = "snps,dw-apb-ictl";
334 reg = <0xe000 0x400>;
335 interrupt-controller;
336 #interrupt-cells = <1>;
337 interrupt-parent = <&gic>;
338 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
339 };
340 };
341 };
342};
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