[deliverable/linux.git] / arch / arm / boot / dts / berlin2.dtsi

/*
 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
 *
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 *
 * based on GPL'ed 2.6 kernel sources
 *  (c) Marvell International Ltd.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include "skeleton.dtsi"
#include <dt-bindings/clock/berlin2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell Armada 1500 (BG2) SoC";
	compatible = "marvell,berlin2", "marvell,berlin";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,berlin-smp";

		cpu@0 {
			compatible = "marvell,pj4b";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;
		};

		cpu@1 {
			compatible = "marvell,pj4b";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <1>;
		};
	};

	refclk: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&gic>;

		ranges = <0 0xf7000000 0x1000000>;

		sdhci0: sdhci@ab0000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0000 0x200>;
			clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
			clock-names = "io", "core";
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci1: sdhci@ab0800 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0800 0x200>;
			clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
			clock-names = "io", "core";
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci2: sdhci@ab1000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab1000 0x200>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
			clock-names = "io", "core";
			pinctrl-0 = <&emmc_pmux>;
			pinctrl-names = "default";
			status = "disabled";
		};

		l2: l2-cache-controller@ac0000 {
			compatible = "marvell,tauros3-cache", "arm,pl310-cache";
			reg = <0xac0000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};

		scu: snoop-control-unit@ad0000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xad0000 0x58>;
		};

		gic: interrupt-controller@ad1000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		local-timer@ad0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xad0600 0x20>;
			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip CLKID_TWD>;
		};

		eth1: ethernet@b90000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xb90000 0x10000>;
			clocks = <&chip CLKID_GETH1>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy1>;
			status = "disabled";

			ethphy1: ethernet-phy@0 {
				reg = <0>;
			};
		};

		cpu-ctrl@dd0000 {
			compatible = "marvell,berlin-cpu-ctrl";
			reg = <0xdd0000 0x10000>;
		};

		eth0: ethernet@e50000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xe50000 0x10000>;
			clocks = <&chip CLKID_GETH0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy0>;
			status = "disabled";

			ethphy0: ethernet-phy@0 {
				reg = <0>;
			};
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			gpio0: gpio@0400 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0400 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porta: gpio-port@0 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <0>;
				};
			};

			gpio1: gpio@0800 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0800 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portb: gpio-port@1 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <1>;
				};
			};

			gpio2: gpio@0c00 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0c00 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portc: gpio-port@2 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <2>;
				};
			};

			gpio3: gpio@1000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x1000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portd: gpio-port@3 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <3>;
				};
			};

			timer0: timer@2c00 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c00 0x14>;
				interrupts = <8>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer1: timer@2c14 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c14 0x14>;
				interrupts = <9>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer2: timer@2c28 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c28 0x14>;
				interrupts = <10>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer3: timer@2c3c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c3c 0x14>;
				interrupts = <11>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer4: timer@2c50 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c50 0x14>;
				interrupts = <12>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer5: timer@2c64 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c64 0x14>;
				interrupts = <13>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer6: timer@2c78 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c78 0x14>;
				interrupts = <14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer7: timer@2c8c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c8c 0x14>;
				interrupts = <15>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			aic: interrupt-controller@3000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3000 0xc00>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		chip: chip-control@ea0000 {
			compatible = "marvell,berlin2-chip-ctrl";
			#clock-cells = <1>;
			#reset-cells = <2>;
			reg = <0xea0000 0x400>;
			clocks = <&refclk>;
			clock-names = "refclk";

			emmc_pmux: emmc-pmux {
				groups = "G26";
				function = "emmc";
			};
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			sm_gpio1: gpio@5000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x5000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portf: gpio-port@5 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
				};
			};

			sm_gpio0: gpio@c000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0xc000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porte: gpio-port@4 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <11>;
				};
			};

			uart0: serial@9000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x9000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <8>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart1: serial@a000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xa000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <9>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart1_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart2: serial@b000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xb000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <10>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart2_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			sysctrl: system-controller@d000 {
				compatible = "marvell,berlin2-system-ctrl";
				reg = <0xd000 0x100>;

				uart0_pmux: uart0-pmux {
					groups = "GSM4";
					function = "uart0";
				};

				uart1_pmux: uart1-pmux {
					groups = "GSM5";
					function = "uart1";
				};

				uart2_pmux: uart2-pmux {
					groups = "GSM3";
					function = "uart2";
				};
			};

			sic: interrupt-controller@e000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0xe000 0x400>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};
Commit	Line	Data
2440946c SH	1	/*
	2	* Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
	3	*
	4	* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
	5	*
	6	* based on GPL'ed 2.6 kernel sources
	7	* (c) Marvell International Ltd.
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
	14	#include "skeleton.dtsi"
36601dbf	15	#include <dt-bindings/clock/berlin2.h>
2440946c SH	16	#include <dt-bindings/interrupt-controller/arm-gic.h>
	17
	18	/ {
	19	model = "Marvell Armada 1500 (BG2) SoC";
	20	compatible = "marvell,berlin2", "marvell,berlin";
	21
	22	cpus {
	23	#address-cells = <1>;
	24	#size-cells = <0>;
460d02ac	25	enable-method = "marvell,berlin-smp";
2440946c SH	26
	27	cpu@0 {
	28	compatible = "marvell,pj4b";
	29	device_type = "cpu";
	30	next-level-cache = <&l2>;
	31	reg = <0>;
	32	};
	33
	34	cpu@1 {
	35	compatible = "marvell,pj4b";
	36	device_type = "cpu";
	37	next-level-cache = <&l2>;
	38	reg = <1>;
	39	};
	40	};
	41
36601dbf SH	42	refclk: oscillator {
	43	compatible = "fixed-clock";
	44	#clock-cells = <0>;
	45	clock-frequency = <25000000>;
2440946c SH	46	};
	47
	48	soc {
	49	compatible = "simple-bus";
	50	#address-cells = <1>;
	51	#size-cells = <1>;
	52	interrupt-parent = <&gic>;
	53
	54	ranges = <0 0xf7000000 0x1000000>;
	55
652538c4 SH	56	sdhci0: sdhci@ab0000 {
	57	compatible = "mrvl,pxav3-mmc";
	58	reg = <0xab0000 0x200>;
	59	clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
	60	clock-names = "io", "core";
	61	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	62	status = "disabled";
	63	};
	64
	65	sdhci1: sdhci@ab0800 {
	66	compatible = "mrvl,pxav3-mmc";
	67	reg = <0xab0800 0x200>;
	68	clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
	69	clock-names = "io", "core";
	70	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	71	status = "disabled";
	72	};
	73
	74	sdhci2: sdhci@ab1000 {
	75	compatible = "mrvl,pxav3-mmc";
	76	reg = <0xab1000 0x200>;
	77	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	78	clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
	79	clock-names = "io", "core";
	80	pinctrl-0 = <&emmc_pmux>;
	81	pinctrl-names = "default";
	82	status = "disabled";
	83	};
	84
2440946c SH	85	l2: l2-cache-controller@ac0000 {
	86	compatible = "marvell,tauros3-cache", "arm,pl310-cache";
	87	reg = <0xac0000 0x1000>;
	88	cache-unified;
	89	cache-level = <2>;
	90	};
	91
0bd4b346 SH	92	scu: snoop-control-unit@ad0000 {
	93	compatible = "arm,cortex-a9-scu";
	94	reg = <0xad0000 0x58>;
	95	};
	96
2440946c SH	97	gic: interrupt-controller@ad1000 {
	98	compatible = "arm,cortex-a9-gic";
	99	reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
	100	interrupt-controller;
	101	#interrupt-cells = <3>;
	102	};
	103
	104	local-timer@ad0600 {
	105	compatible = "arm,cortex-a9-twd-timer";
	106	reg = <0xad0600 0x20>;
	107	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
36601dbf	108	clocks = <&chip CLKID_TWD>;
2440946c SH	109	};
2440946c SH	110
ae01f64b SH	111	eth1: ethernet@b90000 {
	112	compatible = "marvell,pxa168-eth";
	113	reg = <0xb90000 0x10000>;
	114	clocks = <&chip CLKID_GETH1>;
	115	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	116	/* set by bootloader */
	117	local-mac-address = [00 00 00 00 00 00];
	118	#address-cells = <1>;
	119	#size-cells = <0>;
	120	phy-connection-type = "mii";
	121	phy-handle = <&ethphy1>;
	122	status = "disabled";
	123
	124	ethphy1: ethernet-phy@0 {
	125	reg = <0>;
	126	};
	127	};
	128
460d02ac AT	129	cpu-ctrl@dd0000 {
	130	compatible = "marvell,berlin-cpu-ctrl";
	131	reg = <0xdd0000 0x10000>;
	132	};
	133
ae01f64b SH	134	eth0: ethernet@e50000 {
	135	compatible = "marvell,pxa168-eth";
	136	reg = <0xe50000 0x10000>;
	137	clocks = <&chip CLKID_GETH0>;
	138	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	139	/* set by bootloader */
	140	local-mac-address = [00 00 00 00 00 00];
	141	#address-cells = <1>;
	142	#size-cells = <0>;
	143	phy-connection-type = "mii";
	144	phy-handle = <&ethphy0>;
	145	status = "disabled";
	146
	147	ethphy0: ethernet-phy@0 {
	148	reg = <0>;
	149	};
	150	};
	151
2440946c SH	152	apb@e80000 {
	153	compatible = "simple-bus";
	154	#address-cells = <1>;
	155	#size-cells = <1>;
	156
	157	ranges = <0 0xe80000 0x10000>;
	158	interrupt-parent = <&aic>;
	159
6d3da018 AT	160	gpio0: gpio@0400 {
	161	compatible = "snps,dw-apb-gpio";
	162	reg = <0x0400 0x400>;
	163	#address-cells = <1>;
	164	#size-cells = <0>;
	165
	166	porta: gpio-port@0 {
	167	compatible = "snps,dw-apb-gpio-port";
	168	gpio-controller;
	169	#gpio-cells = <2>;
	170	snps,nr-gpios = <8>;
	171	reg = <0>;
	172	interrupt-controller;
	173	#interrupt-cells = <2>;
	174	interrupts = <0>;
	175	};
	176	};
	177
	178	gpio1: gpio@0800 {
	179	compatible = "snps,dw-apb-gpio";
	180	reg = <0x0800 0x400>;
	181	#address-cells = <1>;
	182	#size-cells = <0>;
	183
	184	portb: gpio-port@1 {
	185	compatible = "snps,dw-apb-gpio-port";
	186	gpio-controller;
	187	#gpio-cells = <2>;
	188	snps,nr-gpios = <8>;
	189	reg = <0>;
	190	interrupt-controller;
	191	#interrupt-cells = <2>;
	192	interrupts = <1>;
	193	};
	194	};
	195
	196	gpio2: gpio@0c00 {
	197	compatible = "snps,dw-apb-gpio";
	198	reg = <0x0c00 0x400>;
	199	#address-cells = <1>;
	200	#size-cells = <0>;
	201
	202	portc: gpio-port@2 {
	203	compatible = "snps,dw-apb-gpio-port";
	204	gpio-controller;
	205	#gpio-cells = <2>;
	206	snps,nr-gpios = <8>;
	207	reg = <0>;
	208	interrupt-controller;
	209	#interrupt-cells = <2>;
	210	interrupts = <2>;
	211	};
	212	};
	213
	214	gpio3: gpio@1000 {
	215	compatible = "snps,dw-apb-gpio";
	216	reg = <0x1000 0x400>;
	217	#address-cells = <1>;
	218	#size-cells = <0>;
	219
	220	portd: gpio-port@3 {
	221	compatible = "snps,dw-apb-gpio-port";
	222	gpio-controller;
	223	#gpio-cells = <2>;
224	snps,nr-gpios = <8>;
225	reg = <0>;
226	interrupt-controller;
227	#interrupt-cells = <2>;
228	interrupts = <3>;
229	};
230	};
231
2440946c SH	232	timer0: timer@2c00 {
	233	compatible = "snps,dw-apb-timer";
	234	reg = <0x2c00 0x14>;
	235	interrupts = <8>;
36601dbf	236	clocks = <&chip CLKID_CFG>;
2440946c SH	237	clock-names = "timer";
	238	status = "okay";
	239	};
	240
	241	timer1: timer@2c14 {
	242	compatible = "snps,dw-apb-timer";
	243	reg = <0x2c14 0x14>;
	244	interrupts = <9>;
36601dbf	245	clocks = <&chip CLKID_CFG>;
2440946c SH	246	clock-names = "timer";
	247	status = "okay";
	248	};
	249
	250	timer2: timer@2c28 {
	251	compatible = "snps,dw-apb-timer";
	252	reg = <0x2c28 0x14>;
	253	interrupts = <10>;
36601dbf	254	clocks = <&chip CLKID_CFG>;
2440946c SH	255	clock-names = "timer";
	256	status = "disabled";
	257	};
	258
	259	timer3: timer@2c3c {
	260	compatible = "snps,dw-apb-timer";
	261	reg = <0x2c3c 0x14>;
	262	interrupts = <11>;
36601dbf	263	clocks = <&chip CLKID_CFG>;
2440946c SH	264	clock-names = "timer";
	265	status = "disabled";
	266	};
	267
	268	timer4: timer@2c50 {
	269	compatible = "snps,dw-apb-timer";
	270	reg = <0x2c50 0x14>;
	271	interrupts = <12>;
36601dbf	272	clocks = <&chip CLKID_CFG>;
2440946c SH	273	clock-names = "timer";
	274	status = "disabled";
	275	};
	276
	277	timer5: timer@2c64 {
	278	compatible = "snps,dw-apb-timer";
	279	reg = <0x2c64 0x14>;
	280	interrupts = <13>;
36601dbf	281	clocks = <&chip CLKID_CFG>;
2440946c SH	282	clock-names = "timer";
	283	status = "disabled";
	284	};
	285
	286	timer6: timer@2c78 {
	287	compatible = "snps,dw-apb-timer";
	288	reg = <0x2c78 0x14>;
	289	interrupts = <14>;
36601dbf	290	clocks = <&chip CLKID_CFG>;
2440946c SH	291	clock-names = "timer";
	292	status = "disabled";
	293	};
	294
	295	timer7: timer@2c8c {
	296	compatible = "snps,dw-apb-timer";
	297	reg = <0x2c8c 0x14>;
	298	interrupts = <15>;
36601dbf	299	clocks = <&chip CLKID_CFG>;
2440946c SH	300	clock-names = "timer";
	301	status = "disabled";
	302	};
	303
	304	aic: interrupt-controller@3000 {
	305	compatible = "snps,dw-apb-ictl";
	306	reg = <0x3000 0xc00>;
	307	interrupt-controller;
	308	#interrupt-cells = <1>;
	309	interrupt-parent = <&gic>;
	310	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	311	};
	312	};
	313
36601dbf SH	314	chip: chip-control@ea0000 {
	315	compatible = "marvell,berlin2-chip-ctrl";
	316	#clock-cells = <1>;
1e27a261	317	#reset-cells = <2>;
36601dbf SH	318	reg = <0xea0000 0x400>;
	319	clocks = <&refclk>;
	320	clock-names = "refclk";
652538c4 SH	321
	322	emmc_pmux: emmc-pmux {
	323	groups = "G26";
	324	function = "emmc";
	325	};
0bd4b346 SH	326	};
0bd4b346 SH	327
2440946c SH	328	apb@fc0000 {
	329	compatible = "simple-bus";
	330	#address-cells = <1>;
	331	#size-cells = <1>;
	332
	333	ranges = <0 0xfc0000 0x10000>;
	334	interrupt-parent = <&sic>;
	335
6d3da018 AT	336	sm_gpio1: gpio@5000 {
	337	compatible = "snps,dw-apb-gpio";
	338	reg = <0x5000 0x400>;
	339	#address-cells = <1>;
	340	#size-cells = <0>;
	341
	342	portf: gpio-port@5 {
	343	compatible = "snps,dw-apb-gpio-port";
	344	gpio-controller;
	345	#gpio-cells = <2>;
	346	snps,nr-gpios = <8>;
	347	reg = <0>;
	348	};
	349	};
	350
	351	sm_gpio0: gpio@c000 {
	352	compatible = "snps,dw-apb-gpio";
	353	reg = <0xc000 0x400>;
	354	#address-cells = <1>;
	355	#size-cells = <0>;
	356
	357	porte: gpio-port@4 {
	358	compatible = "snps,dw-apb-gpio-port";
	359	gpio-controller;
	360	#gpio-cells = <2>;
	361	snps,nr-gpios = <8>;
	362	reg = <0>;
	363	interrupt-controller;
	364	#interrupt-cells = <2>;
	365	interrupts = <11>;
	366	};
	367	};
	368
2440946c SH	369	uart0: serial@9000 {
	370	compatible = "snps,dw-apb-uart";
	371	reg = <0x9000 0x100>;
	372	reg-shift = <2>;
	373	reg-io-width = <1>;
	374	interrupts = <8>;
36601dbf	375	clocks = <&refclk>;
50cc24ff AT	376	pinctrl-0 = <&uart0_pmux>;
50cc24ff AT	377	pinctrl-names = "default";
2440946c SH	378	status = "disabled";
	379	};
	380
	381	uart1: serial@a000 {
	382	compatible = "snps,dw-apb-uart";
	383	reg = <0xa000 0x100>;
	384	reg-shift = <2>;
	385	reg-io-width = <1>;
	386	interrupts = <9>;
36601dbf	387	clocks = <&refclk>;
50cc24ff AT	388	pinctrl-0 = <&uart1_pmux>;
50cc24ff AT	389	pinctrl-names = "default";
2440946c SH	390	status = "disabled";
	391	};
	392
	393	uart2: serial@b000 {
	394	compatible = "snps,dw-apb-uart";
	395	reg = <0xb000 0x100>;
	396	reg-shift = <2>;
	397	reg-io-width = <1>;
	398	interrupts = <10>;
36601dbf	399	clocks = <&refclk>;
50cc24ff AT	400	pinctrl-0 = <&uart2_pmux>;
50cc24ff AT	401	pinctrl-names = "default";
2440946c SH	402	status = "disabled";
	403	};
	404
50cc24ff AT	405	sysctrl: system-controller@d000 {
	406	compatible = "marvell,berlin2-system-ctrl";
	407	reg = <0xd000 0x100>;
	408
	409	uart0_pmux: uart0-pmux {
	410	groups = "GSM4";
	411	function = "uart0";
	412	};
	413
	414	uart1_pmux: uart1-pmux {
	415	groups = "GSM5";
	416	function = "uart1";
	417	};
	418
	419	uart2_pmux: uart2-pmux {
	420	groups = "GSM3";
	421	function = "uart2";
	422	};
	423	};
	424
2440946c SH	425	sic: interrupt-controller@e000 {
	426	compatible = "snps,dw-apb-ictl";
	427	reg = <0xe000 0x400>;
	428	interrupt-controller;
	429	#interrupt-cells = <1>;
	430	interrupt-parent = <&gic>;
	431	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	432	};
	433	};
	434	};
	435	};