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a9092118 SH |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC | |
3 | * | |
4 | * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | |
5 | * | |
6 | * based on GPL'ed 2.6 kernel sources | |
7 | * (c) Marvell International Ltd. | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include "skeleton.dtsi" | |
556f4a33 | 15 | #include <dt-bindings/clock/berlin2.h> |
a9092118 SH |
16 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
17 | ||
18 | / { | |
19 | model = "Marvell Armada 1500-mini (BG2CD) SoC"; | |
20 | compatible = "marvell,berlin2cd", "marvell,berlin"; | |
21 | ||
22 | cpus { | |
23 | #address-cells = <1>; | |
24 | #size-cells = <0>; | |
25 | ||
26 | cpu@0 { | |
27 | compatible = "arm,cortex-a9"; | |
28 | device_type = "cpu"; | |
29 | next-level-cache = <&l2>; | |
30 | reg = <0>; | |
31 | }; | |
32 | }; | |
33 | ||
556f4a33 SH |
34 | refclk: oscillator { |
35 | compatible = "fixed-clock"; | |
36 | #clock-cells = <0>; | |
37 | clock-frequency = <25000000>; | |
a9092118 SH |
38 | }; |
39 | ||
40 | soc { | |
41 | compatible = "simple-bus"; | |
42 | #address-cells = <1>; | |
43 | #size-cells = <1>; | |
44 | interrupt-parent = <&gic>; | |
45 | ||
46 | ranges = <0 0xf7000000 0x1000000>; | |
47 | ||
d4ce8042 JZ |
48 | pmu { |
49 | compatible = "arm,cortex-a9-pmu"; | |
50 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
51 | }; | |
52 | ||
652538c4 SH |
53 | sdhci0: sdhci@ab0000 { |
54 | compatible = "mrvl,pxav3-mmc"; | |
55 | reg = <0xab0000 0x200>; | |
b8b59d4c | 56 | clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; |
652538c4 SH |
57 | clock-names = "io", "core"; |
58 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
59 | status = "disabled"; | |
60 | }; | |
61 | ||
a9092118 SH |
62 | l2: l2-cache-controller@ac0000 { |
63 | compatible = "arm,pl310-cache"; | |
64 | reg = <0xac0000 0x1000>; | |
65 | cache-unified; | |
66 | cache-level = <2>; | |
67 | }; | |
68 | ||
69 | gic: interrupt-controller@ad1000 { | |
70 | compatible = "arm,cortex-a9-gic"; | |
71 | reg = <0xad1000 0x1000>, <0xad0100 0x0100>; | |
72 | interrupt-controller; | |
73 | #interrupt-cells = <3>; | |
74 | }; | |
75 | ||
76 | local-timer@ad0600 { | |
77 | compatible = "arm,cortex-a9-twd-timer"; | |
78 | reg = <0xad0600 0x20>; | |
2356d2f3 | 79 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; |
b8b59d4c | 80 | clocks = <&chip_clk CLKID_TWD>; |
a9092118 SH |
81 | }; |
82 | ||
e802b3a2 SH |
83 | usb_phy0: usb-phy@b74000 { |
84 | compatible = "marvell,berlin2cd-usb-phy"; | |
85 | reg = <0xb74000 0x128>; | |
86 | #phy-cells = <0>; | |
43225728 | 87 | resets = <&chip_rst 0x178 23>; |
e802b3a2 SH |
88 | status = "disabled"; |
89 | }; | |
90 | ||
91 | usb_phy1: usb-phy@b78000 { | |
92 | compatible = "marvell,berlin2cd-usb-phy"; | |
93 | reg = <0xb78000 0x128>; | |
94 | #phy-cells = <0>; | |
43225728 | 95 | resets = <&chip_rst 0x178 24>; |
e802b3a2 SH |
96 | status = "disabled"; |
97 | }; | |
98 | ||
631338af SH |
99 | eth1: ethernet@b90000 { |
100 | compatible = "marvell,pxa168-eth"; | |
101 | reg = <0xb90000 0x10000>; | |
b8b59d4c | 102 | clocks = <&chip_clk CLKID_GETH1>; |
631338af SH |
103 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
104 | /* set by bootloader */ | |
105 | local-mac-address = [00 00 00 00 00 00]; | |
106 | #address-cells = <1>; | |
107 | #size-cells = <0>; | |
108 | phy-connection-type = "mii"; | |
109 | phy-handle = <ðphy1>; | |
110 | status = "disabled"; | |
111 | ||
112 | ethphy1: ethernet-phy@0 { | |
113 | reg = <0>; | |
114 | }; | |
115 | }; | |
116 | ||
117 | eth0: ethernet@e50000 { | |
118 | compatible = "marvell,pxa168-eth"; | |
119 | reg = <0xe50000 0x10000>; | |
b8b59d4c | 120 | clocks = <&chip_clk CLKID_GETH0>; |
631338af SH |
121 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
122 | /* set by bootloader */ | |
123 | local-mac-address = [00 00 00 00 00 00]; | |
124 | #address-cells = <1>; | |
125 | #size-cells = <0>; | |
126 | phy-connection-type = "mii"; | |
127 | phy-handle = <ðphy0>; | |
128 | status = "disabled"; | |
129 | ||
130 | ethphy0: ethernet-phy@0 { | |
131 | reg = <0>; | |
132 | }; | |
133 | }; | |
134 | ||
a9092118 SH |
135 | apb@e80000 { |
136 | compatible = "simple-bus"; | |
137 | #address-cells = <1>; | |
138 | #size-cells = <1>; | |
139 | ||
140 | ranges = <0 0xe80000 0x10000>; | |
141 | interrupt-parent = <&aic>; | |
142 | ||
c920a669 AT |
143 | gpio0: gpio@0400 { |
144 | compatible = "snps,dw-apb-gpio"; | |
145 | reg = <0x0400 0x400>; | |
146 | #address-cells = <1>; | |
147 | #size-cells = <0>; | |
148 | ||
149 | porta: gpio-port@0 { | |
150 | compatible = "snps,dw-apb-gpio-port"; | |
151 | gpio-controller; | |
152 | #gpio-cells = <2>; | |
153 | snps,nr-gpios = <8>; | |
154 | reg = <0>; | |
155 | interrupt-controller; | |
156 | #interrupt-cells = <2>; | |
157 | interrupts = <0>; | |
158 | }; | |
159 | }; | |
160 | ||
161 | gpio1: gpio@0800 { | |
162 | compatible = "snps,dw-apb-gpio"; | |
163 | reg = <0x0800 0x400>; | |
164 | #address-cells = <1>; | |
165 | #size-cells = <0>; | |
166 | ||
167 | portb: gpio-port@1 { | |
168 | compatible = "snps,dw-apb-gpio-port"; | |
169 | gpio-controller; | |
170 | #gpio-cells = <2>; | |
171 | snps,nr-gpios = <8>; | |
172 | reg = <0>; | |
173 | interrupt-controller; | |
174 | #interrupt-cells = <2>; | |
175 | interrupts = <1>; | |
176 | }; | |
177 | }; | |
178 | ||
179 | gpio2: gpio@0c00 { | |
180 | compatible = "snps,dw-apb-gpio"; | |
181 | reg = <0x0c00 0x400>; | |
182 | #address-cells = <1>; | |
183 | #size-cells = <0>; | |
184 | ||
185 | portc: gpio-port@2 { | |
186 | compatible = "snps,dw-apb-gpio-port"; | |
187 | gpio-controller; | |
188 | #gpio-cells = <2>; | |
189 | snps,nr-gpios = <8>; | |
190 | reg = <0>; | |
191 | interrupt-controller; | |
192 | #interrupt-cells = <2>; | |
193 | interrupts = <2>; | |
194 | }; | |
195 | }; | |
196 | ||
197 | gpio3: gpio@1000 { | |
198 | compatible = "snps,dw-apb-gpio"; | |
199 | reg = <0x1000 0x400>; | |
200 | #address-cells = <1>; | |
201 | #size-cells = <0>; | |
202 | ||
203 | portd: gpio-port@3 { | |
204 | compatible = "snps,dw-apb-gpio-port"; | |
205 | gpio-controller; | |
206 | #gpio-cells = <2>; | |
207 | snps,nr-gpios = <8>; | |
208 | reg = <0>; | |
209 | interrupt-controller; | |
210 | #interrupt-cells = <2>; | |
211 | interrupts = <3>; | |
212 | }; | |
213 | }; | |
214 | ||
a9092118 SH |
215 | timer0: timer@2c00 { |
216 | compatible = "snps,dw-apb-timer"; | |
217 | reg = <0x2c00 0x14>; | |
218 | interrupts = <8>; | |
b8b59d4c | 219 | clocks = <&chip_clk CLKID_CFG>; |
a9092118 SH |
220 | clock-names = "timer"; |
221 | status = "okay"; | |
222 | }; | |
223 | ||
224 | timer1: timer@2c14 { | |
225 | compatible = "snps,dw-apb-timer"; | |
226 | reg = <0x2c14 0x14>; | |
227 | interrupts = <9>; | |
b8b59d4c | 228 | clocks = <&chip_clk CLKID_CFG>; |
a9092118 SH |
229 | clock-names = "timer"; |
230 | status = "okay"; | |
231 | }; | |
232 | ||
233 | timer2: timer@2c28 { | |
234 | compatible = "snps,dw-apb-timer"; | |
235 | reg = <0x2c28 0x14>; | |
236 | interrupts = <10>; | |
b8b59d4c | 237 | clocks = <&chip_clk CLKID_CFG>; |
a9092118 SH |
238 | clock-names = "timer"; |
239 | status = "disabled"; | |
240 | }; | |
241 | ||
242 | timer3: timer@2c3c { | |
243 | compatible = "snps,dw-apb-timer"; | |
244 | reg = <0x2c3c 0x14>; | |
245 | interrupts = <11>; | |
b8b59d4c | 246 | clocks = <&chip_clk CLKID_CFG>; |
a9092118 SH |
247 | clock-names = "timer"; |
248 | status = "disabled"; | |
249 | }; | |
250 | ||
251 | timer4: timer@2c50 { | |
252 | compatible = "snps,dw-apb-timer"; | |
253 | reg = <0x2c50 0x14>; | |
254 | interrupts = <12>; | |
b8b59d4c | 255 | clocks = <&chip_clk CLKID_CFG>; |
a9092118 SH |
256 | clock-names = "timer"; |
257 | status = "disabled"; | |
258 | }; | |
259 | ||
260 | timer5: timer@2c64 { | |
261 | compatible = "snps,dw-apb-timer"; | |
262 | reg = <0x2c64 0x14>; | |
263 | interrupts = <13>; | |
b8b59d4c | 264 | clocks = <&chip_clk CLKID_CFG>; |
a9092118 SH |
265 | clock-names = "timer"; |
266 | status = "disabled"; | |
267 | }; | |
268 | ||
269 | timer6: timer@2c78 { | |
270 | compatible = "snps,dw-apb-timer"; | |
271 | reg = <0x2c78 0x14>; | |
272 | interrupts = <14>; | |
b8b59d4c | 273 | clocks = <&chip_clk CLKID_CFG>; |
a9092118 SH |
274 | clock-names = "timer"; |
275 | status = "disabled"; | |
276 | }; | |
277 | ||
278 | timer7: timer@2c8c { | |
279 | compatible = "snps,dw-apb-timer"; | |
280 | reg = <0x2c8c 0x14>; | |
281 | interrupts = <15>; | |
b8b59d4c | 282 | clocks = <&chip_clk CLKID_CFG>; |
a9092118 SH |
283 | clock-names = "timer"; |
284 | status = "disabled"; | |
285 | }; | |
286 | ||
287 | aic: interrupt-controller@3000 { | |
288 | compatible = "snps,dw-apb-ictl"; | |
289 | reg = <0x3000 0xc00>; | |
290 | interrupt-controller; | |
291 | #interrupt-cells = <1>; | |
292 | interrupt-parent = <&gic>; | |
293 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
294 | }; | |
295 | }; | |
296 | ||
556f4a33 | 297 | chip: chip-control@ea0000 { |
ffcc33a5 | 298 | compatible = "marvell,berlin2cd-chip-ctrl", "simple-mfd", "syscon"; |
556f4a33 | 299 | reg = <0xea0000 0x400>; |
b8b59d4c AT |
300 | |
301 | chip_clk: clock { | |
302 | compatible = "marvell,berlin2-clk"; | |
303 | #clock-cells = <1>; | |
304 | clocks = <&refclk>; | |
305 | clock-names = "refclk"; | |
306 | }; | |
50cc24ff | 307 | |
630c986b AT |
308 | soc_pinctrl: pin-controller { |
309 | compatible = "marvell,berlin2cd-soc-pinctrl"; | |
310 | ||
311 | uart0_pmux: uart0-pmux { | |
312 | groups = "G6"; | |
313 | function = "uart0"; | |
314 | }; | |
50cc24ff | 315 | }; |
43225728 AT |
316 | |
317 | chip_rst: reset { | |
318 | compatible = "marvell,berlin2-reset"; | |
319 | #reset-cells = <2>; | |
320 | }; | |
556f4a33 SH |
321 | }; |
322 | ||
e802b3a2 SH |
323 | usb0: usb@ed0000 { |
324 | compatible = "chipidea,usb2"; | |
325 | reg = <0xed0000 0x200>; | |
326 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
b8b59d4c | 327 | clocks = <&chip_clk CLKID_USB0>; |
e802b3a2 SH |
328 | phys = <&usb_phy0>; |
329 | phy-names = "usb-phy"; | |
330 | status = "disabled"; | |
331 | }; | |
332 | ||
333 | usb1: usb@ee0000 { | |
334 | compatible = "chipidea,usb2"; | |
335 | reg = <0xee0000 0x200>; | |
336 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
b8b59d4c | 337 | clocks = <&chip_clk CLKID_USB1>; |
e802b3a2 SH |
338 | phys = <&usb_phy1>; |
339 | phy-names = "usb-phy"; | |
340 | status = "disabled"; | |
341 | }; | |
342 | ||
a9092118 SH |
343 | apb@fc0000 { |
344 | compatible = "simple-bus"; | |
345 | #address-cells = <1>; | |
346 | #size-cells = <1>; | |
347 | ||
348 | ranges = <0 0xfc0000 0x10000>; | |
349 | interrupt-parent = <&sic>; | |
350 | ||
c920a669 AT |
351 | sm_gpio1: gpio@5000 { |
352 | compatible = "snps,dw-apb-gpio"; | |
353 | reg = <0x5000 0x400>; | |
354 | #address-cells = <1>; | |
355 | #size-cells = <0>; | |
356 | ||
357 | portf: gpio-port@5 { | |
358 | compatible = "snps,dw-apb-gpio-port"; | |
359 | gpio-controller; | |
360 | #gpio-cells = <2>; | |
361 | snps,nr-gpios = <8>; | |
362 | reg = <0>; | |
363 | }; | |
364 | }; | |
365 | ||
366 | sm_gpio0: gpio@c000 { | |
367 | compatible = "snps,dw-apb-gpio"; | |
368 | reg = <0xc000 0x400>; | |
369 | #address-cells = <1>; | |
370 | #size-cells = <0>; | |
371 | ||
372 | porte: gpio-port@4 { | |
373 | compatible = "snps,dw-apb-gpio-port"; | |
374 | gpio-controller; | |
375 | #gpio-cells = <2>; | |
376 | snps,nr-gpios = <8>; | |
377 | reg = <0>; | |
378 | }; | |
379 | }; | |
380 | ||
a9092118 SH |
381 | uart0: serial@9000 { |
382 | compatible = "snps,dw-apb-uart"; | |
383 | reg = <0x9000 0x100>; | |
384 | reg-shift = <2>; | |
385 | reg-io-width = <1>; | |
386 | interrupts = <8>; | |
556f4a33 | 387 | clocks = <&refclk>; |
50cc24ff AT |
388 | pinctrl-0 = <&uart0_pmux>; |
389 | pinctrl-names = "default"; | |
a9092118 SH |
390 | status = "disabled"; |
391 | }; | |
392 | ||
393 | uart1: serial@a000 { | |
394 | compatible = "snps,dw-apb-uart"; | |
395 | reg = <0xa000 0x100>; | |
396 | reg-shift = <2>; | |
397 | reg-io-width = <1>; | |
398 | interrupts = <9>; | |
556f4a33 | 399 | clocks = <&refclk>; |
a9092118 SH |
400 | status = "disabled"; |
401 | }; | |
402 | ||
50cc24ff | 403 | sysctrl: system-controller@d000 { |
ffcc33a5 | 404 | compatible = "marvell,berlin2cd-system-ctrl", "simple-mfd", "syscon"; |
50cc24ff | 405 | reg = <0xd000 0x100>; |
630c986b AT |
406 | |
407 | sys_pinctrl: pin-controller { | |
408 | compatible = "marvell,berlin2cd-system-pinctrl"; | |
409 | }; | |
50cc24ff AT |
410 | }; |
411 | ||
a9092118 SH |
412 | sic: interrupt-controller@e000 { |
413 | compatible = "snps,dw-apb-ictl"; | |
414 | reg = <0xe000 0x400>; | |
415 | interrupt-controller; | |
416 | #interrupt-cells = <1>; | |
417 | interrupt-parent = <&gic>; | |
418 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
419 | }; | |
420 | }; | |
421 | }; | |
422 | }; |