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374ddcbf AT |
1 | /* |
2 | * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> | |
3 | * | |
4 | * This file is licensed under the terms of the GNU General Public | |
5 | * License version 2. This program is licensed "as is" without any | |
6 | * warranty of any kind, whether express or implied. | |
7 | */ | |
8 | ||
414dcf8f | 9 | #include <dt-bindings/clock/berlin2q.h> |
374ddcbf AT |
10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
11 | ||
12 | #include "skeleton.dtsi" | |
13 | ||
14 | / { | |
15 | model = "Marvell Armada 1500 pro (BG2-Q) SoC"; | |
16 | compatible = "marvell,berlin2q", "marvell,berlin"; | |
17 | ||
18 | cpus { | |
19 | #address-cells = <1>; | |
20 | #size-cells = <0>; | |
d19c9367 | 21 | enable-method = "marvell,berlin-smp"; |
374ddcbf AT |
22 | |
23 | cpu@0 { | |
24 | compatible = "arm,cortex-a9"; | |
25 | device_type = "cpu"; | |
26 | next-level-cache = <&l2>; | |
27 | reg = <0>; | |
28 | }; | |
29 | ||
30 | cpu@1 { | |
31 | compatible = "arm,cortex-a9"; | |
32 | device_type = "cpu"; | |
33 | next-level-cache = <&l2>; | |
34 | reg = <1>; | |
35 | }; | |
36 | ||
37 | cpu@2 { | |
38 | compatible = "arm,cortex-a9"; | |
39 | device_type = "cpu"; | |
40 | next-level-cache = <&l2>; | |
41 | reg = <2>; | |
42 | }; | |
43 | ||
44 | cpu@3 { | |
45 | compatible = "arm,cortex-a9"; | |
46 | device_type = "cpu"; | |
47 | next-level-cache = <&l2>; | |
48 | reg = <3>; | |
49 | }; | |
50 | }; | |
51 | ||
414dcf8f | 52 | refclk: oscillator { |
374ddcbf AT |
53 | compatible = "fixed-clock"; |
54 | #clock-cells = <0>; | |
55 | clock-frequency = <25000000>; | |
56 | }; | |
57 | ||
374ddcbf AT |
58 | soc { |
59 | compatible = "simple-bus"; | |
60 | #address-cells = <1>; | |
61 | #size-cells = <1>; | |
62 | ||
63 | ranges = <0 0xf7000000 0x1000000>; | |
64 | interrupt-parent = <&gic>; | |
65 | ||
0d859a6a AT |
66 | sdhci0: sdhci@ab0000 { |
67 | compatible = "mrvl,pxav3-mmc"; | |
68 | reg = <0xab0000 0x200>; | |
69 | clocks = <&chip CLKID_SDIO1XIN>; | |
70 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
71 | status = "disabled"; | |
72 | }; | |
73 | ||
74 | sdhci1: sdhci@ab0800 { | |
75 | compatible = "mrvl,pxav3-mmc"; | |
76 | reg = <0xab0800 0x200>; | |
77 | clocks = <&chip CLKID_SDIO1XIN>; | |
78 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
79 | status = "disabled"; | |
80 | }; | |
81 | ||
82 | sdhci2: sdhci@ab1000 { | |
83 | compatible = "mrvl,pxav3-mmc"; | |
84 | reg = <0xab1000 0x200>; | |
85 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
96ed6046 JZ |
86 | clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>; |
87 | clock-names = "io", "core"; | |
0d859a6a AT |
88 | status = "disabled"; |
89 | }; | |
90 | ||
374ddcbf AT |
91 | l2: l2-cache-controller@ac0000 { |
92 | compatible = "arm,pl310-cache"; | |
93 | reg = <0xac0000 0x1000>; | |
94 | cache-level = <2>; | |
44991eb4 JZ |
95 | arm,data-latency = <2 2 2>; |
96 | arm,tag-latency = <2 2 2>; | |
374ddcbf AT |
97 | }; |
98 | ||
0bd4b346 SH |
99 | scu: snoop-control-unit@ad0000 { |
100 | compatible = "arm,cortex-a9-scu"; | |
101 | reg = <0xad0000 0x58>; | |
102 | }; | |
103 | ||
374ddcbf AT |
104 | local-timer@ad0600 { |
105 | compatible = "arm,cortex-a9-twd-timer"; | |
106 | reg = <0xad0600 0x20>; | |
414dcf8f | 107 | clocks = <&chip CLKID_TWD>; |
374ddcbf AT |
108 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; |
109 | }; | |
110 | ||
111 | gic: interrupt-controller@ad1000 { | |
112 | compatible = "arm,cortex-a9-gic"; | |
113 | reg = <0xad1000 0x1000>, <0xad0100 0x100>; | |
114 | interrupt-controller; | |
115 | #interrupt-cells = <3>; | |
116 | }; | |
117 | ||
c539711e AT |
118 | usb_phy2: phy@a2f400 { |
119 | compatible = "marvell,berlin2-usb-phy"; | |
120 | reg = <0xa2f400 0x128>; | |
121 | #phy-cells = <0>; | |
122 | resets = <&chip 0x104 14>; | |
123 | status = "disabled"; | |
124 | }; | |
125 | ||
126 | usb2: usb@a30000 { | |
127 | compatible = "chipidea,usb2"; | |
128 | reg = <0xa30000 0x10000>; | |
129 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
130 | clocks = <&chip CLKID_USB2>; | |
131 | phys = <&usb_phy2>; | |
132 | phy-names = "usb-phy"; | |
133 | status = "disabled"; | |
134 | }; | |
135 | ||
136 | usb_phy0: phy@b74000 { | |
137 | compatible = "marvell,berlin2-usb-phy"; | |
138 | reg = <0xb74000 0x128>; | |
139 | #phy-cells = <0>; | |
140 | resets = <&chip 0x104 12>; | |
141 | status = "disabled"; | |
142 | }; | |
143 | ||
144 | usb_phy1: phy@b78000 { | |
145 | compatible = "marvell,berlin2-usb-phy"; | |
146 | reg = <0xb78000 0x128>; | |
147 | #phy-cells = <0>; | |
148 | resets = <&chip 0x104 13>; | |
149 | status = "disabled"; | |
150 | }; | |
151 | ||
bdc06cd7 AT |
152 | eth0: ethernet@b90000 { |
153 | compatible = "marvell,pxa168-eth"; | |
154 | reg = <0xb90000 0x10000>; | |
155 | clocks = <&chip CLKID_GETH0>; | |
156 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
157 | /* set by bootloader */ | |
158 | local-mac-address = [00 00 00 00 00 00]; | |
159 | #address-cells = <1>; | |
160 | #size-cells = <0>; | |
f5799dcf | 161 | phy-connection-type = "mii"; |
bdc06cd7 AT |
162 | phy-handle = <ðphy0>; |
163 | status = "disabled"; | |
164 | ||
165 | ethphy0: ethernet-phy@0 { | |
166 | reg = <0>; | |
167 | }; | |
168 | }; | |
169 | ||
d19c9367 AT |
170 | cpu-ctrl@dd0000 { |
171 | compatible = "marvell,berlin-cpu-ctrl"; | |
172 | reg = <0xdd0000 0x10000>; | |
173 | }; | |
174 | ||
374ddcbf AT |
175 | apb@e80000 { |
176 | compatible = "simple-bus"; | |
177 | #address-cells = <1>; | |
178 | #size-cells = <1>; | |
179 | ||
180 | ranges = <0 0xe80000 0x10000>; | |
181 | interrupt-parent = <&aic>; | |
182 | ||
cedf57fc AT |
183 | gpio0: gpio@0400 { |
184 | compatible = "snps,dw-apb-gpio"; | |
185 | reg = <0x0400 0x400>; | |
186 | #address-cells = <1>; | |
187 | #size-cells = <0>; | |
188 | ||
189 | porta: gpio-port@0 { | |
190 | compatible = "snps,dw-apb-gpio-port"; | |
191 | gpio-controller; | |
192 | #gpio-cells = <2>; | |
193 | snps,nr-gpios = <32>; | |
194 | reg = <0>; | |
195 | interrupt-controller; | |
196 | #interrupt-cells = <2>; | |
197 | interrupts = <0>; | |
198 | }; | |
199 | }; | |
200 | ||
201 | gpio1: gpio@0800 { | |
202 | compatible = "snps,dw-apb-gpio"; | |
203 | reg = <0x0800 0x400>; | |
204 | #address-cells = <1>; | |
205 | #size-cells = <0>; | |
206 | ||
207 | portb: gpio-port@1 { | |
208 | compatible = "snps,dw-apb-gpio-port"; | |
209 | gpio-controller; | |
210 | #gpio-cells = <2>; | |
211 | snps,nr-gpios = <32>; | |
212 | reg = <0>; | |
213 | interrupt-controller; | |
214 | #interrupt-cells = <2>; | |
215 | interrupts = <1>; | |
216 | }; | |
217 | }; | |
218 | ||
219 | gpio2: gpio@0c00 { | |
220 | compatible = "snps,dw-apb-gpio"; | |
221 | reg = <0x0c00 0x400>; | |
222 | #address-cells = <1>; | |
223 | #size-cells = <0>; | |
224 | ||
225 | portc: gpio-port@2 { | |
226 | compatible = "snps,dw-apb-gpio-port"; | |
227 | gpio-controller; | |
228 | #gpio-cells = <2>; | |
229 | snps,nr-gpios = <32>; | |
230 | reg = <0>; | |
231 | interrupt-controller; | |
232 | #interrupt-cells = <2>; | |
233 | interrupts = <2>; | |
234 | }; | |
235 | }; | |
236 | ||
237 | gpio3: gpio@1000 { | |
238 | compatible = "snps,dw-apb-gpio"; | |
239 | reg = <0x1000 0x400>; | |
240 | #address-cells = <1>; | |
241 | #size-cells = <0>; | |
242 | ||
243 | portd: gpio-port@3 { | |
244 | compatible = "snps,dw-apb-gpio-port"; | |
245 | gpio-controller; | |
246 | #gpio-cells = <2>; | |
247 | snps,nr-gpios = <32>; | |
248 | reg = <0>; | |
249 | interrupt-controller; | |
250 | #interrupt-cells = <2>; | |
251 | interrupts = <3>; | |
252 | }; | |
253 | }; | |
254 | ||
99f3deb8 AT |
255 | i2c0: i2c@1400 { |
256 | compatible = "snps,designware-i2c"; | |
257 | #address-cells = <1>; | |
258 | #size-cells = <0>; | |
259 | reg = <0x1400 0x100>; | |
260 | interrupt-parent = <&aic>; | |
261 | interrupts = <4>; | |
262 | clocks = <&chip CLKID_CFG>; | |
263 | pinctrl-0 = <&twsi0_pmux>; | |
264 | pinctrl-names = "default"; | |
265 | status = "disabled"; | |
266 | }; | |
267 | ||
268 | i2c1: i2c@1800 { | |
269 | compatible = "snps,designware-i2c"; | |
270 | #address-cells = <1>; | |
271 | #size-cells = <0>; | |
272 | reg = <0x1800 0x100>; | |
273 | interrupt-parent = <&aic>; | |
274 | interrupts = <5>; | |
275 | clocks = <&chip CLKID_CFG>; | |
276 | pinctrl-0 = <&twsi1_pmux>; | |
277 | pinctrl-names = "default"; | |
278 | status = "disabled"; | |
279 | }; | |
280 | ||
374ddcbf AT |
281 | timer0: timer@2c00 { |
282 | compatible = "snps,dw-apb-timer"; | |
283 | reg = <0x2c00 0x14>; | |
414dcf8f | 284 | clocks = <&chip CLKID_CFG>; |
374ddcbf AT |
285 | clock-names = "timer"; |
286 | interrupts = <8>; | |
287 | }; | |
288 | ||
289 | timer1: timer@2c14 { | |
290 | compatible = "snps,dw-apb-timer"; | |
291 | reg = <0x2c14 0x14>; | |
414dcf8f | 292 | clocks = <&chip CLKID_CFG>; |
374ddcbf | 293 | clock-names = "timer"; |
374ddcbf AT |
294 | }; |
295 | ||
296 | timer2: timer@2c28 { | |
297 | compatible = "snps,dw-apb-timer"; | |
298 | reg = <0x2c28 0x14>; | |
414dcf8f | 299 | clocks = <&chip CLKID_CFG>; |
374ddcbf AT |
300 | clock-names = "timer"; |
301 | status = "disabled"; | |
302 | }; | |
303 | ||
304 | timer3: timer@2c3c { | |
305 | compatible = "snps,dw-apb-timer"; | |
306 | reg = <0x2c3c 0x14>; | |
414dcf8f | 307 | clocks = <&chip CLKID_CFG>; |
374ddcbf AT |
308 | clock-names = "timer"; |
309 | status = "disabled"; | |
310 | }; | |
311 | ||
312 | timer4: timer@2c50 { | |
313 | compatible = "snps,dw-apb-timer"; | |
314 | reg = <0x2c50 0x14>; | |
414dcf8f | 315 | clocks = <&chip CLKID_CFG>; |
374ddcbf AT |
316 | clock-names = "timer"; |
317 | status = "disabled"; | |
318 | }; | |
319 | ||
320 | timer5: timer@2c64 { | |
321 | compatible = "snps,dw-apb-timer"; | |
322 | reg = <0x2c64 0x14>; | |
414dcf8f | 323 | clocks = <&chip CLKID_CFG>; |
374ddcbf AT |
324 | clock-names = "timer"; |
325 | status = "disabled"; | |
326 | }; | |
327 | ||
328 | timer6: timer@2c78 { | |
329 | compatible = "snps,dw-apb-timer"; | |
330 | reg = <0x2c78 0x14>; | |
414dcf8f | 331 | clocks = <&chip CLKID_CFG>; |
374ddcbf AT |
332 | clock-names = "timer"; |
333 | status = "disabled"; | |
334 | }; | |
335 | ||
336 | timer7: timer@2c8c { | |
337 | compatible = "snps,dw-apb-timer"; | |
338 | reg = <0x2c8c 0x14>; | |
414dcf8f | 339 | clocks = <&chip CLKID_CFG>; |
374ddcbf AT |
340 | clock-names = "timer"; |
341 | status = "disabled"; | |
342 | }; | |
343 | ||
344 | aic: interrupt-controller@3800 { | |
345 | compatible = "snps,dw-apb-ictl"; | |
346 | reg = <0x3800 0x30>; | |
347 | interrupt-controller; | |
348 | #interrupt-cells = <1>; | |
349 | interrupt-parent = <&gic>; | |
350 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
351 | }; | |
cedf57fc AT |
352 | |
353 | gpio4: gpio@5000 { | |
354 | compatible = "snps,dw-apb-gpio"; | |
355 | reg = <0x5000 0x400>; | |
356 | #address-cells = <1>; | |
357 | #size-cells = <0>; | |
358 | ||
359 | porte: gpio-port@4 { | |
360 | compatible = "snps,dw-apb-gpio-port"; | |
361 | gpio-controller; | |
362 | #gpio-cells = <2>; | |
363 | snps,nr-gpios = <32>; | |
364 | reg = <0>; | |
365 | }; | |
366 | }; | |
367 | ||
368 | gpio5: gpio@c000 { | |
369 | compatible = "snps,dw-apb-gpio"; | |
370 | reg = <0xc000 0x400>; | |
371 | #address-cells = <1>; | |
372 | #size-cells = <0>; | |
373 | ||
374 | portf: gpio-port@5 { | |
375 | compatible = "snps,dw-apb-gpio-port"; | |
376 | gpio-controller; | |
377 | #gpio-cells = <2>; | |
378 | snps,nr-gpios = <32>; | |
379 | reg = <0>; | |
380 | }; | |
381 | }; | |
374ddcbf AT |
382 | }; |
383 | ||
414dcf8f AB |
384 | chip: chip-control@ea0000 { |
385 | compatible = "marvell,berlin2q-chip-ctrl"; | |
386 | #clock-cells = <1>; | |
1e27a261 | 387 | #reset-cells = <2>; |
414dcf8f AB |
388 | reg = <0xea0000 0x400>, <0xdd0170 0x10>; |
389 | clocks = <&refclk>; | |
390 | clock-names = "refclk"; | |
99f3deb8 AT |
391 | |
392 | twsi0_pmux: twsi0-pmux { | |
393 | groups = "G6"; | |
394 | function = "twsi0"; | |
395 | }; | |
396 | ||
397 | twsi1_pmux: twsi1-pmux { | |
398 | groups = "G7"; | |
399 | function = "twsi1"; | |
400 | }; | |
0bd4b346 SH |
401 | }; |
402 | ||
70a2b717 AT |
403 | ahci: sata@e90000 { |
404 | compatible = "marvell,berlin2q-ahci", "generic-ahci"; | |
405 | reg = <0xe90000 0x1000>; | |
406 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
407 | clocks = <&chip CLKID_SATA>; | |
408 | #address-cells = <1>; | |
409 | #size-cells = <0>; | |
410 | ||
411 | sata0: sata-port@0 { | |
412 | reg = <0>; | |
413 | phys = <&sata_phy 0>; | |
414 | status = "disabled"; | |
415 | }; | |
416 | ||
417 | sata1: sata-port@1 { | |
418 | reg = <1>; | |
419 | phys = <&sata_phy 1>; | |
420 | status = "disabled"; | |
421 | }; | |
422 | }; | |
423 | ||
424 | sata_phy: phy@e900a0 { | |
425 | compatible = "marvell,berlin2q-sata-phy"; | |
426 | reg = <0xe900a0 0x200>; | |
427 | clocks = <&chip CLKID_SATA>; | |
428 | #address-cells = <1>; | |
429 | #size-cells = <0>; | |
430 | #phy-cells = <1>; | |
431 | status = "disabled"; | |
432 | ||
433 | sata-phy@0 { | |
434 | reg = <0>; | |
435 | }; | |
436 | ||
437 | sata-phy@1 { | |
438 | reg = <1>; | |
439 | }; | |
440 | }; | |
441 | ||
c539711e AT |
442 | usb0: usb@ed0000 { |
443 | compatible = "chipidea,usb2"; | |
444 | reg = <0xed0000 0x10000>; | |
445 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
446 | clocks = <&chip CLKID_USB0>; | |
447 | phys = <&usb_phy0>; | |
448 | phy-names = "usb-phy"; | |
449 | status = "disabled"; | |
450 | }; | |
451 | ||
452 | usb1: usb@ee0000 { | |
453 | compatible = "chipidea,usb2"; | |
454 | reg = <0xee0000 0x10000>; | |
455 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
456 | clocks = <&chip CLKID_USB1>; | |
457 | phys = <&usb_phy1>; | |
458 | phy-names = "usb-phy"; | |
459 | status = "disabled"; | |
460 | }; | |
461 | ||
374ddcbf AT |
462 | apb@fc0000 { |
463 | compatible = "simple-bus"; | |
464 | #address-cells = <1>; | |
465 | #size-cells = <1>; | |
466 | ||
467 | ranges = <0 0xfc0000 0x10000>; | |
468 | interrupt-parent = <&sic>; | |
469 | ||
99f3deb8 AT |
470 | i2c2: i2c@7000 { |
471 | compatible = "snps,designware-i2c"; | |
472 | #address-cells = <1>; | |
473 | #size-cells = <0>; | |
474 | reg = <0x7000 0x100>; | |
475 | interrupt-parent = <&sic>; | |
476 | interrupts = <6>; | |
477 | clocks = <&refclk>; | |
478 | pinctrl-0 = <&twsi2_pmux>; | |
479 | pinctrl-names = "default"; | |
480 | status = "disabled"; | |
481 | }; | |
482 | ||
483 | i2c3: i2c@8000 { | |
484 | compatible = "snps,designware-i2c"; | |
485 | #address-cells = <1>; | |
486 | #size-cells = <0>; | |
487 | reg = <0x8000 0x100>; | |
488 | interrupt-parent = <&sic>; | |
489 | interrupts = <7>; | |
490 | clocks = <&refclk>; | |
491 | pinctrl-0 = <&twsi3_pmux>; | |
492 | pinctrl-names = "default"; | |
493 | status = "disabled"; | |
494 | }; | |
495 | ||
374ddcbf AT |
496 | uart0: uart@9000 { |
497 | compatible = "snps,dw-apb-uart"; | |
498 | reg = <0x9000 0x100>; | |
499 | interrupt-parent = <&sic>; | |
500 | interrupts = <8>; | |
414dcf8f | 501 | clocks = <&refclk>; |
374ddcbf | 502 | reg-shift = <2>; |
50cc24ff AT |
503 | pinctrl-0 = <&uart0_pmux>; |
504 | pinctrl-names = "default"; | |
374ddcbf AT |
505 | status = "disabled"; |
506 | }; | |
507 | ||
508 | uart1: uart@a000 { | |
509 | compatible = "snps,dw-apb-uart"; | |
510 | reg = <0xa000 0x100>; | |
511 | interrupt-parent = <&sic>; | |
512 | interrupts = <9>; | |
414dcf8f | 513 | clocks = <&refclk>; |
374ddcbf | 514 | reg-shift = <2>; |
50cc24ff AT |
515 | pinctrl-0 = <&uart1_pmux>; |
516 | pinctrl-names = "default"; | |
374ddcbf AT |
517 | status = "disabled"; |
518 | }; | |
519 | ||
50cc24ff AT |
520 | sysctrl: pin-controller@d000 { |
521 | compatible = "marvell,berlin2q-system-ctrl"; | |
522 | reg = <0xd000 0x100>; | |
523 | ||
524 | uart0_pmux: uart0-pmux { | |
525 | groups = "GSM12"; | |
526 | function = "uart0"; | |
527 | }; | |
528 | ||
529 | uart1_pmux: uart1-pmux { | |
530 | groups = "GSM14"; | |
531 | function = "uart1"; | |
532 | }; | |
99f3deb8 AT |
533 | |
534 | twsi2_pmux: twsi2-pmux { | |
535 | groups = "GSM13"; | |
536 | function = "twsi2"; | |
537 | }; | |
538 | ||
539 | twsi3_pmux: twsi3-pmux { | |
540 | groups = "GSM14"; | |
541 | function = "twsi3"; | |
542 | }; | |
50cc24ff AT |
543 | }; |
544 | ||
374ddcbf AT |
545 | sic: interrupt-controller@e000 { |
546 | compatible = "snps,dw-apb-ictl"; | |
547 | reg = <0xe000 0x30>; | |
548 | interrupt-controller; | |
549 | #interrupt-cells = <1>; | |
550 | interrupt-parent = <&gic>; | |
551 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
552 | }; | |
553 | }; | |
554 | }; | |
555 | }; |