[deliverable/linux.git] / arch / arm / boot / dts / berlin2q.dtsi

/*
 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <dt-bindings/clock/berlin2q.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	model = "Marvell Armada 1500 pro (BG2-Q) SoC";
	compatible = "marvell,berlin2q", "marvell,berlin";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,berlin-smp";

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <3>;
		};
	};

	refclk: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0 0xf7000000 0x1000000>;
		interrupt-parent = <&gic>;

		sdhci0: sdhci@ab0000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0000 0x200>;
			clocks = <&chip CLKID_SDIO1XIN>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci1: sdhci@ab0800 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0800 0x200>;
			clocks = <&chip CLKID_SDIO1XIN>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci2: sdhci@ab1000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab1000 0x200>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip CLKID_SDIO1XIN>;
			status = "disabled";
		};

		l2: l2-cache-controller@ac0000 {
			compatible = "arm,pl310-cache";
			reg = <0xac0000 0x1000>;
			cache-level = <2>;
			arm,data-latency = <2 2 2>;
			arm,tag-latency = <2 2 2>;
		};

		scu: snoop-control-unit@ad0000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xad0000 0x58>;
		};

		local-timer@ad0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xad0600 0x20>;
			clocks = <&chip CLKID_TWD>;
			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
		};

		gic: interrupt-controller@ad1000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0xad1000 0x1000>, <0xad0100 0x100>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		cpu-ctrl@dd0000 {
			compatible = "marvell,berlin-cpu-ctrl";
			reg = <0xdd0000 0x10000>;
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			gpio0: gpio@0400 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0400 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porta: gpio-port@0 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <0>;
				};
			};

			gpio1: gpio@0800 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0800 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portb: gpio-port@1 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <1>;
				};
			};

			gpio2: gpio@0c00 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0c00 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portc: gpio-port@2 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <2>;
				};
			};

			gpio3: gpio@1000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x1000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portd: gpio-port@3 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <3>;
				};
			};

			i2c0: i2c@1400 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x1400 0x100>;
				interrupt-parent = <&aic>;
				interrupts = <4>;
				clocks = <&chip CLKID_CFG>;
				pinctrl-0 = <&twsi0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			i2c1: i2c@1800 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x1800 0x100>;
				interrupt-parent = <&aic>;
				interrupts = <5>;
				clocks = <&chip CLKID_CFG>;
				pinctrl-0 = <&twsi1_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			timer0: timer@2c00 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c00 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				interrupts = <8>;
			};

			timer1: timer@2c14 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c14 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer2: timer@2c28 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c28 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer3: timer@2c3c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c3c 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer4: timer@2c50 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c50 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer5: timer@2c64 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c64 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer6: timer@2c78 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c78 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer7: timer@2c8c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c8c 0x14>;
				clocks = <&chip CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			aic: interrupt-controller@3800 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3800 0x30>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio4: gpio@5000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x5000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porte: gpio-port@4 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
				};
			};

			gpio5: gpio@c000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0xc000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portf: gpio-port@5 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
				};
			};
		};

		chip: chip-control@ea0000 {
			compatible = "marvell,berlin2q-chip-ctrl";
			#clock-cells = <1>;
			reg = <0xea0000 0x400>, <0xdd0170 0x10>;
			clocks = <&refclk>;
			clock-names = "refclk";

			twsi0_pmux: twsi0-pmux {
				groups = "G6";
				function = "twsi0";
			};

			twsi1_pmux: twsi1-pmux {
				groups = "G7";
				function = "twsi1";
			};
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			i2c2: i2c@7000 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x7000 0x100>;
				interrupt-parent = <&sic>;
				interrupts = <6>;
				clocks = <&refclk>;
				pinctrl-0 = <&twsi2_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			i2c3: i2c@8000 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x8000 0x100>;
				interrupt-parent = <&sic>;
				interrupts = <7>;
				clocks = <&refclk>;
				pinctrl-0 = <&twsi3_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart0: uart@9000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x9000 0x100>;
				interrupt-parent = <&sic>;
				interrupts = <8>;
				clocks = <&refclk>;
				reg-shift = <2>;
				pinctrl-0 = <&uart0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart1: uart@a000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xa000 0x100>;
				interrupt-parent = <&sic>;
				interrupts = <9>;
				clocks = <&refclk>;
				reg-shift = <2>;
				pinctrl-0 = <&uart1_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			sysctrl: pin-controller@d000 {
				compatible = "marvell,berlin2q-system-ctrl";
				reg = <0xd000 0x100>;

				uart0_pmux: uart0-pmux {
					groups = "GSM12";
					function = "uart0";
				};

				uart1_pmux: uart1-pmux {
					groups = "GSM14";
					function = "uart1";
				};

				twsi2_pmux: twsi2-pmux {
					groups = "GSM13";
					function = "twsi2";
				};

				twsi3_pmux: twsi3-pmux {
					groups = "GSM14";
					function = "twsi3";
				};
			};

			sic: interrupt-controller@e000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0xe000 0x30>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};
Commit	Line	Data
374ddcbf AT	1	/*
	2	* Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
	3	*
	4	* This file is licensed under the terms of the GNU General Public
	5	* License version 2. This program is licensed "as is" without any
	6	* warranty of any kind, whether express or implied.
	7	*/
	8
414dcf8f	9	#include <dt-bindings/clock/berlin2q.h>
374ddcbf AT	10	#include <dt-bindings/interrupt-controller/arm-gic.h>
	11
	12	#include "skeleton.dtsi"
	13
	14	/ {
	15	model = "Marvell Armada 1500 pro (BG2-Q) SoC";
	16	compatible = "marvell,berlin2q", "marvell,berlin";
	17
	18	cpus {
	19	#address-cells = <1>;
	20	#size-cells = <0>;
d19c9367	21	enable-method = "marvell,berlin-smp";
374ddcbf AT	22
	23	cpu@0 {
	24	compatible = "arm,cortex-a9";
	25	device_type = "cpu";
	26	next-level-cache = <&l2>;
	27	reg = <0>;
	28	};
	29
	30	cpu@1 {
	31	compatible = "arm,cortex-a9";
	32	device_type = "cpu";
	33	next-level-cache = <&l2>;
	34	reg = <1>;
	35	};
	36
	37	cpu@2 {
	38	compatible = "arm,cortex-a9";
	39	device_type = "cpu";
	40	next-level-cache = <&l2>;
	41	reg = <2>;
	42	};
	43
	44	cpu@3 {
	45	compatible = "arm,cortex-a9";
	46	device_type = "cpu";
	47	next-level-cache = <&l2>;
	48	reg = <3>;
	49	};
	50	};
	51
414dcf8f	52	refclk: oscillator {
374ddcbf AT	53	compatible = "fixed-clock";
	54	#clock-cells = <0>;
	55	clock-frequency = <25000000>;
	56	};
	57
374ddcbf AT	58	soc {
	59	compatible = "simple-bus";
	60	#address-cells = <1>;
	61	#size-cells = <1>;
	62
	63	ranges = <0 0xf7000000 0x1000000>;
	64	interrupt-parent = <&gic>;
	65
0d859a6a AT	66	sdhci0: sdhci@ab0000 {
	67	compatible = "mrvl,pxav3-mmc";
	68	reg = <0xab0000 0x200>;
	69	clocks = <&chip CLKID_SDIO1XIN>;
	70	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	71	status = "disabled";
	72	};
	73
	74	sdhci1: sdhci@ab0800 {
	75	compatible = "mrvl,pxav3-mmc";
	76	reg = <0xab0800 0x200>;
	77	clocks = <&chip CLKID_SDIO1XIN>;
	78	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	79	status = "disabled";
	80	};
	81
	82	sdhci2: sdhci@ab1000 {
	83	compatible = "mrvl,pxav3-mmc";
	84	reg = <0xab1000 0x200>;
	85	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	86	clocks = <&chip CLKID_SDIO1XIN>;
	87	status = "disabled";
	88	};
	89
374ddcbf AT	90	l2: l2-cache-controller@ac0000 {
	91	compatible = "arm,pl310-cache";
	92	reg = <0xac0000 0x1000>;
	93	cache-level = <2>;
44991eb4 JZ	94	arm,data-latency = <2 2 2>;
44991eb4 JZ	95	arm,tag-latency = <2 2 2>;
374ddcbf AT	96	};
374ddcbf AT	97
0bd4b346 SH	98	scu: snoop-control-unit@ad0000 {
	99	compatible = "arm,cortex-a9-scu";
	100	reg = <0xad0000 0x58>;
	101	};
	102
374ddcbf AT	103	local-timer@ad0600 {
	104	compatible = "arm,cortex-a9-twd-timer";
	105	reg = <0xad0600 0x20>;
414dcf8f	106	clocks = <&chip CLKID_TWD>;
374ddcbf AT	107	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
	108	};
	109
	110	gic: interrupt-controller@ad1000 {
	111	compatible = "arm,cortex-a9-gic";
	112	reg = <0xad1000 0x1000>, <0xad0100 0x100>;
	113	interrupt-controller;
	114	#interrupt-cells = <3>;
	115	};
	116
d19c9367 AT	117	cpu-ctrl@dd0000 {
	118	compatible = "marvell,berlin-cpu-ctrl";
	119	reg = <0xdd0000 0x10000>;
	120	};
	121
374ddcbf AT	122	apb@e80000 {
	123	compatible = "simple-bus";
	124	#address-cells = <1>;
	125	#size-cells = <1>;
	126
	127	ranges = <0 0xe80000 0x10000>;
	128	interrupt-parent = <&aic>;
	129
cedf57fc AT	130	gpio0: gpio@0400 {
	131	compatible = "snps,dw-apb-gpio";
	132	reg = <0x0400 0x400>;
	133	#address-cells = <1>;
	134	#size-cells = <0>;
	135
	136	porta: gpio-port@0 {
	137	compatible = "snps,dw-apb-gpio-port";
	138	gpio-controller;
	139	#gpio-cells = <2>;
	140	snps,nr-gpios = <32>;
	141	reg = <0>;
	142	interrupt-controller;
	143	#interrupt-cells = <2>;
	144	interrupts = <0>;
	145	};
	146	};
	147
	148	gpio1: gpio@0800 {
	149	compatible = "snps,dw-apb-gpio";
	150	reg = <0x0800 0x400>;
	151	#address-cells = <1>;
	152	#size-cells = <0>;
	153
	154	portb: gpio-port@1 {
	155	compatible = "snps,dw-apb-gpio-port";
	156	gpio-controller;
	157	#gpio-cells = <2>;
	158	snps,nr-gpios = <32>;
	159	reg = <0>;
	160	interrupt-controller;
	161	#interrupt-cells = <2>;
	162	interrupts = <1>;
	163	};
	164	};
	165
	166	gpio2: gpio@0c00 {
	167	compatible = "snps,dw-apb-gpio";
	168	reg = <0x0c00 0x400>;
	169	#address-cells = <1>;
	170	#size-cells = <0>;
	171
	172	portc: gpio-port@2 {
	173	compatible = "snps,dw-apb-gpio-port";
	174	gpio-controller;
	175	#gpio-cells = <2>;
	176	snps,nr-gpios = <32>;
	177	reg = <0>;
	178	interrupt-controller;
	179	#interrupt-cells = <2>;
	180	interrupts = <2>;
	181	};
	182	};
	183
	184	gpio3: gpio@1000 {
	185	compatible = "snps,dw-apb-gpio";
	186	reg = <0x1000 0x400>;
	187	#address-cells = <1>;
	188	#size-cells = <0>;
	189
	190	portd: gpio-port@3 {
	191	compatible = "snps,dw-apb-gpio-port";
	192	gpio-controller;
	193	#gpio-cells = <2>;
194	snps,nr-gpios = <32>;
195	reg = <0>;
196	interrupt-controller;
197	#interrupt-cells = <2>;
198	interrupts = <3>;
199	};
200	};
201
99f3deb8 AT	202	i2c0: i2c@1400 {
	203	compatible = "snps,designware-i2c";
	204	#address-cells = <1>;
	205	#size-cells = <0>;
	206	reg = <0x1400 0x100>;
	207	interrupt-parent = <&aic>;
	208	interrupts = <4>;
	209	clocks = <&chip CLKID_CFG>;
	210	pinctrl-0 = <&twsi0_pmux>;
	211	pinctrl-names = "default";
	212	status = "disabled";
	213	};
	214
	215	i2c1: i2c@1800 {
	216	compatible = "snps,designware-i2c";
	217	#address-cells = <1>;
	218	#size-cells = <0>;
	219	reg = <0x1800 0x100>;
	220	interrupt-parent = <&aic>;
	221	interrupts = <5>;
	222	clocks = <&chip CLKID_CFG>;
	223	pinctrl-0 = <&twsi1_pmux>;
	224	pinctrl-names = "default";
	225	status = "disabled";
	226	};
	227
374ddcbf AT	228	timer0: timer@2c00 {
	229	compatible = "snps,dw-apb-timer";
	230	reg = <0x2c00 0x14>;
414dcf8f	231	clocks = <&chip CLKID_CFG>;
374ddcbf AT	232	clock-names = "timer";
	233	interrupts = <8>;
	234	};
	235
	236	timer1: timer@2c14 {
	237	compatible = "snps,dw-apb-timer";
	238	reg = <0x2c14 0x14>;
414dcf8f	239	clocks = <&chip CLKID_CFG>;
374ddcbf AT	240	clock-names = "timer";
	241	status = "disabled";
	242	};
	243
	244	timer2: timer@2c28 {
	245	compatible = "snps,dw-apb-timer";
	246	reg = <0x2c28 0x14>;
414dcf8f	247	clocks = <&chip CLKID_CFG>;
374ddcbf AT	248	clock-names = "timer";
	249	status = "disabled";
	250	};
	251
	252	timer3: timer@2c3c {
	253	compatible = "snps,dw-apb-timer";
	254	reg = <0x2c3c 0x14>;
414dcf8f	255	clocks = <&chip CLKID_CFG>;
374ddcbf AT	256	clock-names = "timer";
	257	status = "disabled";
	258	};
	259
	260	timer4: timer@2c50 {
	261	compatible = "snps,dw-apb-timer";
	262	reg = <0x2c50 0x14>;
414dcf8f	263	clocks = <&chip CLKID_CFG>;
374ddcbf AT	264	clock-names = "timer";
	265	status = "disabled";
	266	};
	267
	268	timer5: timer@2c64 {
	269	compatible = "snps,dw-apb-timer";
	270	reg = <0x2c64 0x14>;
414dcf8f	271	clocks = <&chip CLKID_CFG>;
374ddcbf AT	272	clock-names = "timer";
	273	status = "disabled";
	274	};
	275
	276	timer6: timer@2c78 {
	277	compatible = "snps,dw-apb-timer";
	278	reg = <0x2c78 0x14>;
414dcf8f	279	clocks = <&chip CLKID_CFG>;
374ddcbf AT	280	clock-names = "timer";
	281	status = "disabled";
	282	};
	283
	284	timer7: timer@2c8c {
	285	compatible = "snps,dw-apb-timer";
	286	reg = <0x2c8c 0x14>;
414dcf8f	287	clocks = <&chip CLKID_CFG>;
374ddcbf AT	288	clock-names = "timer";
	289	status = "disabled";
	290	};
	291
	292	aic: interrupt-controller@3800 {
	293	compatible = "snps,dw-apb-ictl";
	294	reg = <0x3800 0x30>;
	295	interrupt-controller;
	296	#interrupt-cells = <1>;
	297	interrupt-parent = <&gic>;
	298	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	299	};
cedf57fc AT	300
	301	gpio4: gpio@5000 {
	302	compatible = "snps,dw-apb-gpio";
	303	reg = <0x5000 0x400>;
	304	#address-cells = <1>;
	305	#size-cells = <0>;
	306
	307	porte: gpio-port@4 {
	308	compatible = "snps,dw-apb-gpio-port";
	309	gpio-controller;
	310	#gpio-cells = <2>;
	311	snps,nr-gpios = <32>;
	312	reg = <0>;
	313	};
	314	};
	315
	316	gpio5: gpio@c000 {
	317	compatible = "snps,dw-apb-gpio";
	318	reg = <0xc000 0x400>;
	319	#address-cells = <1>;
	320	#size-cells = <0>;
	321
	322	portf: gpio-port@5 {
	323	compatible = "snps,dw-apb-gpio-port";
	324	gpio-controller;
	325	#gpio-cells = <2>;
	326	snps,nr-gpios = <32>;
	327	reg = <0>;
	328	};
	329	};
374ddcbf AT	330	};
374ddcbf AT	331
414dcf8f AB	332	chip: chip-control@ea0000 {
	333	compatible = "marvell,berlin2q-chip-ctrl";
	334	#clock-cells = <1>;
	335	reg = <0xea0000 0x400>, <0xdd0170 0x10>;
	336	clocks = <&refclk>;
	337	clock-names = "refclk";
99f3deb8 AT	338
	339	twsi0_pmux: twsi0-pmux {
	340	groups = "G6";
	341	function = "twsi0";
	342	};
	343
	344	twsi1_pmux: twsi1-pmux {
	345	groups = "G7";
	346	function = "twsi1";
	347	};
0bd4b346 SH	348	};
0bd4b346 SH	349
374ddcbf AT	350	apb@fc0000 {
	351	compatible = "simple-bus";
	352	#address-cells = <1>;
	353	#size-cells = <1>;
	354
	355	ranges = <0 0xfc0000 0x10000>;
	356	interrupt-parent = <&sic>;
	357
99f3deb8 AT	358	i2c2: i2c@7000 {
	359	compatible = "snps,designware-i2c";
	360	#address-cells = <1>;
	361	#size-cells = <0>;
	362	reg = <0x7000 0x100>;
	363	interrupt-parent = <&sic>;
	364	interrupts = <6>;
	365	clocks = <&refclk>;
	366	pinctrl-0 = <&twsi2_pmux>;
	367	pinctrl-names = "default";
	368	status = "disabled";
	369	};
	370
	371	i2c3: i2c@8000 {
	372	compatible = "snps,designware-i2c";
	373	#address-cells = <1>;
	374	#size-cells = <0>;
	375	reg = <0x8000 0x100>;
	376	interrupt-parent = <&sic>;
	377	interrupts = <7>;
	378	clocks = <&refclk>;
	379	pinctrl-0 = <&twsi3_pmux>;
	380	pinctrl-names = "default";
	381	status = "disabled";
	382	};
	383
374ddcbf AT	384	uart0: uart@9000 {
	385	compatible = "snps,dw-apb-uart";
	386	reg = <0x9000 0x100>;
	387	interrupt-parent = <&sic>;
	388	interrupts = <8>;
414dcf8f	389	clocks = <&refclk>;
374ddcbf	390	reg-shift = <2>;
50cc24ff AT	391	pinctrl-0 = <&uart0_pmux>;
50cc24ff AT	392	pinctrl-names = "default";
374ddcbf AT	393	status = "disabled";
	394	};
	395
	396	uart1: uart@a000 {
	397	compatible = "snps,dw-apb-uart";
	398	reg = <0xa000 0x100>;
	399	interrupt-parent = <&sic>;
	400	interrupts = <9>;
414dcf8f	401	clocks = <&refclk>;
374ddcbf	402	reg-shift = <2>;
50cc24ff AT	403	pinctrl-0 = <&uart1_pmux>;
50cc24ff AT	404	pinctrl-names = "default";
374ddcbf AT	405	status = "disabled";
	406	};
	407
50cc24ff AT	408	sysctrl: pin-controller@d000 {
	409	compatible = "marvell,berlin2q-system-ctrl";
	410	reg = <0xd000 0x100>;
	411
	412	uart0_pmux: uart0-pmux {
	413	groups = "GSM12";
	414	function = "uart0";
	415	};
	416
	417	uart1_pmux: uart1-pmux {
	418	groups = "GSM14";
	419	function = "uart1";
	420	};
99f3deb8 AT	421
	422	twsi2_pmux: twsi2-pmux {
	423	groups = "GSM13";
	424	function = "twsi2";
	425	};
	426
	427	twsi3_pmux: twsi3-pmux {
	428	groups = "GSM14";
	429	function = "twsi3";
	430	};
50cc24ff AT	431	};
50cc24ff AT	432
374ddcbf AT	433	sic: interrupt-controller@e000 {
	434	compatible = "snps,dw-apb-ictl";
	435	reg = <0xe000 0x30>;
	436	interrupt-controller;
	437	#interrupt-cells = <1>;
	438	interrupt-parent = <&gic>;
	439	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	440	};
	441	};
	442	};
	443	};