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f3d953ea TL |
1 | /* |
2 | * This file is licensed under the terms of the GNU General Public License | |
3 | * version 2. This program is licensed "as is" without any warranty of any | |
4 | * kind, whether express or implied. | |
5 | */ | |
6 | ||
7 | #include <dt-bindings/gpio/gpio.h> | |
b4d6df2a | 8 | #include <dt-bindings/pinctrl/dm814x.h> |
f3d953ea TL |
9 | |
10 | #include "skeleton.dtsi" | |
11 | ||
12 | / { | |
13 | compatible = "ti,dm814"; | |
14 | interrupt-parent = <&intc>; | |
15 | ||
16 | aliases { | |
17 | i2c0 = &i2c1; | |
18 | i2c1 = &i2c2; | |
19 | serial0 = &uart1; | |
20 | serial1 = &uart2; | |
21 | serial2 = &uart3; | |
22 | ethernet0 = &cpsw_emac0; | |
23 | ethernet1 = &cpsw_emac1; | |
89639d9f TL |
24 | usb0 = &usb0; |
25 | usb1 = &usb1; | |
26 | phy0 = &usb0_phy; | |
27 | phy1 = &usb1_phy; | |
f3d953ea TL |
28 | }; |
29 | ||
30 | cpus { | |
31 | #address-cells = <1>; | |
32 | #size-cells = <0>; | |
33 | cpu@0 { | |
34 | compatible = "arm,cortex-a8"; | |
35 | device_type = "cpu"; | |
36 | reg = <0>; | |
37 | }; | |
38 | }; | |
39 | ||
40 | pmu { | |
41 | compatible = "arm,cortex-a8-pmu"; | |
42 | interrupts = <3>; | |
43 | }; | |
44 | ||
45 | /* | |
46 | * The soc node represents the soc top level view. It is used for IPs | |
47 | * that are not memory mapped in the MPU view or for the MPU itself. | |
48 | */ | |
49 | soc { | |
50 | compatible = "ti,omap-infra"; | |
51 | mpu { | |
52 | compatible = "ti,omap3-mpu"; | |
53 | ti,hwmods = "mpu"; | |
54 | }; | |
55 | }; | |
56 | ||
57 | ocp { | |
58 | compatible = "simple-bus"; | |
59 | #address-cells = <1>; | |
60 | #size-cells = <1>; | |
61 | ranges; | |
62 | ti,hwmods = "l3_main"; | |
63 | ||
89639d9f TL |
64 | usb: usb@47400000 { |
65 | compatible = "ti,am33xx-usb"; | |
66 | reg = <0x47400000 0x1000>; | |
67 | ranges; | |
68 | #address-cells = <1>; | |
69 | #size-cells = <1>; | |
70 | ti,hwmods = "usb_otg_hs"; | |
71 | ||
72 | usb0_phy: usb-phy@47401300 { | |
73 | compatible = "ti,am335x-usb-phy"; | |
74 | reg = <0x47401300 0x100>; | |
75 | reg-names = "phy"; | |
76 | ti,ctrl_mod = <&usb_ctrl_mod>; | |
77 | }; | |
78 | ||
79 | usb0: usb@47401000 { | |
80 | compatible = "ti,musb-am33xx"; | |
81 | reg = <0x47401400 0x400 | |
82 | 0x47401000 0x200>; | |
83 | reg-names = "mc", "control"; | |
84 | ||
85 | interrupts = <18>; | |
86 | interrupt-names = "mc"; | |
87 | dr_mode = "otg"; | |
88 | mentor,multipoint = <1>; | |
89 | mentor,num-eps = <16>; | |
90 | mentor,ram-bits = <12>; | |
91 | mentor,power = <500>; | |
92 | phys = <&usb0_phy>; | |
93 | ||
94 | dmas = <&cppi41dma 0 0 &cppi41dma 1 0 | |
95 | &cppi41dma 2 0 &cppi41dma 3 0 | |
96 | &cppi41dma 4 0 &cppi41dma 5 0 | |
97 | &cppi41dma 6 0 &cppi41dma 7 0 | |
98 | &cppi41dma 8 0 &cppi41dma 9 0 | |
99 | &cppi41dma 10 0 &cppi41dma 11 0 | |
100 | &cppi41dma 12 0 &cppi41dma 13 0 | |
101 | &cppi41dma 14 0 &cppi41dma 0 1 | |
102 | &cppi41dma 1 1 &cppi41dma 2 1 | |
103 | &cppi41dma 3 1 &cppi41dma 4 1 | |
104 | &cppi41dma 5 1 &cppi41dma 6 1 | |
105 | &cppi41dma 7 1 &cppi41dma 8 1 | |
106 | &cppi41dma 9 1 &cppi41dma 10 1 | |
107 | &cppi41dma 11 1 &cppi41dma 12 1 | |
108 | &cppi41dma 13 1 &cppi41dma 14 1>; | |
109 | dma-names = | |
110 | "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", | |
111 | "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", | |
112 | "rx14", "rx15", | |
113 | "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", | |
114 | "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", | |
115 | "tx14", "tx15"; | |
116 | }; | |
117 | ||
118 | usb1: usb@47401800 { | |
119 | compatible = "ti,musb-am33xx"; | |
120 | reg = <0x47401c00 0x400 | |
121 | 0x47401800 0x200>; | |
122 | reg-names = "mc", "control"; | |
123 | interrupts = <19>; | |
124 | interrupt-names = "mc"; | |
125 | dr_mode = "otg"; | |
126 | mentor,multipoint = <1>; | |
127 | mentor,num-eps = <16>; | |
128 | mentor,ram-bits = <12>; | |
129 | mentor,power = <500>; | |
130 | phys = <&usb1_phy>; | |
131 | ||
132 | dmas = <&cppi41dma 15 0 &cppi41dma 16 0 | |
133 | &cppi41dma 17 0 &cppi41dma 18 0 | |
134 | &cppi41dma 19 0 &cppi41dma 20 0 | |
135 | &cppi41dma 21 0 &cppi41dma 22 0 | |
136 | &cppi41dma 23 0 &cppi41dma 24 0 | |
137 | &cppi41dma 25 0 &cppi41dma 26 0 | |
138 | &cppi41dma 27 0 &cppi41dma 28 0 | |
139 | &cppi41dma 29 0 &cppi41dma 15 1 | |
140 | &cppi41dma 16 1 &cppi41dma 17 1 | |
141 | &cppi41dma 18 1 &cppi41dma 19 1 | |
142 | &cppi41dma 20 1 &cppi41dma 21 1 | |
143 | &cppi41dma 22 1 &cppi41dma 23 1 | |
144 | &cppi41dma 24 1 &cppi41dma 25 1 | |
145 | &cppi41dma 26 1 &cppi41dma 27 1 | |
146 | &cppi41dma 28 1 &cppi41dma 29 1>; | |
147 | dma-names = | |
148 | "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", | |
149 | "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", | |
150 | "rx14", "rx15", | |
151 | "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", | |
152 | "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", | |
153 | "tx14", "tx15"; | |
154 | }; | |
155 | ||
156 | cppi41dma: dma-controller@47402000 { | |
157 | compatible = "ti,am3359-cppi41"; | |
158 | reg = <0x47400000 0x1000 | |
159 | 0x47402000 0x1000 | |
160 | 0x47403000 0x1000 | |
161 | 0x47404000 0x4000>; | |
162 | reg-names = "glue", "controller", "scheduler", "queuemgr"; | |
163 | interrupts = <17>; | |
164 | interrupt-names = "glue"; | |
165 | #dma-cells = <2>; | |
166 | #dma-channels = <30>; | |
167 | #dma-requests = <256>; | |
168 | }; | |
169 | }; | |
170 | ||
f3d953ea | 171 | /* |
3a91b061 TL |
172 | * See TRM "Table 1-317. L4LS Instance Summary" for hints. |
173 | * It shows the module target agent registers though, so the | |
174 | * actual device is typically 0x1000 before the target agent | |
175 | * except in cases where the module is larger than 0x1000. | |
f3d953ea TL |
176 | */ |
177 | l4ls: l4ls@48000000 { | |
178 | compatible = "ti,dm814-l4ls", "simple-bus"; | |
179 | #address-cells = <1>; | |
180 | #size-cells = <1>; | |
181 | ranges = <0 0x48000000 0x2000000>; | |
182 | ||
183 | i2c1: i2c@28000 { | |
184 | compatible = "ti,omap4-i2c"; | |
185 | #address-cells = <1>; | |
186 | #size-cells = <0>; | |
187 | ti,hwmods = "i2c1"; | |
188 | reg = <0x28000 0x1000>; | |
189 | interrupts = <70>; | |
190 | }; | |
191 | ||
192 | elm: elm@80000 { | |
193 | compatible = "ti,814-elm"; | |
194 | ti,hwmods = "elm"; | |
195 | reg = <0x80000 0x2000>; | |
196 | interrupts = <4>; | |
197 | }; | |
198 | ||
199 | gpio1: gpio@32000 { | |
200 | compatible = "ti,omap4-gpio"; | |
201 | ti,hwmods = "gpio1"; | |
202 | ti,gpio-always-on; | |
203 | reg = <0x32000 0x2000>; | |
204 | interrupts = <96>; | |
205 | gpio-controller; | |
206 | #gpio-cells = <2>; | |
207 | interrupt-controller; | |
208 | #interrupt-cells = <2>; | |
209 | }; | |
210 | ||
211 | gpio2: gpio@4c000 { | |
212 | compatible = "ti,omap4-gpio"; | |
213 | ti,hwmods = "gpio2"; | |
214 | ti,gpio-always-on; | |
215 | reg = <0x4c000 0x2000>; | |
216 | interrupts = <98>; | |
217 | gpio-controller; | |
218 | #gpio-cells = <2>; | |
219 | interrupt-controller; | |
220 | #interrupt-cells = <2>; | |
221 | }; | |
222 | ||
223 | i2c2: i2c@2a000 { | |
224 | compatible = "ti,omap4-i2c"; | |
225 | #address-cells = <1>; | |
226 | #size-cells = <0>; | |
227 | ti,hwmods = "i2c2"; | |
228 | reg = <0x2a000 0x1000>; | |
229 | interrupts = <71>; | |
230 | }; | |
231 | ||
232 | mcspi1: spi@30000 { | |
233 | compatible = "ti,omap4-mcspi"; | |
234 | reg = <0x30000 0x1000>; | |
235 | #address-cells = <1>; | |
236 | #size-cells = <0>; | |
237 | interrupts = <65>; | |
238 | ti,spi-num-cs = <4>; | |
239 | ti,hwmods = "mcspi1"; | |
9a640422 TL |
240 | dmas = <&edma 16 0 &edma 17 0 |
241 | &edma 18 0 &edma 19 0>; | |
f3d953ea TL |
242 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
243 | }; | |
244 | ||
245 | timer1: timer@2e000 { | |
246 | compatible = "ti,dm814-timer"; | |
247 | reg = <0x2e000 0x2000>; | |
248 | interrupts = <67>; | |
249 | ti,hwmods = "timer1"; | |
250 | ti,timer-alwon; | |
251 | }; | |
252 | ||
253 | uart1: uart@20000 { | |
254 | compatible = "ti,omap3-uart"; | |
255 | ti,hwmods = "uart1"; | |
256 | reg = <0x20000 0x2000>; | |
257 | clock-frequency = <48000000>; | |
258 | interrupts = <72>; | |
9a640422 | 259 | dmas = <&edma 26 0 &edma 27 0>; |
f3d953ea TL |
260 | dma-names = "tx", "rx"; |
261 | }; | |
262 | ||
263 | uart2: uart@22000 { | |
264 | compatible = "ti,omap3-uart"; | |
265 | ti,hwmods = "uart2"; | |
266 | reg = <0x22000 0x2000>; | |
267 | clock-frequency = <48000000>; | |
268 | interrupts = <73>; | |
9a640422 | 269 | dmas = <&edma 28 0 &edma 29 0>; |
f3d953ea TL |
270 | dma-names = "tx", "rx"; |
271 | }; | |
272 | ||
273 | uart3: uart@24000 { | |
274 | compatible = "ti,omap3-uart"; | |
275 | ti,hwmods = "uart3"; | |
276 | reg = <0x24000 0x2000>; | |
277 | clock-frequency = <48000000>; | |
278 | interrupts = <74>; | |
9a640422 | 279 | dmas = <&edma 30 0 &edma 31 0>; |
f3d953ea TL |
280 | dma-names = "tx", "rx"; |
281 | }; | |
282 | ||
283 | timer2: timer@40000 { | |
284 | compatible = "ti,dm814-timer"; | |
285 | reg = <0x40000 0x2000>; | |
286 | interrupts = <68>; | |
287 | ti,hwmods = "timer2"; | |
288 | }; | |
289 | ||
290 | timer3: timer@42000 { | |
291 | compatible = "ti,dm814-timer"; | |
292 | reg = <0x42000 0x2000>; | |
293 | interrupts = <69>; | |
294 | ti,hwmods = "timer3"; | |
295 | }; | |
296 | ||
609e5574 TL |
297 | mmc1: mmc@60000 { |
298 | compatible = "ti,omap4-hsmmc"; | |
299 | ti,hwmods = "mmc1"; | |
300 | dmas = <&edma 24 0 | |
301 | &edma 25 0>; | |
302 | dma-names = "tx", "rx"; | |
303 | interrupts = <64>; | |
304 | interrupt-parent = <&intc>; | |
305 | reg = <0x60000 0x1000>; | |
306 | }; | |
307 | ||
f22b0b4f TL |
308 | rtc: rtc@c0000 { |
309 | compatible = "ti,am3352-rtc", "ti,da830-rtc"; | |
310 | reg = <0xc0000 0x1000>; | |
311 | interrupts = <75 76>; | |
312 | ti,hwmods = "rtc"; | |
313 | }; | |
314 | ||
609e5574 TL |
315 | mmc2: mmc@1d8000 { |
316 | compatible = "ti,omap4-hsmmc"; | |
317 | ti,hwmods = "mmc2"; | |
318 | dmas = <&edma 2 0 | |
319 | &edma 3 0>; | |
320 | dma-names = "tx", "rx"; | |
321 | interrupts = <28>; | |
322 | interrupt-parent = <&intc>; | |
323 | reg = <0x1d8000 0x1000>; | |
324 | }; | |
325 | ||
87ee15ec | 326 | control: control@140000 { |
f3d953ea | 327 | compatible = "ti,dm814-scm", "simple-bus"; |
3a91b061 | 328 | reg = <0x140000 0x20000>; |
f3d953ea TL |
329 | #address-cells = <1>; |
330 | #size-cells = <1>; | |
3a91b061 | 331 | ranges = <0 0x140000 0x20000>; |
f3d953ea TL |
332 | |
333 | scm_conf: scm_conf@0 { | |
334 | compatible = "syscon"; | |
335 | reg = <0x0 0x800>; | |
336 | #address-cells = <1>; | |
337 | #size-cells = <1>; | |
338 | ||
339 | scm_clocks: clocks { | |
340 | #address-cells = <1>; | |
341 | #size-cells = <0>; | |
342 | }; | |
343 | ||
344 | scm_clockdomains: clockdomains { | |
345 | }; | |
346 | }; | |
347 | ||
89639d9f TL |
348 | usb_ctrl_mod: control@620 { |
349 | compatible = "ti,am335x-usb-ctrl-module"; | |
350 | reg = <0x620 0x10 | |
351 | 0x648 0x4>; | |
352 | reg-names = "phy_ctrl", "wakeup"; | |
353 | }; | |
354 | ||
9a640422 TL |
355 | edma_xbar: dma-router@f90 { |
356 | compatible = "ti,am335x-edma-crossbar"; | |
357 | reg = <0xf90 0x40>; | |
358 | #dma-cells = <3>; | |
359 | dma-requests = <32>; | |
360 | dma-masters = <&edma>; | |
361 | }; | |
362 | ||
9621557f TL |
363 | /* |
364 | * Note that silicon revision 2.1 and older | |
365 | * require input enabled (bit 18 set) for all | |
366 | * 3.3V I/Os to avoid cumulative hardware damage. | |
367 | * For more info, see errata advisory 2.1.87. | |
368 | * We leave bit 18 out of function-mask and rely | |
369 | * on the bootloader for it. | |
370 | */ | |
f3d953ea TL |
371 | pincntl: pinmux@800 { |
372 | compatible = "pinctrl-single"; | |
9621557f | 373 | reg = <0x800 0x438>; |
f3d953ea TL |
374 | #address-cells = <1>; |
375 | #size-cells = <0>; | |
376 | pinctrl-single,register-width = <32>; | |
9621557f | 377 | pinctrl-single,function-mask = <0x307ff>; |
f3d953ea | 378 | }; |
89639d9f TL |
379 | |
380 | usb1_phy: usb-phy@1b00 { | |
381 | compatible = "ti,am335x-usb-phy"; | |
382 | reg = <0x1b00 0x100>; | |
383 | reg-names = "phy"; | |
384 | ti,ctrl_mod = <&usb_ctrl_mod>; | |
385 | }; | |
f3d953ea TL |
386 | }; |
387 | ||
388 | prcm: prcm@180000 { | |
389 | compatible = "ti,dm814-prcm", "simple-bus"; | |
7f8f0b11 TL |
390 | reg = <0x180000 0x2000>; |
391 | #address-cells = <1>; | |
392 | #size-cells = <1>; | |
393 | ranges = <0 0x180000 0x2000>; | |
f3d953ea TL |
394 | |
395 | prcm_clocks: clocks { | |
396 | #address-cells = <1>; | |
397 | #size-cells = <0>; | |
398 | }; | |
399 | ||
400 | prcm_clockdomains: clockdomains { | |
401 | }; | |
402 | }; | |
403 | ||
7f8f0b11 | 404 | /* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */ |
f3d953ea TL |
405 | pllss: pllss@1c5000 { |
406 | compatible = "ti,dm814-pllss", "simple-bus"; | |
7f8f0b11 TL |
407 | reg = <0x1c5000 0x1000>; |
408 | #address-cells = <1>; | |
409 | #size-cells = <1>; | |
410 | ranges = <0 0x1c5000 0x1000>; | |
f3d953ea TL |
411 | |
412 | pllss_clocks: clocks { | |
413 | #address-cells = <1>; | |
414 | #size-cells = <0>; | |
415 | }; | |
416 | ||
417 | pllss_clockdomains: clockdomains { | |
418 | }; | |
419 | }; | |
420 | ||
421 | wdt1: wdt@1c7000 { | |
422 | compatible = "ti,omap3-wdt"; | |
423 | ti,hwmods = "wd_timer"; | |
424 | reg = <0x1c7000 0x1000>; | |
425 | interrupts = <91>; | |
426 | }; | |
427 | }; | |
428 | ||
429 | intc: interrupt-controller@48200000 { | |
430 | compatible = "ti,dm814-intc"; | |
431 | interrupt-controller; | |
432 | #interrupt-cells = <1>; | |
433 | reg = <0x48200000 0x1000>; | |
434 | }; | |
435 | ||
609e5574 TL |
436 | /* Board must configure evtmux with edma_xbar for EDMA */ |
437 | mmc3: mmc@47810000 { | |
438 | compatible = "ti,omap4-hsmmc"; | |
439 | ti,hwmods = "mmc3"; | |
440 | interrupts = <29>; | |
441 | interrupt-parent = <&intc>; | |
442 | reg = <0x47810000 0x1000>; | |
443 | }; | |
444 | ||
f3d953ea | 445 | edma: edma@49000000 { |
9a640422 TL |
446 | compatible = "ti,edma3-tpcc"; |
447 | ti,hwmods = "tpcc"; | |
448 | reg = <0x49000000 0x10000>; | |
449 | reg-names = "edma3_cc"; | |
f3d953ea | 450 | interrupts = <12 13 14>; |
a5206553 | 451 | interrupt-names = "edma3_ccint", "edma3_mperr", |
9a640422 TL |
452 | "edma3_ccerrint"; |
453 | dma-requests = <64>; | |
454 | #dma-cells = <2>; | |
455 | ||
456 | ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, | |
457 | <&edma_tptc2 3>, <&edma_tptc3 0>; | |
458 | ||
459 | ti,edma-memcpy-channels = <20 21>; | |
460 | }; | |
461 | ||
462 | edma_tptc0: tptc@49800000 { | |
463 | compatible = "ti,edma3-tptc"; | |
464 | ti,hwmods = "tptc0"; | |
465 | reg = <0x49800000 0x100000>; | |
466 | interrupts = <112>; | |
467 | interrupt-names = "edma3_tcerrint"; | |
468 | }; | |
469 | ||
470 | edma_tptc1: tptc@49900000 { | |
471 | compatible = "ti,edma3-tptc"; | |
472 | ti,hwmods = "tptc1"; | |
473 | reg = <0x49900000 0x100000>; | |
474 | interrupts = <113>; | |
475 | interrupt-names = "edma3_tcerrint"; | |
476 | }; | |
477 | ||
478 | edma_tptc2: tptc@49a00000 { | |
479 | compatible = "ti,edma3-tptc"; | |
480 | ti,hwmods = "tptc2"; | |
481 | reg = <0x49a00000 0x100000>; | |
482 | interrupts = <114>; | |
483 | interrupt-names = "edma3_tcerrint"; | |
484 | }; | |
485 | ||
486 | edma_tptc3: tptc@49b00000 { | |
487 | compatible = "ti,edma3-tptc"; | |
488 | ti,hwmods = "tptc3"; | |
489 | reg = <0x49b00000 0x100000>; | |
490 | interrupts = <115>; | |
491 | interrupt-names = "edma3_tcerrint"; | |
f3d953ea TL |
492 | }; |
493 | ||
494 | /* See TRM "Table 1-318. L4HS Instance Summary" */ | |
495 | l4hs: l4hs@4a000000 { | |
496 | compatible = "ti,dm814-l4hs", "simple-bus"; | |
497 | #address-cells = <1>; | |
498 | #size-cells = <1>; | |
499 | ranges = <0 0x4a000000 0x1b4040>; | |
500 | }; | |
501 | ||
502 | /* REVISIT: Move to live under l4hs once driver is fixed */ | |
503 | mac: ethernet@4a100000 { | |
504 | compatible = "ti,cpsw"; | |
505 | ti,hwmods = "cpgmac0"; | |
506 | clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; | |
507 | clock-names = "fck", "cpts"; | |
508 | cpdma_channels = <8>; | |
509 | ale_entries = <1024>; | |
510 | bd_ram_size = <0x2000>; | |
511 | no_bd_ram = <0>; | |
f3d953ea TL |
512 | mac_control = <0x20>; |
513 | slaves = <2>; | |
514 | active_slave = <0>; | |
515 | cpts_clock_mult = <0x80000000>; | |
516 | cpts_clock_shift = <29>; | |
517 | reg = <0x4a100000 0x800 | |
518 | 0x4a100900 0x100>; | |
519 | #address-cells = <1>; | |
520 | #size-cells = <1>; | |
521 | interrupt-parent = <&intc>; | |
522 | /* | |
523 | * c0_rx_thresh_pend | |
524 | * c0_rx_pend | |
525 | * c0_tx_pend | |
526 | * c0_misc_pend | |
527 | */ | |
528 | interrupts = <40 41 42 43>; | |
529 | ranges; | |
530 | syscon = <&scm_conf>; | |
531 | ||
532 | davinci_mdio: mdio@4a100800 { | |
533 | compatible = "ti,davinci_mdio"; | |
534 | #address-cells = <1>; | |
535 | #size-cells = <0>; | |
536 | ti,hwmods = "davinci_mdio"; | |
537 | bus_freq = <1000000>; | |
538 | reg = <0x4a100800 0x100>; | |
539 | }; | |
540 | ||
541 | cpsw_emac0: slave@4a100200 { | |
542 | /* Filled in by U-Boot */ | |
543 | mac-address = [ 00 00 00 00 00 00 ]; | |
544 | }; | |
545 | ||
546 | cpsw_emac1: slave@4a100300 { | |
547 | /* Filled in by U-Boot */ | |
548 | mac-address = [ 00 00 00 00 00 00 ]; | |
549 | }; | |
550 | ||
87ee15ec | 551 | phy_sel: cpsw-phy-sel@48140650 { |
f3d953ea | 552 | compatible = "ti,am3352-cpsw-phy-sel"; |
87ee15ec | 553 | reg= <0x48140650 0x4>; |
f3d953ea TL |
554 | reg-names = "gmii-sel"; |
555 | }; | |
556 | }; | |
003fb0ae TL |
557 | |
558 | gpmc: gpmc@50000000 { | |
559 | compatible = "ti,am3352-gpmc"; | |
560 | ti,hwmods = "gpmc"; | |
561 | ti,no-idle-on-init; | |
562 | reg = <0x50000000 0x2000>; | |
563 | interrupts = <100>; | |
564 | gpmc,num-cs = <7>; | |
565 | gpmc,num-waitpins = <2>; | |
566 | #address-cells = <2>; | |
567 | #size-cells = <1>; | |
0c3e192a RQ |
568 | interrupt-controller; |
569 | #interrupt-cells = <2>; | |
0cac398b RQ |
570 | gpio-controller; |
571 | #gpio-cells = <2>; | |
003fb0ae | 572 | }; |
f3d953ea TL |
573 | }; |
574 | }; | |
25515b63 TL |
575 | |
576 | #include "dm814x-clocks.dtsi" |