[deliverable/linux.git] / arch / arm / boot / dts / dm816x.dtsi

/*
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/omap.h>

#include "skeleton.dtsi"

/ {
	compatible = "ti,dm816";
	interrupt-parent = <&intc>;

	aliases {
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		ethernet0 = &eth0;
		ethernet1 = &eth1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "arm,cortex-a8";
			device_type = "cpu";
			reg = <0>;
		};
	};

	pmu {
		compatible = "arm,cortex-a8-pmu";
		interrupts = <3>;
	};

	/*
	 * The soc node represents the soc top level view. It is used for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap3-mpu";
			ti,hwmods = "mpu";
		};
	};

	/*
	 * XXX: Use a flat representation of the dm816x interconnect.
	 * The real dm816x interconnect network is quite complex. Since
	 * it will not bring real advantage to represent that in DT
	 * for the moment, just use a fake OCP bus entry to represent
	 * the whole bus hierarchy.
	 */
	ocp {
		compatible = "ti,omap3-l3-smx", "simple-bus";
		reg = <0x44000000 0x10000>;
		interrupts = <9 10>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main";

		prcm: prcm@48180000 {
			compatible = "ti,dm816-prcm";
			reg = <0x48180000 0x4000>;

			prcm_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			prcm_clockdomains: clockdomains {
			};
		};

		scrm: scrm@48140000 {
			compatible = "ti,dm816-scrm", "simple-bus";
			reg = <0x48140000 0x21000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x48140000 0x21000>;

			dm816x_pinmux: pinmux@800 {
				compatible = "pinctrl-single";
				reg = <0x800 0x50a>;
				#address-cells = <1>;
				#size-cells = <0>;
				pinctrl-single,register-width = <16>;
				pinctrl-single,function-mask = <0xf>;
			};

			/* Device Configuration Registers */
			scm_conf: syscon@600 {
				compatible = "syscon", "simple-bus";
				reg = <0x600 0x110>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x600 0x110>;

				usb_phy0: usb-phy@20 {
					compatible = "ti,dm8168-usb-phy";
					reg = <0x20 0x8>;
					reg-names = "phy";
					clocks = <&main_fapll 6>;
					clock-names = "refclk";
					#phy-cells = <0>;
					syscon = <&scm_conf>;
				};

				usb_phy1: usb-phy@28 {
					compatible = "ti,dm8168-usb-phy";
					reg = <0x28 0x8>;
					reg-names = "phy";
					clocks = <&main_fapll 6>;
					clock-names = "refclk";
					#phy-cells = <0>;
					syscon = <&scm_conf>;
				};
			};

			scrm_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			scrm_clockdomains: clockdomains {
			};
		};

		edma: edma@49000000 {
			compatible = "ti,edma3";
			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
			reg =   <0x49000000 0x10000>,
			        <0x44e10f90 0x40>;
			interrupts = <12 13 14>;
			#dma-cells = <1>;
		};

		elm: elm@48080000 {
			compatible = "ti,816-elm";
			ti,hwmods = "elm";
			reg = <0x48080000 0x2000>;
			interrupts = <4>;
		};

		gpio1: gpio@48032000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio1";
			ti,gpio-always-on;
			reg = <0x48032000 0x1000>;
			interrupts = <96>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@4804c000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio2";
			ti,gpio-always-on;
			reg = <0x4804c000 0x1000>;
			interrupts = <98>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpmc: gpmc@50000000 {
			compatible = "ti,am3352-gpmc";
			ti,hwmods = "gpmc";
			reg = <0x50000000 0x2000>;
			#address-cells = <2>;
			#size-cells = <1>;
			interrupts = <100>;
			gpmc,num-cs = <6>;
			gpmc,num-waitpins = <2>;
		};

		i2c1: i2c@48028000 {
			compatible = "ti,omap4-i2c";
			ti,hwmods = "i2c1";
			reg = <0x48028000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <70>;
			dmas = <&edma 58 &edma 59>;
			dma-names = "tx", "rx";
		};

		i2c2: i2c@4802a000 {
			compatible = "ti,omap4-i2c";
			ti,hwmods = "i2c2";
			reg = <0x4802a000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <71>;
			dmas = <&edma 60 &edma 61>;
			dma-names = "tx", "rx";
		};

		intc: interrupt-controller@48200000 {
			compatible = "ti,dm816-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x48200000 0x1000>;
		};

		mailbox: mailbox@480c8000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x480c8000 0x2000>;
			interrupts = <77>;
			ti,hwmods = "mailbox";
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <12>;
			mbox_dsp: mbox_dsp {
				ti,mbox-tx = <3 0 0>;
				ti,mbox-rx = <0 0 0>;
			};
		};

		mdio: mdio@4a100800 {
			compatible = "ti,davinci_mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x4a100800 0x100>;
			ti,hwmods = "davinci_mdio";
			bus_freq = <1000000>;
			phy0: ethernet-phy@0 {
				reg = <1>;
			};
			phy1: ethernet-phy@1 {
				reg = <2>;
			};
		};

		eth0: ethernet@4a100000 {
			compatible = "ti,dm816-emac";
			ti,hwmods = "emac0";
			reg = <0x4a100000 0x800
			       0x4a100900 0x3700>;
			clocks = <&sysclk24_ck>;
			syscon = <&scm_conf>;
			ti,davinci-ctrl-reg-offset = <0>;
			ti,davinci-ctrl-mod-reg-offset = <0x900>;
			ti,davinci-ctrl-ram-offset = <0x2000>;
			ti,davinci-ctrl-ram-size = <0x2000>;
			interrupts = <40 41 42 43>;
			phy-handle = <&phy0>;
		};

		eth1: ethernet@4a120000 {
			compatible = "ti,dm816-emac";
			ti,hwmods = "emac1";
			reg = <0x4a120000 0x4000>;
			clocks = <&sysclk24_ck>;
			syscon = <&scm_conf>;
			ti,davinci-ctrl-reg-offset = <0>;
			ti,davinci-ctrl-mod-reg-offset = <0x900>;
			ti,davinci-ctrl-ram-offset = <0x2000>;
			ti,davinci-ctrl-ram-size = <0x2000>;
			interrupts = <44 45 46 47>;
			phy-handle = <&phy1>;
		};

		mcspi1: spi@48030000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x48030000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <65>;
			ti,spi-num-cs = <4>;
			ti,hwmods = "mcspi1";
			dmas = <&edma 16 &edma 17
				&edma 18 &edma 19>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
		};

		mmc1: mmc@48060000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x48060000 0x11000>;
			ti,hwmods = "mmc1";
			interrupts = <64>;
			dmas = <&edma 24 &edma 25>;
			dma-names = "tx", "rx";
		};

		timer1: timer@4802e000 {
			compatible = "ti,dm816-timer";
			reg = <0x4802e000 0x2000>;
			interrupts = <67>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		timer2: timer@48040000 {
			compatible = "ti,dm816-timer";
			reg = <0x48040000 0x2000>;
			interrupts = <68>;
			ti,hwmods = "timer2";
		};

		timer3: timer@48042000 {
			compatible = "ti,dm816-timer";
			reg = <0x48042000 0x2000>;
			interrupts = <69>;
			ti,hwmods = "timer3";
		};

		timer4: timer@48044000 {
			compatible = "ti,dm816-timer";
			reg = <0x48044000 0x2000>;
			interrupts = <92>;
			ti,hwmods = "timer4";
		};

		timer5: timer@48046000 {
			compatible = "ti,dm816-timer";
			reg = <0x48046000 0x2000>;
			interrupts = <93>;
			ti,hwmods = "timer5";
		};

		timer6: timer@48048000 {
			compatible = "ti,dm816-timer";
			reg = <0x48048000 0x2000>;
			interrupts = <94>;
			ti,hwmods = "timer6";
		};

		timer7: timer@4804a000 {
			compatible = "ti,dm816-timer";
			reg = <0x4804a000 0x2000>;
			interrupts = <95>;
			ti,hwmods = "timer7";
		};

		uart1: uart@48020000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart1";
			reg = <0x48020000 0x2000>;
			clock-frequency = <48000000>;
			interrupts = <72>;
			dmas = <&edma 26 &edma 27>;
			dma-names = "tx", "rx";
		};

		uart2: uart@48022000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart2";
			reg = <0x48022000 0x2000>;
			clock-frequency = <48000000>;
			interrupts = <73>;
			dmas = <&edma 28 &edma 29>;
			dma-names = "tx", "rx";
		};

		uart3: uart@48024000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart3";
			reg = <0x48024000 0x2000>;
			clock-frequency = <48000000>;
			interrupts = <74>;
			dmas = <&edma 30 &edma 31>;
			dma-names = "tx", "rx";
		};

		/* NOTE: USB needs a transceiver driver for phys to work */
		usb: usb_otg_hs@47401000 {
			compatible = "ti,am33xx-usb";
			reg = <0x47401000 0x400000>;
			ranges;
			#address-cells = <1>;
			#size-cells = <1>;
			ti,hwmods = "usb_otg_hs";

			usb0: usb@47401000 {
				compatible = "ti,musb-am33xx";
				reg = <0x47401400 0x400
				       0x47401000 0x200>;
				reg-names = "mc", "control";
				interrupts = <18>;
				interrupt-names = "mc";
				dr_mode = "host";
				interface-type = <0>;
				phys = <&usb_phy0>;
				phy-names = "usb2-phy";
				mentor,multipoint = <1>;
				mentor,num-eps = <16>;
				mentor,ram-bits = <12>;
				mentor,power = <500>;
			};

			usb1: usb@47401800 {
				compatible = "ti,musb-am33xx";
				reg = <0x47401c00 0x400
				       0x47401800 0x200>;
				reg-names = "mc", "control";
				interrupts = <19>;
				interrupt-names = "mc";
				dr_mode = "host";
				interface-type = <0>;
				phys = <&usb_phy1>;
				phy-names = "usb2-phy";
				mentor,multipoint = <1>;
				mentor,num-eps = <16>;
				mentor,ram-bits = <12>;
				mentor,power = <500>;
			};
		};

		wd_timer2: wd_timer@480c2000 {
			compatible = "ti,omap3-wdt";
			ti,hwmods = "wd_timer";
			reg = <0x480c2000 0x1000>;
			interrupts = <0>;
		};
	};
};

#include "dm816x-clocks.dtsi"
Commit	Line	Data
7800064b TL	1	/*
	2	* This file is licensed under the terms of the GNU General Public License
	3	* version 2. This program is licensed "as is" without any warranty of any
	4	* kind, whether express or implied.
	5	*/
	6
	7	#include <dt-bindings/gpio/gpio.h>
	8	#include <dt-bindings/pinctrl/omap.h>
	9
	10	#include "skeleton.dtsi"
	11
	12	/ {
	13	compatible = "ti,dm816";
	14	interrupt-parent = <&intc>;
	15
	16	aliases {
	17	i2c0 = &i2c1;
	18	i2c1 = &i2c2;
	19	serial0 = &uart1;
	20	serial1 = &uart2;
	21	serial2 = &uart3;
	22	ethernet0 = &eth0;
	23	ethernet1 = &eth1;
	24	};
	25
	26	cpus {
	27	#address-cells = <1>;
	28	#size-cells = <0>;
	29	cpu@0 {
	30	compatible = "arm,cortex-a8";
	31	device_type = "cpu";
	32	reg = <0>;
	33	};
	34	};
	35
	36	pmu {
	37	compatible = "arm,cortex-a8-pmu";
	38	interrupts = <3>;
	39	};
	40
	41	/*
	42	* The soc node represents the soc top level view. It is used for IPs
	43	* that are not memory mapped in the MPU view or for the MPU itself.
	44	*/
	45	soc {
	46	compatible = "ti,omap-infra";
	47	mpu {
	48	compatible = "ti,omap3-mpu";
	49	ti,hwmods = "mpu";
	50	};
	51	};
	52
7800064b TL	53	/*
	54	* XXX: Use a flat representation of the dm816x interconnect.
	55	* The real dm816x interconnect network is quite complex. Since
	56	* it will not bring real advantage to represent that in DT
	57	* for the moment, just use a fake OCP bus entry to represent
	58	* the whole bus hierarchy.
	59	*/
	60	ocp {
	61	compatible = "ti,omap3-l3-smx", "simple-bus";
	62	reg = <0x44000000 0x10000>;
	63	interrupts = <9 10>;
	64	#address-cells = <1>;
	65	#size-cells = <1>;
	66	ranges;
	67	ti,hwmods = "l3_main";
	68
	69	prcm: prcm@48180000 {
	70	compatible = "ti,dm816-prcm";
	71	reg = <0x48180000 0x4000>;
	72
	73	prcm_clocks: clocks {
	74	#address-cells = <1>;
	75	#size-cells = <0>;
	76	};
	77
	78	prcm_clockdomains: clockdomains {
	79	};
	80	};
	81
	82	scrm: scrm@48140000 {
72d03226	83	compatible = "ti,dm816-scrm", "simple-bus";
7800064b TL	84	reg = <0x48140000 0x21000>;
	85	#address-cells = <1>;
	86	#size-cells = <1>;
	87	ranges = <0 0x48140000 0x21000>;
	88
72d03226 TL	89	dm816x_pinmux: pinmux@800 {
	90	compatible = "pinctrl-single";
	91	reg = <0x800 0x50a>;
	92	#address-cells = <1>;
	93	#size-cells = <0>;
	94	pinctrl-single,register-width = <16>;
	95	pinctrl-single,function-mask = <0xf>;
	96	};
	97
	98	/* Device Configuration Registers */
	99	scm_conf: syscon@600 {
a54879a0	100	compatible = "syscon", "simple-bus";
72d03226 TL	101	reg = <0x600 0x110>;
	102	#address-cells = <1>;
	103	#size-cells = <1>;
a54879a0 TL	104	ranges = <0 0x600 0x110>;
	105
	106	usb_phy0: usb-phy@20 {
	107	compatible = "ti,dm8168-usb-phy";
	108	reg = <0x20 0x8>;
	109	reg-names = "phy";
	110	clocks = <&main_fapll 6>;
	111	clock-names = "refclk";
	112	#phy-cells = <0>;
	113	syscon = <&scm_conf>;
	114	};
	115
	116	usb_phy1: usb-phy@28 {
	117	compatible = "ti,dm8168-usb-phy";
	118	reg = <0x28 0x8>;
	119	reg-names = "phy";
	120	clocks = <&main_fapll 6>;
	121	clock-names = "refclk";
	122	#phy-cells = <0>;
	123	syscon = <&scm_conf>;
	124	};
72d03226 TL	125	};
72d03226 TL	126
7800064b TL	127	scrm_clocks: clocks {
	128	#address-cells = <1>;
	129	#size-cells = <0>;
	130	};
	131
	132	scrm_clockdomains: clockdomains {
	133	};
	134	};
	135
7800064b TL	136	edma: edma@49000000 {
	137	compatible = "ti,edma3";
	138	ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
	139	reg = <0x49000000 0x10000>,
	140	<0x44e10f90 0x40>;
	141	interrupts = <12 13 14>;
	142	#dma-cells = <1>;
	143	};
	144
	145	elm: elm@48080000 {
	146	compatible = "ti,816-elm";
	147	ti,hwmods = "elm";
	148	reg = <0x48080000 0x2000>;
	149	interrupts = <4>;
	150	};
	151
	152	gpio1: gpio@48032000 {
599c376c	153	compatible = "ti,omap4-gpio";
7800064b	154	ti,hwmods = "gpio1";
599c376c	155	ti,gpio-always-on;
7800064b	156	reg = <0x48032000 0x1000>;
599c376c TL	157	interrupts = <96>;
	158	gpio-controller;
	159	#gpio-cells = <2>;
	160	interrupt-controller;
	161	#interrupt-cells = <2>;
7800064b TL	162	};
	163
	164	gpio2: gpio@4804c000 {
599c376c	165	compatible = "ti,omap4-gpio";
7800064b	166	ti,hwmods = "gpio2";
599c376c	167	ti,gpio-always-on;
7800064b	168	reg = <0x4804c000 0x1000>;
599c376c TL	169	interrupts = <98>;
	170	gpio-controller;
	171	#gpio-cells = <2>;
	172	interrupt-controller;
	173	#interrupt-cells = <2>;
7800064b TL	174	};
	175
	176	gpmc: gpmc@50000000 {
	177	compatible = "ti,am3352-gpmc";
	178	ti,hwmods = "gpmc";
	179	reg = <0x50000000 0x2000>;
	180	#address-cells = <2>;
	181	#size-cells = <1>;
	182	interrupts = <100>;
	183	gpmc,num-cs = <6>;
	184	gpmc,num-waitpins = <2>;
	185	};
	186
	187	i2c1: i2c@48028000 {
	188	compatible = "ti,omap4-i2c";
	189	ti,hwmods = "i2c1";
	190	reg = <0x48028000 0x1000>;
	191	#address-cells = <1>;
	192	#size-cells = <0>;
	193	interrupts = <70>;
	194	dmas = <&edma 58 &edma 59>;
	195	dma-names = "tx", "rx";
	196	};
	197
	198	i2c2: i2c@4802a000 {
	199	compatible = "ti,omap4-i2c";
	200	ti,hwmods = "i2c2";
	201	reg = <0x4802a000 0x1000>;
	202	#address-cells = <1>;
	203	#size-cells = <0>;
	204	interrupts = <71>;
	205	dmas = <&edma 60 &edma 61>;
	206	dma-names = "tx", "rx";
	207	};
	208
	209	intc: interrupt-controller@48200000 {
	210	compatible = "ti,dm816-intc";
	211	interrupt-controller;
	212	#interrupt-cells = <1>;
	213	reg = <0x48200000 0x1000>;
	214	};
	215
	216	mailbox: mailbox@480c8000 {
	217	compatible = "ti,omap4-mailbox";
	218	reg = <0x480c8000 0x2000>;
	219	interrupts = <77>;
	220	ti,hwmods = "mailbox";
	221	ti,mbox-num-users = <4>;
	222	ti,mbox-num-fifos = <12>;
	223	mbox_dsp: mbox_dsp {
	224	ti,mbox-tx = <3 0 0>;
	225	ti,mbox-rx = <0 0 0>;
	226	};
	227	};
	228
	229	mdio: mdio@4a100800 {
	230	compatible = "ti,davinci_mdio";
	231	#address-cells = <1>;
	232	#size-cells = <0>;
	233	reg = <0x4a100800 0x100>;
	234	ti,hwmods = "davinci_mdio";
	235	bus_freq = <1000000>;
	236	phy0: ethernet-phy@0 {
	237	reg = <1>;
238	};
239	phy1: ethernet-phy@1 {
240	reg = <2>;
241	};
242	};
243
244	eth0: ethernet@4a100000 {
245	compatible = "ti,dm816-emac";
246	ti,hwmods = "emac0";
247	reg = <0x4a100000 0x800
248	0x4a100900 0x3700>;
249	clocks = <&sysclk24_ck>;
72d03226	250	syscon = <&scm_conf>;
7800064b TL	251	ti,davinci-ctrl-reg-offset = <0>;
	252	ti,davinci-ctrl-mod-reg-offset = <0x900>;
	253	ti,davinci-ctrl-ram-offset = <0x2000>;
	254	ti,davinci-ctrl-ram-size = <0x2000>;
	255	interrupts = <40 41 42 43>;
	256	phy-handle = <&phy0>;
	257	};
	258
	259	eth1: ethernet@4a120000 {
	260	compatible = "ti,dm816-emac";
	261	ti,hwmods = "emac1";
	262	reg = <0x4a120000 0x4000>;
	263	clocks = <&sysclk24_ck>;
72d03226	264	syscon = <&scm_conf>;
7800064b TL	265	ti,davinci-ctrl-reg-offset = <0>;
	266	ti,davinci-ctrl-mod-reg-offset = <0x900>;
	267	ti,davinci-ctrl-ram-offset = <0x2000>;
	268	ti,davinci-ctrl-ram-size = <0x2000>;
	269	interrupts = <44 45 46 47>;
	270	phy-handle = <&phy1>;
	271	};
	272
	273	mcspi1: spi@48030000 {
	274	compatible = "ti,omap4-mcspi";
	275	reg = <0x48030000 0x1000>;
	276	#address-cells = <1>;
	277	#size-cells = <0>;
	278	interrupts = <65>;
	279	ti,spi-num-cs = <4>;
	280	ti,hwmods = "mcspi1";
	281	dmas = <&edma 16 &edma 17
	282	&edma 18 &edma 19>;
	283	dma-names = "tx0", "rx0", "tx1", "rx1";
	284	};
	285
	286	mmc1: mmc@48060000 {
	287	compatible = "ti,omap4-hsmmc";
	288	reg = <0x48060000 0x11000>;
	289	ti,hwmods = "mmc1";
	290	interrupts = <64>;
	291	dmas = <&edma 24 &edma 25>;
	292	dma-names = "tx", "rx";
	293	};
	294
	295	timer1: timer@4802e000 {
	296	compatible = "ti,dm816-timer";
	297	reg = <0x4802e000 0x2000>;
	298	interrupts = <67>;
	299	ti,hwmods = "timer1";
	300	ti,timer-alwon;
	301	};
	302
	303	timer2: timer@48040000 {
	304	compatible = "ti,dm816-timer";
	305	reg = <0x48040000 0x2000>;
	306	interrupts = <68>;
	307	ti,hwmods = "timer2";
	308	};
	309
	310	timer3: timer@48042000 {
	311	compatible = "ti,dm816-timer";
	312	reg = <0x48042000 0x2000>;
	313	interrupts = <69>;
	314	ti,hwmods = "timer3";
	315	};
	316
	317	timer4: timer@48044000 {
	318	compatible = "ti,dm816-timer";
	319	reg = <0x48044000 0x2000>;
	320	interrupts = <92>;
	321	ti,hwmods = "timer4";
	322	};
	323
	324	timer5: timer@48046000 {
	325	compatible = "ti,dm816-timer";
	326	reg = <0x48046000 0x2000>;
	327	interrupts = <93>;
	328	ti,hwmods = "timer5";
329	};
330
331	timer6: timer@48048000 {
332	compatible = "ti,dm816-timer";
333	reg = <0x48048000 0x2000>;
334	interrupts = <94>;
335	ti,hwmods = "timer6";
336	};
337
338	timer7: timer@4804a000 {
339	compatible = "ti,dm816-timer";
340	reg = <0x4804a000 0x2000>;
341	interrupts = <95>;
342	ti,hwmods = "timer7";
343	};
344
345	uart1: uart@48020000 {
346	compatible = "ti,omap3-uart";
347	ti,hwmods = "uart1";
348	reg = <0x48020000 0x2000>;
349	clock-frequency = <48000000>;
350	interrupts = <72>;
351	dmas = <&edma 26 &edma 27>;
352	dma-names = "tx", "rx";
353	};
354
355	uart2: uart@48022000 {
356	compatible = "ti,omap3-uart";
357	ti,hwmods = "uart2";
358	reg = <0x48022000 0x2000>;
359	clock-frequency = <48000000>;
360	interrupts = <73>;
361	dmas = <&edma 28 &edma 29>;
362	dma-names = "tx", "rx";
363	};
364
365	uart3: uart@48024000 {
366	compatible = "ti,omap3-uart";
367	ti,hwmods = "uart3";
368	reg = <0x48024000 0x2000>;
369	clock-frequency = <48000000>;
370	interrupts = <74>;
371	dmas = <&edma 30 &edma 31>;
372	dma-names = "tx", "rx";
373	};
374
375	/* NOTE: USB needs a transceiver driver for phys to work */
376	usb: usb_otg_hs@47401000 {
377	compatible = "ti,am33xx-usb";
378	reg = <0x47401000 0x400000>;
379	ranges;
380	#address-cells = <1>;
381	#size-cells = <1>;
382	ti,hwmods = "usb_otg_hs";
383
384	usb0: usb@47401000 {
385	compatible = "ti,musb-am33xx";
386	reg = <0x47401400 0x400
387	0x47401000 0x200>;
388	reg-names = "mc", "control";
389	interrupts = <18>;
390	interrupt-names = "mc";
a54879a0 TL	391	dr_mode = "host";
	392	interface-type = <0>;
	393	phys = <&usb_phy0>;
	394	phy-names = "usb2-phy";
7800064b TL	395	mentor,multipoint = <1>;
	396	mentor,num-eps = <16>;
	397	mentor,ram-bits = <12>;
	398	mentor,power = <500>;
	399	};
	400
	401	usb1: usb@47401800 {
	402	compatible = "ti,musb-am33xx";
7800064b TL	403	reg = <0x47401c00 0x400
	404	0x47401800 0x200>;
	405	reg-names = "mc", "control";
	406	interrupts = <19>;
	407	interrupt-names = "mc";
a54879a0 TL	408	dr_mode = "host";
	409	interface-type = <0>;
	410	phys = <&usb_phy1>;
	411	phy-names = "usb2-phy";
7800064b TL	412	mentor,multipoint = <1>;
	413	mentor,num-eps = <16>;
	414	mentor,ram-bits = <12>;
	415	mentor,power = <500>;
	416	};
	417	};
	418
	419	wd_timer2: wd_timer@480c2000 {
	420	compatible = "ti,omap3-wdt";
	421	ti,hwmods = "wd_timer";
	422	reg = <0x480c2000 0x1000>;
	423	interrupts = <0>;
	424	};
	425	};
	426	};
	427
7383ca92	428	#include "dm816x-clocks.dtsi"