Merge git://git.infradead.org/intel-iommu
[deliverable/linux.git] / arch / arm / boot / dts / dove-cubox.dts
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1/dts-v1/;
2
fbd99d51 3#include "dove.dtsi"
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4
5/ {
6 model = "SolidRun CuBox";
7 compatible = "solidrun,cubox", "marvell,dove";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x40000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk";
16 };
17
18 leds {
19 compatible = "gpio-leds";
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20 pinctrl-0 = <&pmx_gpio_18>;
21 pinctrl-names = "default";
22
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23 power {
24 label = "Power";
25 gpios = <&gpio0 18 1>;
dcdf14c7 26 default-state = "keep";
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27 };
28 };
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29
30 regulators {
31 compatible = "simple-bus";
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 usb_power: regulator@1 {
36 compatible = "regulator-fixed";
37 reg = <1>;
38 regulator-name = "USB Power";
39 regulator-min-microvolt = <5000000>;
40 regulator-max-microvolt = <5000000>;
41 enable-active-high;
42 regulator-always-on;
43 regulator-boot-on;
44 gpio = <&gpio0 1 0>;
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45 pinctrl-0 = <&pmx_gpio_1>;
46 pinctrl-names = "default";
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47 };
48 };
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49
50 clocks {
51 /* 25MHz reference crystal */
52 ref25: oscillator {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <25000000>;
56 };
57 };
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58
59 ir_recv: ir-receiver {
60 compatible = "gpio-ir-receiver";
61 gpios = <&gpio0 19 1>;
62 pinctrl-0 = <&pmx_gpio_19>;
63 pinctrl-names = "default";
64 };
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65
66 gpu-subsystem {
67 status = "okay";
68 };
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69};
70
71&uart0 { status = "okay"; };
1f5e6c63 72&sata0 { status = "okay"; };
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73&mdio { status = "okay"; };
74&eth { status = "okay"; };
75
76&ethphy {
77 compatible = "marvell,88e1310";
78 reg = <1>;
79};
53e9cb1d 80
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81&gpu {
82 status = "okay";
83};
84
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85&i2c0 {
86 status = "okay";
87 clock-frequency = <100000>;
88
89 si5351: clock-generator {
90 compatible = "silabs,si5351a-msop";
91 reg = <0x60>;
92 #address-cells = <1>;
93 #size-cells = <0>;
94 #clock-cells = <1>;
95
96 /* connect xtal input to 25MHz reference */
97 clocks = <&ref25>;
ba0a1ff8 98 clock-names = "xtal";
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99
100 /* connect xtal input as source of pll0 and pll1 */
101 silabs,pll-source = <0 0>, <1 0>;
102
103 clkout0 {
104 reg = <0>;
105 silabs,drive-strength = <8>;
106 silabs,multisynth-source = <0>;
107 silabs,clock-source = <0>;
108 silabs,pll-master;
109 };
110
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111 clkout2 {
112 reg = <2>;
1deb122c 113 silabs,drive-strength = <8>;
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114 silabs,multisynth-source = <1>;
115 silabs,clock-source = <0>;
1deb122c 116 silabs,pll-master;
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117 };
118 };
119};
1f5e6c63 120
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121&sdio0 {
122 status = "okay";
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123};
124
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125&spi0 {
126 status = "okay";
127
128 /* spi0.0: 4M Flash Winbond W25Q32BV */
129 spi-flash@0 {
130 compatible = "st,w25q32";
131 spi-max-frequency = <20000000>;
132 reg = <0>;
133 };
134};
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135
136&audio1 {
137 status = "okay";
138 clocks = <&gate_clk 13>, <&si5351 2>;
139 clock-names = "internal", "extclk";
140 pinctrl-0 = <&pmx_audio1_i2s1_spdifo &pmx_audio1_extclk>;
141 pinctrl-names = "default";
142};
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