Merge branch 'acpi-lpss'
[deliverable/linux.git] / arch / arm / boot / dts / dove.dtsi
CommitLineData
80a8b54b
SH
1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "marvell,dove";
5 model = "Marvell Armada 88AP510 SoC";
6
9139acd1
SH
7 aliases {
8 gpio0 = &gpio0;
9 gpio1 = &gpio1;
10 gpio2 = &gpio2;
11 };
12
138ee960 13 soc@f1000000 {
80a8b54b 14 compatible = "simple-bus";
80a8b54b
SH
15 #address-cells = <1>;
16 #size-cells = <1>;
138ee960
SH
17 interrupt-parent = <&intc>;
18
19 ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
20 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
21 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
22 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
23 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
24 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
25 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
26 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
80a8b54b 27
fd57c65c
SH
28 l2: l2-cache {
29 compatible = "marvell,tauros2-cache";
30 marvell,tauros2-cache-features = <0>;
31 };
32
138ee960
SH
33 intc: interrupt-controller {
34 compatible = "marvell,orion-intc";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 reg = <0x20204 0x04>, <0x20214 0x04>;
38 };
39
5b03df9a
SH
40 core_clk: core-clocks@d0214 {
41 compatible = "marvell,dove-core-clock";
42 reg = <0xd0214 0x4>;
43 #clock-cells = <1>;
44 };
45
46 gate_clk: clock-gating-control@d0038 {
47 compatible = "marvell,dove-gating-clock";
48 reg = <0xd0038 0x4>;
49 clocks = <&core_clk 0>;
50 #clock-cells = <1>;
51 };
52
80a8b54b
SH
53 uart0: serial@12000 {
54 compatible = "ns16550a";
55 reg = <0x12000 0x100>;
56 reg-shift = <2>;
57 interrupts = <7>;
8be7a962 58 clocks = <&core_clk 0>;
80a8b54b
SH
59 status = "disabled";
60 };
61
62 uart1: serial@12100 {
63 compatible = "ns16550a";
64 reg = <0x12100 0x100>;
65 reg-shift = <2>;
66 interrupts = <8>;
8be7a962 67 clocks = <&core_clk 0>;
80a8b54b
SH
68 status = "disabled";
69 };
70
71 uart2: serial@12200 {
72 compatible = "ns16550a";
73 reg = <0x12000 0x100>;
74 reg-shift = <2>;
75 interrupts = <9>;
8be7a962 76 clocks = <&core_clk 0>;
80a8b54b
SH
77 status = "disabled";
78 };
79
80 uart3: serial@12300 {
81 compatible = "ns16550a";
82 reg = <0x12100 0x100>;
83 reg-shift = <2>;
84 interrupts = <10>;
8be7a962 85 clocks = <&core_clk 0>;
80a8b54b
SH
86 status = "disabled";
87 };
88
80a8b54b
SH
89 gpio0: gpio@d0400 {
90 compatible = "marvell,orion-gpio";
91 #gpio-cells = <2>;
92 gpio-controller;
93 reg = <0xd0400 0x20>;
9139acd1
SH
94 ngpios = <32>;
95 interrupt-controller;
fd2704e8 96 #interrupt-cells = <2>;
80a8b54b
SH
97 interrupts = <12>, <13>, <14>, <60>;
98 };
99
100 gpio1: gpio@d0420 {
101 compatible = "marvell,orion-gpio";
102 #gpio-cells = <2>;
103 gpio-controller;
104 reg = <0xd0420 0x20>;
9139acd1
SH
105 ngpios = <32>;
106 interrupt-controller;
fd2704e8 107 #interrupt-cells = <2>;
80a8b54b
SH
108 interrupts = <61>;
109 };
110
111 gpio2: gpio@e8400 {
112 compatible = "marvell,orion-gpio";
113 #gpio-cells = <2>;
114 gpio-controller;
115 reg = <0xe8400 0x0c>;
9139acd1
SH
116 ngpios = <8>;
117 };
118
119 pinctrl: pinctrl@d0200 {
120 compatible = "marvell,dove-pinctrl";
121 reg = <0xd0200 0x10>;
db7d77e6 122 clocks = <&gate_clk 22>;
80a8b54b
SH
123 };
124
125 spi0: spi@10600 {
126 compatible = "marvell,orion-spi";
127 #address-cells = <1>;
128 #size-cells = <0>;
129 cell-index = <0>;
130 interrupts = <6>;
131 reg = <0x10600 0x28>;
5b03df9a 132 clocks = <&core_clk 0>;
80a8b54b
SH
133 status = "disabled";
134 };
135
136 spi1: spi@14600 {
137 compatible = "marvell,orion-spi";
138 #address-cells = <1>;
139 #size-cells = <0>;
140 cell-index = <1>;
141 interrupts = <5>;
142 reg = <0x14600 0x28>;
5b03df9a 143 clocks = <&core_clk 0>;
80a8b54b
SH
144 status = "disabled";
145 };
146
147 i2c0: i2c@11000 {
148 compatible = "marvell,mv64xxx-i2c";
149 reg = <0x11000 0x20>;
150 #address-cells = <1>;
151 #size-cells = <0>;
152 interrupts = <11>;
153 clock-frequency = <400000>;
154 timeout-ms = <1000>;
5b03df9a 155 clocks = <&core_clk 0>;
80a8b54b
SH
156 status = "disabled";
157 };
158
a1abcd7c
SH
159 ehci0: usb-host@50000 {
160 compatible = "marvell,orion-ehci";
161 reg = <0x50000 0x1000>;
162 interrupts = <24>;
163 clocks = <&gate_clk 0>;
164 status = "okay";
165 };
166
167 ehci1: usb-host@51000 {
168 compatible = "marvell,orion-ehci";
169 reg = <0x51000 0x1000>;
170 interrupts = <25>;
171 clocks = <&gate_clk 1>;
172 status = "okay";
173 };
174
80a8b54b
SH
175 sdio0: sdio@92000 {
176 compatible = "marvell,dove-sdhci";
177 reg = <0x92000 0x100>;
178 interrupts = <35>, <37>;
5b03df9a 179 clocks = <&gate_clk 8>;
80a8b54b
SH
180 status = "disabled";
181 };
182
183 sdio1: sdio@90000 {
184 compatible = "marvell,dove-sdhci";
185 reg = <0x90000 0x100>;
186 interrupts = <36>, <38>;
5b03df9a 187 clocks = <&gate_clk 9>;
80a8b54b
SH
188 status = "disabled";
189 };
190
191 sata0: sata@a0000 {
192 compatible = "marvell,orion-sata";
193 reg = <0xa0000 0x2400>;
194 interrupts = <62>;
5b03df9a 195 clocks = <&gate_clk 3>;
80a8b54b
SH
196 nr-ports = <1>;
197 status = "disabled";
198 };
a458926e 199
85c0c13d
JFM
200 rtc@d8500 {
201 compatible = "marvell,orion-rtc";
202 reg = <0xd8500 0x20>;
203 };
204
a458926e
SH
205 crypto: crypto@30000 {
206 compatible = "marvell,orion-crypto";
207 reg = <0x30000 0x10000>,
208 <0xc8000000 0x800>;
209 reg-names = "regs", "sram";
210 interrupts = <31>;
5b03df9a 211 clocks = <&gate_clk 15>;
a458926e
SH
212 status = "okay";
213 };
49f175b9
SH
214
215 xor0: dma-engine@60800 {
216 compatible = "marvell,orion-xor";
217 reg = <0x60800 0x100
218 0x60a00 0x100>;
219 clocks = <&gate_clk 23>;
a458926e 220 status = "okay";
49f175b9
SH
221
222 channel0 {
223 interrupts = <39>;
224 dmacap,memcpy;
225 dmacap,xor;
226 };
227
228 channel1 {
229 interrupts = <40>;
230 dmacap,memset;
231 dmacap,memcpy;
232 dmacap,xor;
233 };
234 };
235
236 xor1: dma-engine@60900 {
237 compatible = "marvell,orion-xor";
238 reg = <0x60900 0x100
239 0x60b00 0x100>;
240 clocks = <&gate_clk 24>;
241 status = "okay";
242
243 channel0 {
244 interrupts = <42>;
245 dmacap,memcpy;
246 dmacap,xor;
247 };
248
249 channel1 {
250 interrupts = <43>;
251 dmacap,memset;
252 dmacap,memcpy;
253 dmacap,xor;
254 };
a458926e 255 };
80a8b54b
SH
256 };
257};
This page took 0.098767 seconds and 5 git commands to generate.