Commit | Line | Data |
---|---|---|
80a8b54b SH |
1 | /include/ "skeleton.dtsi" |
2 | ||
6953af77 SH |
3 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) |
4 | ||
80a8b54b SH |
5 | / { |
6 | compatible = "marvell,dove"; | |
7 | model = "Marvell Armada 88AP510 SoC"; | |
0ad44659 | 8 | interrupt-parent = <&intc>; |
80a8b54b | 9 | |
9139acd1 SH |
10 | aliases { |
11 | gpio0 = &gpio0; | |
12 | gpio1 = &gpio1; | |
13 | gpio2 = &gpio2; | |
14 | }; | |
15 | ||
2d299834 SH |
16 | cpus { |
17 | #address-cells = <1>; | |
18 | #size-cells = <0>; | |
19 | ||
20 | cpu0: cpu@0 { | |
21 | compatible = "marvell,pj4a", "marvell,sheeva-v7"; | |
22 | device_type = "cpu"; | |
23 | next-level-cache = <&l2>; | |
24 | reg = <0>; | |
25 | }; | |
26 | }; | |
27 | ||
28 | l2: l2-cache { | |
29 | compatible = "marvell,tauros2-cache"; | |
30 | marvell,tauros2-cache-features = <0>; | |
31 | }; | |
32 | ||
960ee4e7 SH |
33 | mbus { |
34 | compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus"; | |
35 | #address-cells = <2>; | |
36 | #size-cells = <1>; | |
37 | controller = <&mbusc>; | |
38 | pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */ | |
39 | pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */ | |
40 | ||
41 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */ | |
42 | MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */ | |
43 | MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */ | |
44 | MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ | |
45 | MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ | |
4c3f6b86 | 46 | |
74ecaa40 SH |
47 | pcie: pcie-controller { |
48 | compatible = "marvell,dove-pcie"; | |
49 | status = "disabled"; | |
50 | device_type = "pci"; | |
51 | #address-cells = <3>; | |
52 | #size-cells = <2>; | |
53 | ||
54 | msi-parent = <&intc>; | |
55 | bus-range = <0x00 0xff>; | |
56 | ||
57 | ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000 | |
58 | 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000 | |
59 | 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */ | |
60 | 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */ | |
61 | 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ | |
62 | 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ | |
63 | ||
64 | pcie-port@0 { | |
65 | device_type = "pci"; | |
66 | status = "disabled"; | |
67 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | |
68 | reg = <0x0800 0 0 0 0>; | |
69 | clocks = <&gate_clk 4>; | |
70 | marvell,pcie-port = <0>; | |
71 | ||
72 | #address-cells = <3>; | |
73 | #size-cells = <2>; | |
74 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | |
75 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | |
76 | ||
77 | #interrupt-cells = <1>; | |
78 | interrupt-map-mask = <0 0 0 0>; | |
79 | interrupt-map = <0 0 0 0 &intc 16>; | |
80 | }; | |
81 | ||
82 | pcie-port@1 { | |
83 | device_type = "pci"; | |
84 | status = "disabled"; | |
85 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; | |
86 | reg = <0x1000 0 0 0 0>; | |
87 | clocks = <&gate_clk 5>; | |
88 | marvell,pcie-port = <1>; | |
89 | ||
90 | #address-cells = <3>; | |
91 | #size-cells = <2>; | |
92 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | |
93 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | |
94 | ||
95 | #interrupt-cells = <1>; | |
96 | interrupt-map-mask = <0 0 0 0>; | |
97 | interrupt-map = <0 0 0 0 &intc 18>; | |
98 | }; | |
99 | }; | |
100 | ||
0ad44659 SH |
101 | internal-regs { |
102 | compatible = "simple-bus"; | |
4c3f6b86 | 103 | #address-cells = <1>; |
0ad44659 SH |
104 | #size-cells = <1>; |
105 | ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */ | |
106 | 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */ | |
107 | 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */ | |
108 | 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */ | |
109 | ||
110 | mbusc: mbus-ctrl@20000 { | |
111 | compatible = "marvell,mbus-controller"; | |
112 | reg = <0x20000 0x80>, <0x800100 0x8>; | |
113 | }; | |
114 | ||
115 | timer: timer@20300 { | |
116 | compatible = "marvell,orion-timer"; | |
117 | reg = <0x20300 0x20>; | |
118 | interrupt-parent = <&bridge_intc>; | |
119 | interrupts = <1>, <2>; | |
120 | clocks = <&core_clk 0>; | |
121 | }; | |
122 | ||
123 | intc: main-interrupt-ctrl@20200 { | |
124 | compatible = "marvell,orion-intc"; | |
125 | interrupt-controller; | |
126 | #interrupt-cells = <1>; | |
127 | reg = <0x20200 0x10>, <0x20210 0x10>; | |
128 | }; | |
129 | ||
130 | bridge_intc: bridge-interrupt-ctrl@20110 { | |
131 | compatible = "marvell,orion-bridge-intc"; | |
132 | interrupt-controller; | |
133 | #interrupt-cells = <1>; | |
134 | reg = <0x20110 0x8>; | |
135 | interrupts = <0>; | |
136 | marvell,#interrupts = <5>; | |
137 | }; | |
138 | ||
139 | core_clk: core-clocks@d0214 { | |
140 | compatible = "marvell,dove-core-clock"; | |
141 | reg = <0xd0214 0x4>; | |
142 | #clock-cells = <1>; | |
143 | }; | |
144 | ||
145 | gate_clk: clock-gating-ctrl@d0038 { | |
146 | compatible = "marvell,dove-gating-clock"; | |
147 | reg = <0xd0038 0x4>; | |
148 | clocks = <&core_clk 0>; | |
149 | #clock-cells = <1>; | |
150 | }; | |
151 | ||
152 | thermal: thermal-diode@d001c { | |
153 | compatible = "marvell,dove-thermal"; | |
154 | reg = <0xd001c 0x0c>, <0xd005c 0x08>; | |
155 | }; | |
156 | ||
157 | uart0: serial@12000 { | |
158 | compatible = "ns16550a"; | |
159 | reg = <0x12000 0x100>; | |
160 | reg-shift = <2>; | |
161 | interrupts = <7>; | |
162 | clocks = <&core_clk 0>; | |
163 | status = "disabled"; | |
164 | }; | |
165 | ||
166 | uart1: serial@12100 { | |
167 | compatible = "ns16550a"; | |
168 | reg = <0x12100 0x100>; | |
169 | reg-shift = <2>; | |
170 | interrupts = <8>; | |
171 | clocks = <&core_clk 0>; | |
172 | pinctrl-0 = <&pmx_uart1>; | |
173 | pinctrl-names = "default"; | |
174 | status = "disabled"; | |
175 | }; | |
176 | ||
177 | uart2: serial@12200 { | |
178 | compatible = "ns16550a"; | |
179 | reg = <0x12000 0x100>; | |
180 | reg-shift = <2>; | |
181 | interrupts = <9>; | |
182 | clocks = <&core_clk 0>; | |
183 | status = "disabled"; | |
184 | }; | |
185 | ||
186 | uart3: serial@12300 { | |
187 | compatible = "ns16550a"; | |
188 | reg = <0x12100 0x100>; | |
189 | reg-shift = <2>; | |
190 | interrupts = <10>; | |
191 | clocks = <&core_clk 0>; | |
192 | status = "disabled"; | |
193 | }; | |
194 | ||
195 | gpio0: gpio-ctrl@d0400 { | |
196 | compatible = "marvell,orion-gpio"; | |
197 | #gpio-cells = <2>; | |
198 | gpio-controller; | |
199 | reg = <0xd0400 0x20>; | |
200 | ngpios = <32>; | |
201 | interrupt-controller; | |
202 | #interrupt-cells = <2>; | |
203 | interrupts = <12>, <13>, <14>, <60>; | |
204 | }; | |
205 | ||
206 | gpio1: gpio-ctrl@d0420 { | |
207 | compatible = "marvell,orion-gpio"; | |
208 | #gpio-cells = <2>; | |
209 | gpio-controller; | |
210 | reg = <0xd0420 0x20>; | |
211 | ngpios = <32>; | |
212 | interrupt-controller; | |
213 | #interrupt-cells = <2>; | |
214 | interrupts = <61>; | |
215 | }; | |
216 | ||
217 | gpio2: gpio-ctrl@e8400 { | |
218 | compatible = "marvell,orion-gpio"; | |
219 | #gpio-cells = <2>; | |
220 | gpio-controller; | |
221 | reg = <0xe8400 0x0c>; | |
222 | ngpios = <8>; | |
223 | }; | |
224 | ||
225 | pinctrl: pin-ctrl@d0200 { | |
226 | compatible = "marvell,dove-pinctrl"; | |
227 | reg = <0xd0200 0x10>; | |
228 | clocks = <&gate_clk 22>; | |
229 | ||
230 | pmx_gpio_0: pmx-gpio-0 { | |
231 | marvell,pins = "mpp0"; | |
232 | marvell,function = "gpio"; | |
233 | }; | |
234 | ||
235 | pmx_gpio_1: pmx-gpio-1 { | |
236 | marvell,pins = "mpp1"; | |
237 | marvell,function = "gpio"; | |
238 | }; | |
239 | ||
240 | pmx_gpio_2: pmx-gpio-2 { | |
241 | marvell,pins = "mpp2"; | |
242 | marvell,function = "gpio"; | |
243 | }; | |
244 | ||
245 | pmx_gpio_3: pmx-gpio-3 { | |
246 | marvell,pins = "mpp3"; | |
247 | marvell,function = "gpio"; | |
248 | }; | |
249 | ||
250 | pmx_gpio_4: pmx-gpio-4 { | |
251 | marvell,pins = "mpp4"; | |
252 | marvell,function = "gpio"; | |
253 | }; | |
254 | ||
255 | pmx_gpio_5: pmx-gpio-5 { | |
256 | marvell,pins = "mpp5"; | |
257 | marvell,function = "gpio"; | |
258 | }; | |
259 | ||
260 | pmx_gpio_6: pmx-gpio-6 { | |
261 | marvell,pins = "mpp6"; | |
262 | marvell,function = "gpio"; | |
263 | }; | |
264 | ||
265 | pmx_gpio_7: pmx-gpio-7 { | |
266 | marvell,pins = "mpp7"; | |
267 | marvell,function = "gpio"; | |
268 | }; | |
269 | ||
270 | pmx_gpio_8: pmx-gpio-8 { | |
271 | marvell,pins = "mpp8"; | |
272 | marvell,function = "gpio"; | |
273 | }; | |
274 | ||
275 | pmx_gpio_9: pmx-gpio-9 { | |
276 | marvell,pins = "mpp9"; | |
277 | marvell,function = "gpio"; | |
278 | }; | |
279 | ||
280 | pmx_gpio_10: pmx-gpio-10 { | |
281 | marvell,pins = "mpp10"; | |
282 | marvell,function = "gpio"; | |
283 | }; | |
284 | ||
285 | pmx_gpio_11: pmx-gpio-11 { | |
286 | marvell,pins = "mpp11"; | |
287 | marvell,function = "gpio"; | |
288 | }; | |
289 | ||
290 | pmx_gpio_12: pmx-gpio-12 { | |
291 | marvell,pins = "mpp12"; | |
292 | marvell,function = "gpio"; | |
293 | }; | |
294 | ||
295 | pmx_gpio_13: pmx-gpio-13 { | |
296 | marvell,pins = "mpp13"; | |
297 | marvell,function = "gpio"; | |
298 | }; | |
299 | ||
34ea5342 JFM |
300 | pmx_audio1_extclk: pmx-audio1-extclk { |
301 | marvell,pins = "mpp13"; | |
302 | marvell,function = "audio1"; | |
303 | }; | |
304 | ||
0ad44659 SH |
305 | pmx_gpio_14: pmx-gpio-14 { |
306 | marvell,pins = "mpp14"; | |
307 | marvell,function = "gpio"; | |
308 | }; | |
309 | ||
310 | pmx_gpio_15: pmx-gpio-15 { | |
311 | marvell,pins = "mpp15"; | |
312 | marvell,function = "gpio"; | |
313 | }; | |
314 | ||
315 | pmx_gpio_16: pmx-gpio-16 { | |
316 | marvell,pins = "mpp16"; | |
317 | marvell,function = "gpio"; | |
318 | }; | |
319 | ||
320 | pmx_gpio_17: pmx-gpio-17 { | |
321 | marvell,pins = "mpp17"; | |
322 | marvell,function = "gpio"; | |
323 | }; | |
324 | ||
325 | pmx_gpio_18: pmx-gpio-18 { | |
326 | marvell,pins = "mpp18"; | |
327 | marvell,function = "gpio"; | |
328 | }; | |
329 | ||
330 | pmx_gpio_19: pmx-gpio-19 { | |
331 | marvell,pins = "mpp19"; | |
332 | marvell,function = "gpio"; | |
333 | }; | |
334 | ||
335 | pmx_gpio_20: pmx-gpio-20 { | |
336 | marvell,pins = "mpp20"; | |
337 | marvell,function = "gpio"; | |
338 | }; | |
339 | ||
340 | pmx_gpio_21: pmx-gpio-21 { | |
341 | marvell,pins = "mpp21"; | |
342 | marvell,function = "gpio"; | |
343 | }; | |
344 | ||
345 | pmx_camera: pmx-camera { | |
346 | marvell,pins = "mpp_camera"; | |
347 | marvell,function = "camera"; | |
348 | }; | |
349 | ||
350 | pmx_camera_gpio: pmx-camera-gpio { | |
351 | marvell,pins = "mpp_camera"; | |
352 | marvell,function = "gpio"; | |
353 | }; | |
354 | ||
355 | pmx_sdio0: pmx-sdio0 { | |
356 | marvell,pins = "mpp_sdio0"; | |
357 | marvell,function = "sdio0"; | |
358 | }; | |
359 | ||
360 | pmx_sdio0_gpio: pmx-sdio0-gpio { | |
361 | marvell,pins = "mpp_sdio0"; | |
362 | marvell,function = "gpio"; | |
363 | }; | |
364 | ||
365 | pmx_sdio1: pmx-sdio1 { | |
366 | marvell,pins = "mpp_sdio1"; | |
367 | marvell,function = "sdio1"; | |
368 | }; | |
369 | ||
370 | pmx_sdio1_gpio: pmx-sdio1-gpio { | |
371 | marvell,pins = "mpp_sdio1"; | |
372 | marvell,function = "gpio"; | |
373 | }; | |
374 | ||
375 | pmx_audio1_gpio: pmx-audio1-gpio { | |
376 | marvell,pins = "mpp_audio1"; | |
377 | marvell,function = "gpio"; | |
378 | }; | |
379 | ||
34ea5342 JFM |
380 | pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { |
381 | marvell,pins = "mpp_audio1"; | |
382 | marvell,function = "i2s1/spdifo"; | |
383 | }; | |
384 | ||
0ad44659 SH |
385 | pmx_spi0: pmx-spi0 { |
386 | marvell,pins = "mpp_spi0"; | |
387 | marvell,function = "spi0"; | |
388 | }; | |
389 | ||
390 | pmx_spi0_gpio: pmx-spi0-gpio { | |
391 | marvell,pins = "mpp_spi0"; | |
392 | marvell,function = "gpio"; | |
393 | }; | |
394 | ||
395 | pmx_uart1: pmx-uart1 { | |
396 | marvell,pins = "mpp_uart1"; | |
397 | marvell,function = "uart1"; | |
398 | }; | |
399 | ||
400 | pmx_uart1_gpio: pmx-uart1-gpio { | |
401 | marvell,pins = "mpp_uart1"; | |
402 | marvell,function = "gpio"; | |
403 | }; | |
404 | ||
405 | pmx_nand: pmx-nand { | |
406 | marvell,pins = "mpp_nand"; | |
407 | marvell,function = "nand"; | |
408 | }; | |
409 | ||
410 | pmx_nand_gpo: pmx-nand-gpo { | |
411 | marvell,pins = "mpp_nand"; | |
412 | marvell,function = "gpo"; | |
413 | }; | |
414 | }; | |
415 | ||
416 | spi0: spi-ctrl@10600 { | |
417 | compatible = "marvell,orion-spi"; | |
418 | #address-cells = <1>; | |
419 | #size-cells = <0>; | |
420 | cell-index = <0>; | |
421 | interrupts = <6>; | |
422 | reg = <0x10600 0x28>; | |
423 | clocks = <&core_clk 0>; | |
424 | pinctrl-0 = <&pmx_spi0>; | |
425 | pinctrl-names = "default"; | |
426 | status = "disabled"; | |
427 | }; | |
428 | ||
429 | spi1: spi-ctrl@14600 { | |
430 | compatible = "marvell,orion-spi"; | |
431 | #address-cells = <1>; | |
432 | #size-cells = <0>; | |
433 | cell-index = <1>; | |
434 | interrupts = <5>; | |
435 | reg = <0x14600 0x28>; | |
436 | clocks = <&core_clk 0>; | |
437 | status = "disabled"; | |
438 | }; | |
439 | ||
440 | i2c0: i2c-ctrl@11000 { | |
441 | compatible = "marvell,mv64xxx-i2c"; | |
442 | reg = <0x11000 0x20>; | |
443 | #address-cells = <1>; | |
444 | #size-cells = <0>; | |
445 | interrupts = <11>; | |
446 | clock-frequency = <400000>; | |
447 | timeout-ms = <1000>; | |
448 | clocks = <&core_clk 0>; | |
449 | status = "disabled"; | |
450 | }; | |
451 | ||
452 | ehci0: usb-host@50000 { | |
453 | compatible = "marvell,orion-ehci"; | |
454 | reg = <0x50000 0x1000>; | |
455 | interrupts = <24>; | |
456 | clocks = <&gate_clk 0>; | |
457 | status = "okay"; | |
458 | }; | |
459 | ||
460 | ehci1: usb-host@51000 { | |
461 | compatible = "marvell,orion-ehci"; | |
462 | reg = <0x51000 0x1000>; | |
463 | interrupts = <25>; | |
464 | clocks = <&gate_clk 1>; | |
465 | status = "okay"; | |
466 | }; | |
467 | ||
468 | sdio0: sdio-host@92000 { | |
469 | compatible = "marvell,dove-sdhci"; | |
470 | reg = <0x92000 0x100>; | |
471 | interrupts = <35>, <37>; | |
472 | clocks = <&gate_clk 8>; | |
473 | pinctrl-0 = <&pmx_sdio0>; | |
474 | pinctrl-names = "default"; | |
475 | status = "disabled"; | |
476 | }; | |
477 | ||
478 | sdio1: sdio-host@90000 { | |
479 | compatible = "marvell,dove-sdhci"; | |
480 | reg = <0x90000 0x100>; | |
481 | interrupts = <36>, <38>; | |
482 | clocks = <&gate_clk 9>; | |
483 | pinctrl-0 = <&pmx_sdio1>; | |
484 | pinctrl-names = "default"; | |
485 | status = "disabled"; | |
486 | }; | |
487 | ||
488 | sata0: sata-host@a0000 { | |
489 | compatible = "marvell,orion-sata"; | |
490 | reg = <0xa0000 0x2400>; | |
491 | interrupts = <62>; | |
492 | clocks = <&gate_clk 3>; | |
493 | nr-ports = <1>; | |
494 | status = "disabled"; | |
495 | }; | |
496 | ||
497 | rtc: real-time-clock@d8500 { | |
498 | compatible = "marvell,orion-rtc"; | |
499 | reg = <0xd8500 0x20>; | |
500 | }; | |
501 | ||
502 | crypto: crypto-engine@30000 { | |
503 | compatible = "marvell,orion-crypto"; | |
504 | reg = <0x30000 0x10000>, | |
505 | <0xffffe000 0x800>; | |
506 | reg-names = "regs", "sram"; | |
507 | interrupts = <31>; | |
508 | clocks = <&gate_clk 15>; | |
509 | status = "okay"; | |
510 | }; | |
511 | ||
512 | xor0: dma-engine@60800 { | |
513 | compatible = "marvell,orion-xor"; | |
514 | reg = <0x60800 0x100 | |
515 | 0x60a00 0x100>; | |
516 | clocks = <&gate_clk 23>; | |
517 | status = "okay"; | |
518 | ||
519 | channel0 { | |
520 | interrupts = <39>; | |
521 | dmacap,memcpy; | |
522 | dmacap,xor; | |
523 | }; | |
524 | ||
525 | channel1 { | |
526 | interrupts = <40>; | |
527 | dmacap,memcpy; | |
528 | dmacap,xor; | |
529 | }; | |
530 | }; | |
531 | ||
532 | xor1: dma-engine@60900 { | |
533 | compatible = "marvell,orion-xor"; | |
534 | reg = <0x60900 0x100 | |
535 | 0x60b00 0x100>; | |
536 | clocks = <&gate_clk 24>; | |
537 | status = "okay"; | |
538 | ||
539 | channel0 { | |
540 | interrupts = <42>; | |
541 | dmacap,memcpy; | |
542 | dmacap,xor; | |
543 | }; | |
544 | ||
545 | channel1 { | |
546 | interrupts = <43>; | |
547 | dmacap,memcpy; | |
548 | dmacap,xor; | |
549 | }; | |
550 | }; | |
551 | ||
552 | mdio: mdio-bus@72004 { | |
553 | compatible = "marvell,orion-mdio"; | |
554 | #address-cells = <1>; | |
555 | #size-cells = <0>; | |
556 | reg = <0x72004 0x84>; | |
557 | interrupts = <30>; | |
558 | clocks = <&gate_clk 2>; | |
559 | status = "disabled"; | |
560 | ||
561 | ethphy: ethernet-phy { | |
0ad44659 SH |
562 | /* set phy address in board file */ |
563 | }; | |
564 | }; | |
565 | ||
566 | eth: ethernet-ctrl@72000 { | |
567 | compatible = "marvell,orion-eth"; | |
568 | #address-cells = <1>; | |
569 | #size-cells = <0>; | |
570 | reg = <0x72000 0x4000>; | |
571 | clocks = <&gate_clk 2>; | |
572 | marvell,tx-checksum-limit = <1600>; | |
573 | status = "disabled"; | |
574 | ||
575 | ethernet-port@0 { | |
576 | device_type = "network"; | |
577 | compatible = "marvell,orion-eth-port"; | |
578 | reg = <0>; | |
579 | interrupts = <29>; | |
580 | /* overwrite MAC address in bootloader */ | |
581 | local-mac-address = [00 00 00 00 00 00]; | |
582 | phy-handle = <ðphy>; | |
583 | }; | |
4c3f6b86 | 584 | }; |
080972aa JFM |
585 | |
586 | audio0: audio-controller@b0000 { | |
587 | compatible = "marvell,dove-audio"; | |
588 | reg = <0xb0000 0x2210>; | |
589 | interrupts = <19>, <20>; | |
590 | clocks = <&gate_clk 12>; | |
591 | clock-names = "internal"; | |
592 | status = "disabled"; | |
593 | }; | |
594 | ||
595 | audio1: audio-controller@b4000 { | |
596 | compatible = "marvell,dove-audio"; | |
597 | reg = <0xb4000 0x2210>; | |
598 | interrupts = <21>, <22>; | |
599 | clocks = <&gate_clk 13>; | |
600 | clock-names = "internal"; | |
601 | status = "disabled"; | |
602 | }; | |
4c3f6b86 | 603 | }; |
80a8b54b SH |
604 | }; |
605 | }; |