projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 80a8b54b SH |
1 | /include/ "skeleton.dtsi" |
| 2 | ||
| 6953af77 SH |
3 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) |
| 4 | ||
| 80a8b54b SH |
5 | / { |
| 6 | compatible = "marvell,dove"; | |
| 7 | model = "Marvell Armada 88AP510 SoC"; | |
| 0ad44659 | 8 | interrupt-parent = <&intc>; |
| 80a8b54b | 9 | |
| 9139acd1 SH |
10 | aliases { |
| 11 | gpio0 = &gpio0; | |
| 12 | gpio1 = &gpio1; | |
| 13 | gpio2 = &gpio2; | |
| 14 | }; | |
| 15 | ||
| 2d299834 SH |
16 | cpus { |
| 17 | #address-cells = <1>; | |
| 18 | #size-cells = <0>; | |
| 19 | ||
| 20 | cpu0: cpu@0 { | |
| 21 | compatible = "marvell,pj4a", "marvell,sheeva-v7"; | |
| 22 | device_type = "cpu"; | |
| 23 | next-level-cache = <&l2>; | |
| 24 | reg = <0>; | |
| 25 | }; | |
| 26 | }; | |
| 27 | ||
| 28 | l2: l2-cache { | |
| 29 | compatible = "marvell,tauros2-cache"; | |
| 30 | marvell,tauros2-cache-features = <0>; | |
| 31 | }; | |
| 32 | ||
| 960ee4e7 SH |
33 | mbus { |
| 34 | compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus"; | |
| 35 | #address-cells = <2>; | |
| 36 | #size-cells = <1>; | |
| 37 | controller = <&mbusc>; | |
| 38 | pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */ | |
| 39 | pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */ | |
| 40 | ||
| 41 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */ | |
| 42 | MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */ | |
| 43 | MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */ | |
| 44 | MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ | |
| 45 | MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ | |
| 4c3f6b86 | 46 | |
| 74ecaa40 SH |
47 | pcie: pcie-controller { |
| 48 | compatible = "marvell,dove-pcie"; | |
| 49 | status = "disabled"; | |
| 50 | device_type = "pci"; | |
| 51 | #address-cells = <3>; | |
| 52 | #size-cells = <2>; | |
| 53 | ||
| 54 | msi-parent = <&intc>; | |
| 55 | bus-range = <0x00 0xff>; | |
| 56 | ||
| 57 | ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000 | |
| 58 | 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000 | |
| 59 | 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */ | |
| 60 | 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */ | |
| 61 | 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ | |
| 62 | 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ | |
| 63 | ||
| 64 | pcie-port@0 { | |
| 65 | device_type = "pci"; | |
| 66 | status = "disabled"; | |
| 67 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | |
| 68 | reg = <0x0800 0 0 0 0>; | |
| 69 | clocks = <&gate_clk 4>; | |
| 70 | marvell,pcie-port = <0>; | |
| 71 | ||
| 72 | #address-cells = <3>; | |
| 73 | #size-cells = <2>; | |
| 74 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | |
| 75 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | |
| 76 | ||
| 77 | #interrupt-cells = <1>; | |
| 78 | interrupt-map-mask = <0 0 0 0>; | |
| 79 | interrupt-map = <0 0 0 0 &intc 16>; | |
| 80 | }; | |
| 81 | ||
| 82 | pcie-port@1 { | |
| 83 | device_type = "pci"; | |
| 84 | status = "disabled"; | |
| 85 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; | |
| 86 | reg = <0x1000 0 0 0 0>; | |
| 87 | clocks = <&gate_clk 5>; | |
| 88 | marvell,pcie-port = <1>; | |
| 89 | ||
| 90 | #address-cells = <3>; | |
| 91 | #size-cells = <2>; | |
| 92 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | |
| 93 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | |
| 94 | ||
| 95 | #interrupt-cells = <1>; | |
| 96 | interrupt-map-mask = <0 0 0 0>; | |
| 97 | interrupt-map = <0 0 0 0 &intc 18>; | |
| 98 | }; | |
| 99 | }; | |
| 100 | ||
| 0ad44659 SH |
101 | internal-regs { |
| 102 | compatible = "simple-bus"; | |
| 4c3f6b86 | 103 | #address-cells = <1>; |
| 0ad44659 SH |
104 | #size-cells = <1>; |
| 105 | ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */ | |
| 106 | 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */ | |
| 107 | 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */ | |
| 108 | 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */ | |
| 109 | ||
| b31b3211 JC |
110 | spi0: spi-ctrl@10600 { |
| 111 | compatible = "marvell,orion-spi"; | |
| 112 | #address-cells = <1>; | |
| 113 | #size-cells = <0>; | |
| 114 | cell-index = <0>; | |
| 115 | interrupts = <6>; | |
| 116 | reg = <0x10600 0x28>; | |
| 0ad44659 | 117 | clocks = <&core_clk 0>; |
| b31b3211 JC |
118 | pinctrl-0 = <&pmx_spi0>; |
| 119 | pinctrl-names = "default"; | |
| 120 | status = "disabled"; | |
| 0ad44659 SH |
121 | }; |
| 122 | ||
| b31b3211 JC |
123 | i2c0: i2c-ctrl@11000 { |
| 124 | compatible = "marvell,mv64xxx-i2c"; | |
| 125 | reg = <0x11000 0x20>; | |
| 126 | #address-cells = <1>; | |
| 127 | #size-cells = <0>; | |
| 128 | interrupts = <11>; | |
| 129 | clock-frequency = <400000>; | |
| 130 | timeout-ms = <1000>; | |
| 0ad44659 | 131 | clocks = <&core_clk 0>; |
| b31b3211 | 132 | status = "disabled"; |
| 0ad44659 SH |
133 | }; |
| 134 | ||
| 135 | uart0: serial@12000 { | |
| 136 | compatible = "ns16550a"; | |
| 137 | reg = <0x12000 0x100>; | |
| 138 | reg-shift = <2>; | |
| 139 | interrupts = <7>; | |
| 140 | clocks = <&core_clk 0>; | |
| 141 | status = "disabled"; | |
| 142 | }; | |
| 143 | ||
| 144 | uart1: serial@12100 { | |
| 145 | compatible = "ns16550a"; | |
| 146 | reg = <0x12100 0x100>; | |
| 147 | reg-shift = <2>; | |
| 148 | interrupts = <8>; | |
| 149 | clocks = <&core_clk 0>; | |
| 150 | pinctrl-0 = <&pmx_uart1>; | |
| 151 | pinctrl-names = "default"; | |
| 152 | status = "disabled"; | |
| 153 | }; | |
| 154 | ||
| 155 | uart2: serial@12200 { | |
| 156 | compatible = "ns16550a"; | |
| 157 | reg = <0x12000 0x100>; | |
| 158 | reg-shift = <2>; | |
| 159 | interrupts = <9>; | |
| 160 | clocks = <&core_clk 0>; | |
| 161 | status = "disabled"; | |
| 162 | }; | |
| 163 | ||
| 164 | uart3: serial@12300 { | |
| 165 | compatible = "ns16550a"; | |
| 166 | reg = <0x12100 0x100>; | |
| 167 | reg-shift = <2>; | |
| 168 | interrupts = <10>; | |
| 169 | clocks = <&core_clk 0>; | |
| 170 | status = "disabled"; | |
| 171 | }; | |
| 172 | ||
| b31b3211 JC |
173 | spi1: spi-ctrl@14600 { |
| 174 | compatible = "marvell,orion-spi"; | |
| 175 | #address-cells = <1>; | |
| 176 | #size-cells = <0>; | |
| 177 | cell-index = <1>; | |
| 178 | interrupts = <5>; | |
| 179 | reg = <0x14600 0x28>; | |
| 180 | clocks = <&core_clk 0>; | |
| 181 | status = "disabled"; | |
| 182 | }; | |
| 183 | ||
| 184 | mbusc: mbus-ctrl@20000 { | |
| 185 | compatible = "marvell,mbus-controller"; | |
| 186 | reg = <0x20000 0x80>, <0x800100 0x8>; | |
| 187 | }; | |
| 188 | ||
| 189 | bridge_intc: bridge-interrupt-ctrl@20110 { | |
| 190 | compatible = "marvell,orion-bridge-intc"; | |
| 0ad44659 | 191 | interrupt-controller; |
| b31b3211 JC |
192 | #interrupt-cells = <1>; |
| 193 | reg = <0x20110 0x8>; | |
| 194 | interrupts = <0>; | |
| 195 | marvell,#interrupts = <5>; | |
| 0ad44659 SH |
196 | }; |
| 197 | ||
| b31b3211 JC |
198 | intc: main-interrupt-ctrl@20200 { |
| 199 | compatible = "marvell,orion-intc"; | |
| 0ad44659 | 200 | interrupt-controller; |
| b31b3211 JC |
201 | #interrupt-cells = <1>; |
| 202 | reg = <0x20200 0x10>, <0x20210 0x10>; | |
| 0ad44659 SH |
203 | }; |
| 204 | ||
| b31b3211 JC |
205 | timer: timer@20300 { |
| 206 | compatible = "marvell,orion-timer"; | |
| 207 | reg = <0x20300 0x20>; | |
| 208 | interrupt-parent = <&bridge_intc>; | |
| 209 | interrupts = <1>, <2>; | |
| 210 | clocks = <&core_clk 0>; | |
| 211 | }; | |
| 212 | ||
| 213 | crypto: crypto-engine@30000 { | |
| 214 | compatible = "marvell,orion-crypto"; | |
| 215 | reg = <0x30000 0x10000>, | |
| 216 | <0xffffe000 0x800>; | |
| 217 | reg-names = "regs", "sram"; | |
| 218 | interrupts = <31>; | |
| 219 | clocks = <&gate_clk 15>; | |
| 220 | status = "okay"; | |
| 221 | }; | |
| 222 | ||
| 223 | ehci0: usb-host@50000 { | |
| 224 | compatible = "marvell,orion-ehci"; | |
| 225 | reg = <0x50000 0x1000>; | |
| 226 | interrupts = <24>; | |
| 227 | clocks = <&gate_clk 0>; | |
| 228 | status = "okay"; | |
| 229 | }; | |
| 230 | ||
| 231 | ehci1: usb-host@51000 { | |
| 232 | compatible = "marvell,orion-ehci"; | |
| 233 | reg = <0x51000 0x1000>; | |
| 234 | interrupts = <25>; | |
| 235 | clocks = <&gate_clk 1>; | |
| 236 | status = "okay"; | |
| 237 | }; | |
| 238 | ||
| 239 | xor0: dma-engine@60800 { | |
| 240 | compatible = "marvell,orion-xor"; | |
| 241 | reg = <0x60800 0x100 | |
| 242 | 0x60a00 0x100>; | |
| 243 | clocks = <&gate_clk 23>; | |
| 244 | status = "okay"; | |
| 245 | ||
| 246 | channel0 { | |
| 247 | interrupts = <39>; | |
| 248 | dmacap,memcpy; | |
| 249 | dmacap,xor; | |
| 250 | }; | |
| 251 | ||
| 252 | channel1 { | |
| 253 | interrupts = <40>; | |
| 254 | dmacap,memcpy; | |
| 255 | dmacap,xor; | |
| 256 | }; | |
| 257 | }; | |
| 258 | ||
| 259 | xor1: dma-engine@60900 { | |
| 260 | compatible = "marvell,orion-xor"; | |
| 261 | reg = <0x60900 0x100 | |
| 262 | 0x60b00 0x100>; | |
| 263 | clocks = <&gate_clk 24>; | |
| 264 | status = "okay"; | |
| 265 | ||
| 266 | channel0 { | |
| 267 | interrupts = <42>; | |
| 268 | dmacap,memcpy; | |
| 269 | dmacap,xor; | |
| 270 | }; | |
| 271 | ||
| 272 | channel1 { | |
| 273 | interrupts = <43>; | |
| 274 | dmacap,memcpy; | |
| 275 | dmacap,xor; | |
| 276 | }; | |
| 277 | }; | |
| 278 | ||
| 279 | sdio1: sdio-host@90000 { | |
| 280 | compatible = "marvell,dove-sdhci"; | |
| 281 | reg = <0x90000 0x100>; | |
| 282 | interrupts = <36>, <38>; | |
| 283 | clocks = <&gate_clk 9>; | |
| 284 | pinctrl-0 = <&pmx_sdio1>; | |
| 285 | pinctrl-names = "default"; | |
| 286 | status = "disabled"; | |
| 287 | }; | |
| 288 | ||
| 289 | eth: ethernet-ctrl@72000 { | |
| 290 | compatible = "marvell,orion-eth"; | |
| 291 | #address-cells = <1>; | |
| 292 | #size-cells = <0>; | |
| 293 | reg = <0x72000 0x4000>; | |
| 294 | clocks = <&gate_clk 2>; | |
| 295 | marvell,tx-checksum-limit = <1600>; | |
| 296 | status = "disabled"; | |
| 297 | ||
| 298 | ethernet-port@0 { | |
| b31b3211 JC |
299 | compatible = "marvell,orion-eth-port"; |
| 300 | reg = <0>; | |
| 301 | interrupts = <29>; | |
| 302 | /* overwrite MAC address in bootloader */ | |
| 303 | local-mac-address = [00 00 00 00 00 00]; | |
| 304 | phy-handle = <ðphy>; | |
| 305 | }; | |
| 306 | }; | |
| 307 | ||
| 308 | mdio: mdio-bus@72004 { | |
| 309 | compatible = "marvell,orion-mdio"; | |
| 310 | #address-cells = <1>; | |
| 311 | #size-cells = <0>; | |
| 312 | reg = <0x72004 0x84>; | |
| 313 | interrupts = <30>; | |
| 314 | clocks = <&gate_clk 2>; | |
| 315 | status = "disabled"; | |
| 316 | ||
| 317 | ethphy: ethernet-phy { | |
| b31b3211 JC |
318 | /* set phy address in board file */ |
| 319 | }; | |
| 320 | }; | |
| 321 | ||
| 322 | sdio0: sdio-host@92000 { | |
| 323 | compatible = "marvell,dove-sdhci"; | |
| 324 | reg = <0x92000 0x100>; | |
| 325 | interrupts = <35>, <37>; | |
| 326 | clocks = <&gate_clk 8>; | |
| 327 | pinctrl-0 = <&pmx_sdio0>; | |
| 328 | pinctrl-names = "default"; | |
| 329 | status = "disabled"; | |
| 330 | }; | |
| 331 | ||
| 332 | sata0: sata-host@a0000 { | |
| 333 | compatible = "marvell,orion-sata"; | |
| 334 | reg = <0xa0000 0x2400>; | |
| 335 | interrupts = <62>; | |
| 336 | clocks = <&gate_clk 3>; | |
| 0ad82cd8 AL |
337 | phys = <&sata_phy0>; |
| 338 | phy-names = "port0"; | |
| b31b3211 JC |
339 | nr-ports = <1>; |
| 340 | status = "disabled"; | |
| 341 | }; | |
| 342 | ||
| 0ad82cd8 AL |
343 | sata_phy0: sata-phy@a2000 { |
| 344 | compatible = "marvell,mvebu-sata-phy"; | |
| 345 | reg = <0xa2000 0x0334>; | |
| 346 | clocks = <&gate_clk 3>; | |
| 347 | clock-names = "sata"; | |
| 348 | #phy-cells = <0>; | |
| 349 | status = "ok"; | |
| 350 | }; | |
| 351 | ||
| b31b3211 JC |
352 | audio0: audio-controller@b0000 { |
| 353 | compatible = "marvell,dove-audio"; | |
| 354 | reg = <0xb0000 0x2210>; | |
| 355 | interrupts = <19>, <20>; | |
| 356 | clocks = <&gate_clk 12>; | |
| 357 | clock-names = "internal"; | |
| 358 | status = "disabled"; | |
| 359 | }; | |
| 360 | ||
| 361 | audio1: audio-controller@b4000 { | |
| 362 | compatible = "marvell,dove-audio"; | |
| 363 | reg = <0xb4000 0x2210>; | |
| 364 | interrupts = <21>, <22>; | |
| 365 | clocks = <&gate_clk 13>; | |
| 366 | clock-names = "internal"; | |
| 367 | status = "disabled"; | |
| 368 | }; | |
| 369 | ||
| 370 | thermal: thermal-diode@d001c { | |
| 371 | compatible = "marvell,dove-thermal"; | |
| 372 | reg = <0xd001c 0x0c>, <0xd005c 0x08>; | |
| 373 | }; | |
| 374 | ||
| 375 | gate_clk: clock-gating-ctrl@d0038 { | |
| 376 | compatible = "marvell,dove-gating-clock"; | |
| 377 | reg = <0xd0038 0x4>; | |
| 378 | clocks = <&core_clk 0>; | |
| 379 | #clock-cells = <1>; | |
| 380 | }; | |
| 381 | ||
| 0ad44659 SH |
382 | pinctrl: pin-ctrl@d0200 { |
| 383 | compatible = "marvell,dove-pinctrl"; | |
| 384 | reg = <0xd0200 0x10>; | |
| 385 | clocks = <&gate_clk 22>; | |
| 386 | ||
| 387 | pmx_gpio_0: pmx-gpio-0 { | |
| 388 | marvell,pins = "mpp0"; | |
| 389 | marvell,function = "gpio"; | |
| 390 | }; | |
| 391 | ||
| 392 | pmx_gpio_1: pmx-gpio-1 { | |
| 393 | marvell,pins = "mpp1"; | |
| 394 | marvell,function = "gpio"; | |
| 395 | }; | |
| 396 | ||
| 397 | pmx_gpio_2: pmx-gpio-2 { | |
| 398 | marvell,pins = "mpp2"; | |
| 399 | marvell,function = "gpio"; | |
| 400 | }; | |
| 401 | ||
| 402 | pmx_gpio_3: pmx-gpio-3 { | |
| 403 | marvell,pins = "mpp3"; | |
| 404 | marvell,function = "gpio"; | |
| 405 | }; | |
| 406 | ||
| 407 | pmx_gpio_4: pmx-gpio-4 { | |
| 408 | marvell,pins = "mpp4"; | |
| 409 | marvell,function = "gpio"; | |
| 410 | }; | |
| 411 | ||
| 412 | pmx_gpio_5: pmx-gpio-5 { | |
| 413 | marvell,pins = "mpp5"; | |
| 414 | marvell,function = "gpio"; | |
| 415 | }; | |
| 416 | ||
| 417 | pmx_gpio_6: pmx-gpio-6 { | |
| 418 | marvell,pins = "mpp6"; | |
| 419 | marvell,function = "gpio"; | |
| 420 | }; | |
| 421 | ||
| 422 | pmx_gpio_7: pmx-gpio-7 { | |
| 423 | marvell,pins = "mpp7"; | |
| 424 | marvell,function = "gpio"; | |
| 425 | }; | |
| 426 | ||
| 427 | pmx_gpio_8: pmx-gpio-8 { | |
| 428 | marvell,pins = "mpp8"; | |
| 429 | marvell,function = "gpio"; | |
| 430 | }; | |
| 431 | ||
| 432 | pmx_gpio_9: pmx-gpio-9 { | |
| 433 | marvell,pins = "mpp9"; | |
| 434 | marvell,function = "gpio"; | |
| 435 | }; | |
| 436 | ||
| 437 | pmx_gpio_10: pmx-gpio-10 { | |
| 438 | marvell,pins = "mpp10"; | |
| 439 | marvell,function = "gpio"; | |
| 440 | }; | |
| 441 | ||
| 442 | pmx_gpio_11: pmx-gpio-11 { | |
| 443 | marvell,pins = "mpp11"; | |
| 444 | marvell,function = "gpio"; | |
| 445 | }; | |
| 446 | ||
| 447 | pmx_gpio_12: pmx-gpio-12 { | |
| 448 | marvell,pins = "mpp12"; | |
| 449 | marvell,function = "gpio"; | |
| 450 | }; | |
| 451 | ||
| 452 | pmx_gpio_13: pmx-gpio-13 { | |
| 453 | marvell,pins = "mpp13"; | |
| 454 | marvell,function = "gpio"; | |
| 455 | }; | |
| 456 | ||
| 34ea5342 JFM |
457 | pmx_audio1_extclk: pmx-audio1-extclk { |
| 458 | marvell,pins = "mpp13"; | |
| 459 | marvell,function = "audio1"; | |
| 460 | }; | |
| 461 | ||
| 0ad44659 SH |
462 | pmx_gpio_14: pmx-gpio-14 { |
| 463 | marvell,pins = "mpp14"; | |
| 464 | marvell,function = "gpio"; | |
| 465 | }; | |
| 466 | ||
| 467 | pmx_gpio_15: pmx-gpio-15 { | |
| 468 | marvell,pins = "mpp15"; | |
| 469 | marvell,function = "gpio"; | |
| 470 | }; | |
| 471 | ||
| 472 | pmx_gpio_16: pmx-gpio-16 { | |
| 473 | marvell,pins = "mpp16"; | |
| 474 | marvell,function = "gpio"; | |
| 475 | }; | |
| 476 | ||
| 477 | pmx_gpio_17: pmx-gpio-17 { | |
| 478 | marvell,pins = "mpp17"; | |
| 479 | marvell,function = "gpio"; | |
| 480 | }; | |
| 481 | ||
| 482 | pmx_gpio_18: pmx-gpio-18 { | |
| 483 | marvell,pins = "mpp18"; | |
| 484 | marvell,function = "gpio"; | |
| 485 | }; | |
| 486 | ||
| 487 | pmx_gpio_19: pmx-gpio-19 { | |
| 488 | marvell,pins = "mpp19"; | |
| 489 | marvell,function = "gpio"; | |
| 490 | }; | |
| 491 | ||
| 492 | pmx_gpio_20: pmx-gpio-20 { | |
| 493 | marvell,pins = "mpp20"; | |
| 494 | marvell,function = "gpio"; | |
| 495 | }; | |
| 496 | ||
| 497 | pmx_gpio_21: pmx-gpio-21 { | |
| 498 | marvell,pins = "mpp21"; | |
| 499 | marvell,function = "gpio"; | |
| 500 | }; | |
| 501 | ||
| 502 | pmx_camera: pmx-camera { | |
| 503 | marvell,pins = "mpp_camera"; | |
| 504 | marvell,function = "camera"; | |
| 505 | }; | |
| 506 | ||
| 507 | pmx_camera_gpio: pmx-camera-gpio { | |
| 508 | marvell,pins = "mpp_camera"; | |
| 509 | marvell,function = "gpio"; | |
| 510 | }; | |
| 511 | ||
| 512 | pmx_sdio0: pmx-sdio0 { | |
| 513 | marvell,pins = "mpp_sdio0"; | |
| 514 | marvell,function = "sdio0"; | |
| 515 | }; | |
| 516 | ||
| 517 | pmx_sdio0_gpio: pmx-sdio0-gpio { | |
| 518 | marvell,pins = "mpp_sdio0"; | |
| 519 | marvell,function = "gpio"; | |
| 520 | }; | |
| 521 | ||
| 522 | pmx_sdio1: pmx-sdio1 { | |
| 523 | marvell,pins = "mpp_sdio1"; | |
| 524 | marvell,function = "sdio1"; | |
| 525 | }; | |
| 526 | ||
| 527 | pmx_sdio1_gpio: pmx-sdio1-gpio { | |
| 528 | marvell,pins = "mpp_sdio1"; | |
| 529 | marvell,function = "gpio"; | |
| 530 | }; | |
| 531 | ||
| 532 | pmx_audio1_gpio: pmx-audio1-gpio { | |
| 533 | marvell,pins = "mpp_audio1"; | |
| 534 | marvell,function = "gpio"; | |
| 535 | }; | |
| 536 | ||
| 34ea5342 JFM |
537 | pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { |
| 538 | marvell,pins = "mpp_audio1"; | |
| 539 | marvell,function = "i2s1/spdifo"; | |
| 540 | }; | |
| 541 | ||
| 0ad44659 SH |
542 | pmx_spi0: pmx-spi0 { |
| 543 | marvell,pins = "mpp_spi0"; | |
| 544 | marvell,function = "spi0"; | |
| 545 | }; | |
| 546 | ||
| 547 | pmx_spi0_gpio: pmx-spi0-gpio { | |
| 548 | marvell,pins = "mpp_spi0"; | |
| 549 | marvell,function = "gpio"; | |
| 550 | }; | |
| 551 | ||
| 552 | pmx_uart1: pmx-uart1 { | |
| 553 | marvell,pins = "mpp_uart1"; | |
| 554 | marvell,function = "uart1"; | |
| 555 | }; | |
| 556 | ||
| 557 | pmx_uart1_gpio: pmx-uart1-gpio { | |
| 558 | marvell,pins = "mpp_uart1"; | |
| 559 | marvell,function = "gpio"; | |
| 560 | }; | |
| 561 | ||
| 562 | pmx_nand: pmx-nand { | |
| 563 | marvell,pins = "mpp_nand"; | |
| 564 | marvell,function = "nand"; | |
| 565 | }; | |
| 566 | ||
| 567 | pmx_nand_gpo: pmx-nand-gpo { | |
| 568 | marvell,pins = "mpp_nand"; | |
| 569 | marvell,function = "gpo"; | |
| 570 | }; | |
| 571 | }; | |
| 572 | ||
| b31b3211 JC |
573 | core_clk: core-clocks@d0214 { |
| 574 | compatible = "marvell,dove-core-clock"; | |
| 575 | reg = <0xd0214 0x4>; | |
| 576 | #clock-cells = <1>; | |
| 0ad44659 SH |
577 | }; |
| 578 | ||
| b31b3211 JC |
579 | gpio0: gpio-ctrl@d0400 { |
| 580 | compatible = "marvell,orion-gpio"; | |
| 581 | #gpio-cells = <2>; | |
| 582 | gpio-controller; | |
| 583 | reg = <0xd0400 0x20>; | |
| 584 | ngpios = <32>; | |
| 585 | interrupt-controller; | |
| 586 | #interrupt-cells = <2>; | |
| 587 | interrupts = <12>, <13>, <14>, <60>; | |
| 0ad44659 SH |
588 | }; |
| 589 | ||
| b31b3211 JC |
590 | gpio1: gpio-ctrl@d0420 { |
| 591 | compatible = "marvell,orion-gpio"; | |
| 592 | #gpio-cells = <2>; | |
| 593 | gpio-controller; | |
| 594 | reg = <0xd0420 0x20>; | |
| 595 | ngpios = <32>; | |
| 596 | interrupt-controller; | |
| 597 | #interrupt-cells = <2>; | |
| 598 | interrupts = <61>; | |
| 0ad44659 SH |
599 | }; |
| 600 | ||
| 601 | rtc: real-time-clock@d8500 { | |
| 602 | compatible = "marvell,orion-rtc"; | |
| 603 | reg = <0xd8500 0x20>; | |
| 604 | }; | |
| 605 | ||
| b31b3211 JC |
606 | gpio2: gpio-ctrl@e8400 { |
| 607 | compatible = "marvell,orion-gpio"; | |
| 608 | #gpio-cells = <2>; | |
| 609 | gpio-controller; | |
| 610 | reg = <0xe8400 0x0c>; | |
| 611 | ngpios = <8>; | |
| 080972aa | 612 | }; |
| 4c3f6b86 | 613 | }; |
| 80a8b54b SH |
614 | }; |
| 615 | }; |