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a4240d3a NM |
1 | /* |
2 | * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | #include "dra72-evm-common.dtsi" | |
9 | #include <dt-bindings/net/ti-dp83867.h> | |
10 | ||
11 | / { | |
12 | model = "TI DRA722 Rev C EVM"; | |
13 | ||
14 | memory { | |
15 | device_type = "memory"; | |
16 | reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ | |
17 | }; | |
18 | }; | |
19 | ||
20 | &tps65917_regulators { | |
21 | ldo2_reg: ldo2 { | |
22 | /* LDO2_OUT --> VDDA_1V8_PHY2 */ | |
23 | regulator-name = "ldo2"; | |
24 | regulator-min-microvolt = <1800000>; | |
25 | regulator-max-microvolt = <1800000>; | |
26 | regulator-always-on; | |
27 | regulator-boot-on; | |
28 | }; | |
29 | }; | |
30 | ||
31 | &hdmi { | |
32 | vdda-supply = <&ldo2_reg>; | |
33 | }; | |
34 | ||
35 | &pcf_gpio_21 { | |
36 | interrupt-parent = <&gpio3>; | |
37 | interrupts = <30 IRQ_TYPE_EDGE_FALLING>; | |
38 | }; | |
39 | ||
40 | &mac { | |
41 | mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, | |
42 | <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ | |
43 | <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ | |
44 | dual_emac; | |
45 | }; | |
46 | ||
47 | &cpsw_emac0 { | |
48 | phy_id = <&davinci_mdio>, <2>; | |
49 | phy-mode = "rgmii-id"; | |
50 | dual_emac_res_vlan = <1>; | |
51 | }; | |
52 | ||
53 | &cpsw_emac1 { | |
54 | phy_id = <&davinci_mdio>, <3>; | |
55 | phy-mode = "rgmii-id"; | |
56 | dual_emac_res_vlan = <2>; | |
57 | }; | |
58 | ||
59 | &davinci_mdio { | |
60 | dp83867_0: ethernet-phy@2 { | |
61 | reg = <2>; | |
62 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; | |
63 | ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>; | |
64 | ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; | |
65 | }; | |
66 | ||
67 | dp83867_1: ethernet-phy@3 { | |
68 | reg = <3>; | |
69 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; | |
70 | ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>; | |
71 | ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; | |
72 | }; | |
73 | }; |