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38b248db RN |
1 | /* |
2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | /dts-v1/; | |
9 | ||
10 | #include "dra72x.dtsi" | |
f56de327 | 11 | #include <dt-bindings/gpio/gpio.h> |
38b248db RN |
12 | |
13 | / { | |
14 | model = "TI DRA722"; | |
15 | compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; | |
16 | ||
17 | memory { | |
18 | device_type = "memory"; | |
19 | reg = <0x80000000 0x40000000>; /* 1024 MB */ | |
20 | }; | |
5b434d7e NM |
21 | |
22 | evm_3v3: fixedregulator-evm_3v3 { | |
23 | compatible = "regulator-fixed"; | |
24 | regulator-name = "evm_3v3"; | |
25 | regulator-min-microvolt = <3300000>; | |
26 | regulator-max-microvolt = <3300000>; | |
27 | }; | |
f56de327 RQ |
28 | |
29 | extcon_usb1: extcon_usb1 { | |
30 | compatible = "linux,extcon-usb-gpio"; | |
31 | id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; | |
32 | }; | |
33 | ||
34 | extcon_usb2: extcon_usb2 { | |
35 | compatible = "linux,extcon-usb-gpio"; | |
36 | id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; | |
37 | }; | |
38b248db RN |
38 | }; |
39 | ||
7e9711aa K |
40 | &dra7_pmx_core { |
41 | i2c1_pins: pinmux_i2c1_pins { | |
42 | pinctrl-single,pins = < | |
43 | 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ | |
44 | 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ | |
45 | >; | |
46 | }; | |
09d4993c RQ |
47 | |
48 | nand_default: nand_default { | |
49 | pinctrl-single,pins = < | |
50 | 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ | |
51 | 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ | |
52 | 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ | |
53 | 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ | |
54 | 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ | |
55 | 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ | |
56 | 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ | |
57 | 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ | |
58 | 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ | |
59 | 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ | |
60 | 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ | |
61 | 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ | |
62 | 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ | |
63 | 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ | |
64 | 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ | |
65 | 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ | |
66 | 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ | |
67 | 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ | |
68 | 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ | |
69 | 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ | |
70 | 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ | |
71 | 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ | |
72 | >; | |
73 | }; | |
95cc6af8 GC |
74 | |
75 | usb1_pins: pinmux_usb1_pins { | |
76 | pinctrl-single,pins = < | |
77 | 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ | |
78 | >; | |
79 | }; | |
80 | ||
81 | usb2_pins: pinmux_usb2_pins { | |
82 | pinctrl-single,pins = < | |
83 | 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ | |
84 | >; | |
85 | }; | |
829acd07 NM |
86 | |
87 | tps65917_pins_default: tps65917_pins_default { | |
88 | pinctrl-single,pins = < | |
89 | 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ | |
90 | >; | |
91 | }; | |
5b434d7e NM |
92 | |
93 | mmc1_pins_default: mmc1_pins_default { | |
94 | pinctrl-single,pins = < | |
95 | 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ | |
96 | 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ | |
97 | 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ | |
98 | 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ | |
99 | 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ | |
100 | 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ | |
101 | 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ | |
102 | >; | |
103 | }; | |
104 | ||
105 | mmc2_pins_default: mmc2_pins_default { | |
106 | pinctrl-single,pins = < | |
107 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | |
108 | 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | |
109 | 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | |
110 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | |
111 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | |
112 | 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | |
113 | 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | |
114 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | |
115 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | |
116 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | |
117 | >; | |
118 | }; | |
ea95af3c RQ |
119 | |
120 | dcan1_pins_default: dcan1_pins_default { | |
121 | pinctrl-single,pins = < | |
d80d581b RQ |
122 | 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ |
123 | 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ | |
ea95af3c RQ |
124 | >; |
125 | }; | |
126 | ||
127 | dcan1_pins_sleep: dcan1_pins_sleep { | |
128 | pinctrl-single,pins = < | |
d80d581b RQ |
129 | 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ |
130 | 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ | |
ea95af3c RQ |
131 | >; |
132 | }; | |
1f43c45d M |
133 | |
134 | qspi1_pins: pinmux_qspi1_pins { | |
135 | pinctrl-single,pins = < | |
136 | 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ | |
137 | 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ | |
138 | 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ | |
139 | 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ | |
140 | 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ | |
141 | 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ | |
142 | 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ | |
143 | >; | |
144 | }; | |
7e9711aa K |
145 | }; |
146 | ||
147 | &i2c1 { | |
148 | status = "okay"; | |
149 | pinctrl-names = "default"; | |
150 | pinctrl-0 = <&i2c1_pins>; | |
151 | clock-frequency = <400000>; | |
b359c426 K |
152 | |
153 | tps65917: tps65917@58 { | |
154 | compatible = "ti,tps65917"; | |
155 | reg = <0x58>; | |
156 | ||
829acd07 NM |
157 | pinctrl-names = "default"; |
158 | pinctrl-0 = <&tps65917_pins_default>; | |
159 | ||
b359c426 K |
160 | interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ |
161 | interrupt-parent = <&gic>; | |
162 | interrupt-controller; | |
163 | #interrupt-cells = <2>; | |
164 | ||
165 | ti,system-power-controller; | |
166 | ||
167 | tps65917_pmic { | |
168 | compatible = "ti,tps65917-pmic"; | |
169 | ||
170 | regulators { | |
171 | smps1_reg: smps1 { | |
172 | /* VDD_MPU */ | |
173 | regulator-name = "smps1"; | |
174 | regulator-min-microvolt = <850000>; | |
175 | regulator-max-microvolt = <1250000>; | |
176 | regulator-always-on; | |
177 | regulator-boot-on; | |
178 | }; | |
179 | ||
180 | smps2_reg: smps2 { | |
181 | /* VDD_CORE */ | |
182 | regulator-name = "smps2"; | |
183 | regulator-min-microvolt = <850000>; | |
70fcaf92 | 184 | regulator-max-microvolt = <1060000>; |
b359c426 K |
185 | regulator-boot-on; |
186 | regulator-always-on; | |
187 | }; | |
188 | ||
189 | smps3_reg: smps3 { | |
190 | /* VDD_GPU IVA DSPEVE */ | |
191 | regulator-name = "smps3"; | |
192 | regulator-min-microvolt = <850000>; | |
193 | regulator-max-microvolt = <1250000>; | |
194 | regulator-boot-on; | |
195 | regulator-always-on; | |
196 | }; | |
197 | ||
198 | smps4_reg: smps4 { | |
199 | /* VDDS1V8 */ | |
200 | regulator-name = "smps4"; | |
201 | regulator-min-microvolt = <1800000>; | |
202 | regulator-max-microvolt = <1800000>; | |
203 | regulator-always-on; | |
204 | regulator-boot-on; | |
205 | }; | |
206 | ||
207 | smps5_reg: smps5 { | |
208 | /* VDD_DDR */ | |
209 | regulator-name = "smps5"; | |
210 | regulator-min-microvolt = <1350000>; | |
211 | regulator-max-microvolt = <1350000>; | |
212 | regulator-boot-on; | |
213 | regulator-always-on; | |
214 | }; | |
215 | ||
216 | ldo1_reg: ldo1 { | |
217 | /* LDO1_OUT --> SDIO */ | |
218 | regulator-name = "ldo1"; | |
219 | regulator-min-microvolt = <1800000>; | |
220 | regulator-max-microvolt = <3300000>; | |
221 | regulator-boot-on; | |
222 | }; | |
223 | ||
224 | ldo2_reg: ldo2 { | |
225 | /* LDO2_OUT --> TP1017 (UNUSED) */ | |
226 | regulator-name = "ldo2"; | |
227 | regulator-min-microvolt = <1800000>; | |
228 | regulator-max-microvolt = <3300000>; | |
229 | }; | |
230 | ||
231 | ldo3_reg: ldo3 { | |
232 | /* VDDA_1V8_PHY */ | |
233 | regulator-name = "ldo3"; | |
234 | regulator-min-microvolt = <1800000>; | |
235 | regulator-max-microvolt = <1800000>; | |
236 | regulator-boot-on; | |
237 | regulator-always-on; | |
238 | }; | |
239 | ||
240 | ldo5_reg: ldo5 { | |
241 | /* VDDA_1V8_PLL */ | |
242 | regulator-name = "ldo5"; | |
243 | regulator-min-microvolt = <1800000>; | |
244 | regulator-max-microvolt = <1800000>; | |
245 | regulator-always-on; | |
246 | regulator-boot-on; | |
247 | }; | |
248 | ||
249 | ldo4_reg: ldo4 { | |
250 | /* VDDA_3V_USB: VDDA_USBHS33 */ | |
251 | regulator-name = "ldo4"; | |
252 | regulator-min-microvolt = <3300000>; | |
253 | regulator-max-microvolt = <3300000>; | |
254 | regulator-boot-on; | |
255 | }; | |
256 | }; | |
257 | }; | |
ab1d3c84 NM |
258 | |
259 | tps65917_power_button { | |
260 | compatible = "ti,palmas-pwrbutton"; | |
261 | interrupt-parent = <&tps65917>; | |
262 | interrupts = <1 IRQ_TYPE_NONE>; | |
263 | wakeup-source; | |
264 | ti,palmas-long-press-seconds = <6>; | |
265 | }; | |
b359c426 | 266 | }; |
f56de327 RQ |
267 | |
268 | pcf_gpio_21: gpio@21 { | |
269 | compatible = "ti,pcf8575"; | |
270 | reg = <0x21>; | |
271 | lines-initial-states = <0x1408>; | |
272 | gpio-controller; | |
273 | #gpio-cells = <2>; | |
274 | interrupt-parent = <&gpio6>; | |
275 | interrupts = <11 IRQ_TYPE_EDGE_FALLING>; | |
276 | interrupt-controller; | |
277 | #interrupt-cells = <2>; | |
278 | }; | |
7e9711aa K |
279 | }; |
280 | ||
38b248db RN |
281 | &uart1 { |
282 | status = "okay"; | |
283 | }; | |
09d4993c RQ |
284 | |
285 | &elm { | |
286 | status = "okay"; | |
287 | }; | |
288 | ||
289 | &gpmc { | |
290 | status = "okay"; | |
291 | pinctrl-names = "default"; | |
292 | pinctrl-0 = <&nand_default>; | |
293 | ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ | |
294 | nand@0,0 { | |
295 | /* To use NAND, DIP switch SW5 must be set like so: | |
296 | * SW5.1 (NAND_SELn) = ON (LOW) | |
297 | * SW5.9 (GPMC_WPN) = OFF (HIGH) | |
298 | */ | |
299 | reg = <0 0 4>; /* device IO registers */ | |
300 | ti,nand-ecc-opt = "bch8"; | |
301 | ti,elm-id = <&elm>; | |
302 | nand-bus-width = <16>; | |
303 | gpmc,device-width = <2>; | |
304 | gpmc,sync-clk-ps = <0>; | |
305 | gpmc,cs-on-ns = <0>; | |
306 | gpmc,cs-rd-off-ns = <80>; | |
307 | gpmc,cs-wr-off-ns = <80>; | |
308 | gpmc,adv-on-ns = <0>; | |
309 | gpmc,adv-rd-off-ns = <60>; | |
310 | gpmc,adv-wr-off-ns = <60>; | |
311 | gpmc,we-on-ns = <10>; | |
312 | gpmc,we-off-ns = <50>; | |
313 | gpmc,oe-on-ns = <4>; | |
314 | gpmc,oe-off-ns = <40>; | |
315 | gpmc,access-ns = <40>; | |
316 | gpmc,wr-access-ns = <80>; | |
317 | gpmc,rd-cycle-ns = <80>; | |
318 | gpmc,wr-cycle-ns = <80>; | |
319 | gpmc,bus-turnaround-ns = <0>; | |
320 | gpmc,cycle2cycle-delay-ns = <0>; | |
321 | gpmc,clk-activation-ns = <0>; | |
322 | gpmc,wait-monitoring-ns = <0>; | |
323 | gpmc,wr-data-mux-bus-ns = <0>; | |
324 | /* MTD partition table */ | |
325 | /* All SPL-* partitions are sized to minimal length | |
326 | * which can be independently programmable. For | |
327 | * NAND flash this is equal to size of erase-block */ | |
328 | #address-cells = <1>; | |
329 | #size-cells = <1>; | |
330 | partition@0 { | |
331 | label = "NAND.SPL"; | |
332 | reg = <0x00000000 0x000020000>; | |
333 | }; | |
334 | partition@1 { | |
335 | label = "NAND.SPL.backup1"; | |
336 | reg = <0x00020000 0x00020000>; | |
337 | }; | |
338 | partition@2 { | |
339 | label = "NAND.SPL.backup2"; | |
340 | reg = <0x00040000 0x00020000>; | |
341 | }; | |
342 | partition@3 { | |
343 | label = "NAND.SPL.backup3"; | |
344 | reg = <0x00060000 0x00020000>; | |
345 | }; | |
346 | partition@4 { | |
347 | label = "NAND.u-boot-spl-os"; | |
348 | reg = <0x00080000 0x00040000>; | |
349 | }; | |
350 | partition@5 { | |
351 | label = "NAND.u-boot"; | |
352 | reg = <0x000c0000 0x00100000>; | |
353 | }; | |
354 | partition@6 { | |
355 | label = "NAND.u-boot-env"; | |
356 | reg = <0x001c0000 0x00020000>; | |
357 | }; | |
358 | partition@7 { | |
359 | label = "NAND.u-boot-env.backup1"; | |
360 | reg = <0x001e0000 0x00020000>; | |
361 | }; | |
362 | partition@8 { | |
363 | label = "NAND.kernel"; | |
364 | reg = <0x00200000 0x00800000>; | |
365 | }; | |
366 | partition@9 { | |
367 | label = "NAND.file-system"; | |
368 | reg = <0x00a00000 0x0f600000>; | |
369 | }; | |
370 | }; | |
371 | }; | |
95cc6af8 | 372 | |
7a15c8e7 RQ |
373 | &usb2_phy1 { |
374 | phy-supply = <&ldo4_reg>; | |
375 | }; | |
376 | ||
377 | &usb2_phy2 { | |
378 | phy-supply = <&ldo4_reg>; | |
379 | }; | |
380 | ||
95cc6af8 GC |
381 | &usb1 { |
382 | dr_mode = "peripheral"; | |
383 | pinctrl-names = "default"; | |
384 | pinctrl-0 = <&usb1_pins>; | |
385 | }; | |
386 | ||
387 | &usb2 { | |
388 | dr_mode = "host"; | |
389 | pinctrl-names = "default"; | |
390 | pinctrl-0 = <&usb2_pins>; | |
391 | }; | |
5b434d7e NM |
392 | |
393 | &mmc1 { | |
394 | status = "okay"; | |
395 | pinctrl-names = "default"; | |
396 | pinctrl-0 = <&mmc1_pins_default>; | |
397 | ||
398 | vmmc-supply = <&ldo1_reg>; | |
399 | bus-width = <4>; | |
400 | /* | |
401 | * SDCD signal is not being used here - using the fact that GPIO mode | |
402 | * is a viable alternative | |
403 | */ | |
404 | cd-gpios = <&gpio6 27 0>; | |
405 | }; | |
406 | ||
407 | &mmc2 { | |
408 | /* SW5-3 in ON position */ | |
409 | status = "okay"; | |
410 | pinctrl-names = "default"; | |
411 | pinctrl-0 = <&mmc2_pins_default>; | |
412 | ||
413 | vmmc-supply = <&evm_3v3>; | |
414 | bus-width = <8>; | |
415 | ti,non-removable; | |
416 | }; | |
d5475152 M |
417 | |
418 | &dra7_pmx_core { | |
419 | cpsw_default: cpsw_default { | |
420 | pinctrl-single,pins = < | |
421 | /* Slave 2 */ | |
422 | 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ | |
423 | 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ | |
424 | 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ | |
425 | 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ | |
426 | 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ | |
427 | 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ | |
428 | 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ | |
429 | 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ | |
430 | 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ | |
431 | 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ | |
432 | 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ | |
433 | 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ | |
434 | >; | |
435 | ||
436 | }; | |
437 | ||
438 | cpsw_sleep: cpsw_sleep { | |
439 | pinctrl-single,pins = < | |
440 | /* Slave 2 */ | |
441 | 0x198 (MUX_MODE15) | |
442 | 0x19c (MUX_MODE15) | |
443 | 0x1a0 (MUX_MODE15) | |
444 | 0x1a4 (MUX_MODE15) | |
445 | 0x1a8 (MUX_MODE15) | |
446 | 0x1ac (MUX_MODE15) | |
447 | 0x1b0 (MUX_MODE15) | |
448 | 0x1b4 (MUX_MODE15) | |
449 | 0x1b8 (MUX_MODE15) | |
450 | 0x1bc (MUX_MODE15) | |
451 | 0x1c0 (MUX_MODE15) | |
452 | 0x1c4 (MUX_MODE15) | |
453 | >; | |
454 | }; | |
455 | ||
456 | davinci_mdio_default: davinci_mdio_default { | |
457 | pinctrl-single,pins = < | |
458 | /* MDIO */ | |
459 | 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ | |
460 | 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | |
461 | >; | |
462 | }; | |
463 | ||
464 | davinci_mdio_sleep: davinci_mdio_sleep { | |
465 | pinctrl-single,pins = < | |
466 | 0x23c (MUX_MODE15) | |
467 | 0x240 (MUX_MODE15) | |
468 | >; | |
469 | }; | |
470 | }; | |
471 | ||
472 | &mac { | |
473 | status = "okay"; | |
474 | pinctrl-names = "default", "sleep"; | |
475 | pinctrl-0 = <&cpsw_default>; | |
476 | pinctrl-1 = <&cpsw_sleep>; | |
477 | }; | |
478 | ||
479 | &cpsw_emac1 { | |
480 | phy_id = <&davinci_mdio>, <3>; | |
481 | phy-mode = "rgmii"; | |
482 | }; | |
483 | ||
484 | &davinci_mdio { | |
485 | pinctrl-names = "default", "sleep"; | |
486 | pinctrl-0 = <&davinci_mdio_default>; | |
487 | pinctrl-1 = <&davinci_mdio_sleep>; | |
488 | active_slave = <1>; | |
489 | }; | |
ea95af3c RQ |
490 | |
491 | &dcan1 { | |
492 | status = "ok"; | |
493 | pinctrl-names = "default", "sleep"; | |
494 | pinctrl-0 = <&dcan1_pins_default>; | |
495 | pinctrl-1 = <&dcan1_pins_sleep>; | |
496 | }; | |
1f43c45d M |
497 | |
498 | &qspi { | |
499 | status = "okay"; | |
500 | pinctrl-names = "default"; | |
501 | pinctrl-0 = <&qspi1_pins>; | |
502 | ||
503 | spi-max-frequency = <48000000>; | |
504 | m25p80@0 { | |
505 | compatible = "s25fl256s1"; | |
506 | spi-max-frequency = <48000000>; | |
507 | reg = <0>; | |
508 | spi-tx-bus-width = <1>; | |
509 | spi-rx-bus-width = <4>; | |
510 | spi-cpol; | |
511 | spi-cpha; | |
512 | #address-cells = <1>; | |
513 | #size-cells = <1>; | |
514 | ||
515 | /* MTD partition table. | |
516 | * The ROM checks the first four physical blocks | |
517 | * for a valid file to boot and the flash here is | |
518 | * 64KiB block size. | |
519 | */ | |
520 | partition@0 { | |
521 | label = "QSPI.SPL"; | |
522 | reg = <0x00000000 0x000010000>; | |
523 | }; | |
524 | partition@1 { | |
525 | label = "QSPI.SPL.backup1"; | |
526 | reg = <0x00010000 0x00010000>; | |
527 | }; | |
528 | partition@2 { | |
529 | label = "QSPI.SPL.backup2"; | |
530 | reg = <0x00020000 0x00010000>; | |
531 | }; | |
532 | partition@3 { | |
533 | label = "QSPI.SPL.backup3"; | |
534 | reg = <0x00030000 0x00010000>; | |
535 | }; | |
536 | partition@4 { | |
537 | label = "QSPI.u-boot"; | |
538 | reg = <0x00040000 0x00100000>; | |
539 | }; | |
540 | partition@5 { | |
541 | label = "QSPI.u-boot-spl-os"; | |
542 | reg = <0x00140000 0x00080000>; | |
543 | }; | |
544 | partition@6 { | |
545 | label = "QSPI.u-boot-env"; | |
546 | reg = <0x001c0000 0x00010000>; | |
547 | }; | |
548 | partition@7 { | |
549 | label = "QSPI.u-boot-env.backup1"; | |
550 | reg = <0x001d0000 0x0010000>; | |
551 | }; | |
552 | partition@8 { | |
553 | label = "QSPI.kernel"; | |
554 | reg = <0x001e0000 0x0800000>; | |
555 | }; | |
556 | partition@9 { | |
557 | label = "QSPI.file-system"; | |
558 | reg = <0x009e0000 0x01620000>; | |
559 | }; | |
560 | }; | |
561 | }; |