Commit | Line | Data |
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7d6ab9b8 RH |
1 | /* |
2 | * Copyright 2011-2012 Calxeda, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | / { | |
18 | chosen { | |
19 | bootargs = "console=ttyAMA0"; | |
20 | }; | |
21 | ||
22 | soc { | |
23 | #address-cells = <1>; | |
24 | #size-cells = <1>; | |
25 | compatible = "simple-bus"; | |
26 | interrupt-parent = <&intc>; | |
27 | ||
28 | sata@ffe08000 { | |
29 | compatible = "calxeda,hb-ahci"; | |
30 | reg = <0xffe08000 0x10000>; | |
31 | interrupts = <0 83 4>; | |
32 | dma-coherent; | |
33 | calxeda,port-phys = <&combophy5 0 &combophy0 0 | |
34 | &combophy0 1 &combophy0 2 | |
35 | &combophy0 3>; | |
36 | }; | |
37 | ||
38 | sdhci@ffe0e000 { | |
39 | compatible = "calxeda,hb-sdhci"; | |
40 | reg = <0xffe0e000 0x1000>; | |
41 | interrupts = <0 90 4>; | |
42 | clocks = <&eclk>; | |
43 | status = "disabled"; | |
44 | }; | |
45 | ||
46 | memory-controller@fff00000 { | |
47 | compatible = "calxeda,hb-ddr-ctrl"; | |
48 | reg = <0xfff00000 0x1000>; | |
49 | interrupts = <0 91 4>; | |
50 | }; | |
51 | ||
52 | ipc@fff20000 { | |
53 | compatible = "arm,pl320", "arm,primecell"; | |
54 | reg = <0xfff20000 0x1000>; | |
55 | interrupts = <0 7 4>; | |
56 | clocks = <&pclk>; | |
57 | clock-names = "apb_pclk"; | |
58 | }; | |
59 | ||
60 | gpioe: gpio@fff30000 { | |
61 | #gpio-cells = <2>; | |
62 | compatible = "arm,pl061", "arm,primecell"; | |
63 | gpio-controller; | |
64 | reg = <0xfff30000 0x1000>; | |
65 | interrupts = <0 14 4>; | |
66 | clocks = <&pclk>; | |
67 | clock-names = "apb_pclk"; | |
68 | status = "disabled"; | |
69 | }; | |
70 | ||
71 | gpiof: gpio@fff31000 { | |
72 | #gpio-cells = <2>; | |
73 | compatible = "arm,pl061", "arm,primecell"; | |
74 | gpio-controller; | |
75 | reg = <0xfff31000 0x1000>; | |
76 | interrupts = <0 15 4>; | |
77 | clocks = <&pclk>; | |
78 | clock-names = "apb_pclk"; | |
79 | status = "disabled"; | |
80 | }; | |
81 | ||
82 | gpiog: gpio@fff32000 { | |
83 | #gpio-cells = <2>; | |
84 | compatible = "arm,pl061", "arm,primecell"; | |
85 | gpio-controller; | |
86 | reg = <0xfff32000 0x1000>; | |
87 | interrupts = <0 16 4>; | |
88 | clocks = <&pclk>; | |
89 | clock-names = "apb_pclk"; | |
90 | status = "disabled"; | |
91 | }; | |
92 | ||
93 | gpioh: gpio@fff33000 { | |
94 | #gpio-cells = <2>; | |
95 | compatible = "arm,pl061", "arm,primecell"; | |
96 | gpio-controller; | |
97 | reg = <0xfff33000 0x1000>; | |
98 | interrupts = <0 17 4>; | |
99 | clocks = <&pclk>; | |
100 | clock-names = "apb_pclk"; | |
101 | status = "disabled"; | |
102 | }; | |
103 | ||
104 | timer@fff34000 { | |
105 | compatible = "arm,sp804", "arm,primecell"; | |
106 | reg = <0xfff34000 0x1000>; | |
107 | interrupts = <0 18 4>; | |
108 | clocks = <&pclk>; | |
109 | clock-names = "apb_pclk"; | |
110 | }; | |
111 | ||
112 | rtc@fff35000 { | |
113 | compatible = "arm,pl031", "arm,primecell"; | |
114 | reg = <0xfff35000 0x1000>; | |
115 | interrupts = <0 19 4>; | |
116 | clocks = <&pclk>; | |
117 | clock-names = "apb_pclk"; | |
118 | }; | |
119 | ||
120 | serial@fff36000 { | |
121 | compatible = "arm,pl011", "arm,primecell"; | |
122 | reg = <0xfff36000 0x1000>; | |
123 | interrupts = <0 20 4>; | |
124 | clocks = <&pclk>; | |
125 | clock-names = "apb_pclk"; | |
126 | }; | |
127 | ||
128 | smic@fff3a000 { | |
129 | compatible = "ipmi-smic"; | |
130 | device_type = "ipmi"; | |
131 | reg = <0xfff3a000 0x1000>; | |
132 | interrupts = <0 24 4>; | |
133 | reg-size = <4>; | |
134 | reg-spacing = <4>; | |
135 | }; | |
136 | ||
137 | sregs@fff3c000 { | |
138 | compatible = "calxeda,hb-sregs"; | |
139 | reg = <0xfff3c000 0x1000>; | |
140 | ||
141 | clocks { | |
142 | #address-cells = <1>; | |
143 | #size-cells = <0>; | |
144 | ||
145 | osc: oscillator { | |
146 | #clock-cells = <0>; | |
147 | compatible = "fixed-clock"; | |
148 | clock-frequency = <33333000>; | |
149 | }; | |
150 | ||
151 | ddrpll: ddrpll { | |
152 | #clock-cells = <0>; | |
153 | compatible = "calxeda,hb-pll-clock"; | |
154 | clocks = <&osc>; | |
155 | reg = <0x108>; | |
156 | }; | |
157 | ||
158 | a9pll: a9pll { | |
159 | #clock-cells = <0>; | |
160 | compatible = "calxeda,hb-pll-clock"; | |
161 | clocks = <&osc>; | |
162 | reg = <0x100>; | |
163 | }; | |
164 | ||
165 | a9periphclk: a9periphclk { | |
166 | #clock-cells = <0>; | |
167 | compatible = "calxeda,hb-a9periph-clock"; | |
168 | clocks = <&a9pll>; | |
169 | reg = <0x104>; | |
170 | }; | |
171 | ||
172 | a9bclk: a9bclk { | |
173 | #clock-cells = <0>; | |
174 | compatible = "calxeda,hb-a9bus-clock"; | |
175 | clocks = <&a9pll>; | |
176 | reg = <0x104>; | |
177 | }; | |
178 | ||
179 | emmcpll: emmcpll { | |
180 | #clock-cells = <0>; | |
181 | compatible = "calxeda,hb-pll-clock"; | |
182 | clocks = <&osc>; | |
183 | reg = <0x10C>; | |
184 | }; | |
185 | ||
186 | eclk: eclk { | |
187 | #clock-cells = <0>; | |
188 | compatible = "calxeda,hb-emmc-clock"; | |
189 | clocks = <&emmcpll>; | |
190 | reg = <0x114>; | |
191 | }; | |
192 | ||
193 | pclk: pclk { | |
194 | #clock-cells = <0>; | |
195 | compatible = "fixed-clock"; | |
196 | clock-frequency = <150000000>; | |
197 | }; | |
198 | }; | |
199 | }; | |
200 | ||
201 | dma@fff3d000 { | |
202 | compatible = "arm,pl330", "arm,primecell"; | |
203 | reg = <0xfff3d000 0x1000>; | |
204 | interrupts = <0 92 4>; | |
205 | clocks = <&pclk>; | |
206 | clock-names = "apb_pclk"; | |
207 | }; | |
208 | ||
209 | ethernet@fff50000 { | |
210 | compatible = "calxeda,hb-xgmac"; | |
211 | reg = <0xfff50000 0x1000>; | |
212 | interrupts = <0 77 4 0 78 4 0 79 4>; | |
213 | dma-coherent; | |
214 | }; | |
215 | ||
216 | ethernet@fff51000 { | |
217 | compatible = "calxeda,hb-xgmac"; | |
218 | reg = <0xfff51000 0x1000>; | |
219 | interrupts = <0 80 4 0 81 4 0 82 4>; | |
220 | dma-coherent; | |
221 | }; | |
222 | ||
223 | combophy0: combo-phy@fff58000 { | |
224 | compatible = "calxeda,hb-combophy"; | |
225 | #phy-cells = <1>; | |
226 | reg = <0xfff58000 0x1000>; | |
227 | phydev = <5>; | |
228 | }; | |
229 | ||
230 | combophy5: combo-phy@fff5d000 { | |
231 | compatible = "calxeda,hb-combophy"; | |
232 | #phy-cells = <1>; | |
233 | reg = <0xfff5d000 0x1000>; | |
234 | phydev = <31>; | |
235 | }; | |
236 | }; | |
237 | }; |