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3d5de271 MD |
1 | /* |
2 | * Device Tree Source for the EMEV2 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Renesas Solutions Corp. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
cef20af0 | 11 | #include "skeleton.dtsi" |
3dc76086 | 12 | #include <dt-bindings/interrupt-controller/irq.h> |
3d5de271 MD |
13 | |
14 | / { | |
15 | compatible = "renesas,emev2"; | |
16 | interrupt-parent = <&gic>; | |
17 | ||
12d035b1 MD |
18 | aliases { |
19 | gpio0 = &gpio0; | |
20 | gpio1 = &gpio1; | |
21 | gpio2 = &gpio2; | |
22 | gpio3 = &gpio3; | |
23 | gpio4 = &gpio4; | |
24 | }; | |
25 | ||
3d5de271 | 26 | cpus { |
fe681d29 SH |
27 | #address-cells = <1>; |
28 | #size-cells = <0>; | |
29 | ||
3d5de271 | 30 | cpu@0 { |
fe681d29 | 31 | device_type = "cpu"; |
3d5de271 | 32 | compatible = "arm,cortex-a9"; |
fe681d29 | 33 | reg = <0>; |
11f1ca10 | 34 | clock-frequency = <533000000>; |
3d5de271 MD |
35 | }; |
36 | cpu@1 { | |
fe681d29 | 37 | device_type = "cpu"; |
3d5de271 | 38 | compatible = "arm,cortex-a9"; |
fe681d29 | 39 | reg = <1>; |
11f1ca10 | 40 | clock-frequency = <533000000>; |
3d5de271 MD |
41 | }; |
42 | }; | |
43 | ||
44 | gic: interrupt-controller@e0020000 { | |
45 | compatible = "arm,cortex-a9-gic"; | |
46 | interrupt-controller; | |
47 | #interrupt-cells = <3>; | |
48 | reg = <0xe0028000 0x1000>, | |
49 | <0xe0020000 0x0100>; | |
50 | }; | |
51 | ||
c95ebbb2 MD |
52 | pmu { |
53 | compatible = "arm,cortex-a9-pmu"; | |
3dc76086 LP |
54 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, |
55 | <0 121 IRQ_TYPE_LEVEL_HIGH>; | |
c95ebbb2 MD |
56 | }; |
57 | ||
87982b2d | 58 | clocks@e0110000 { |
fdf6fd22 TY |
59 | compatible = "renesas,emev2-smu"; |
60 | reg = <0xe0110000 0x10000>; | |
61 | #address-cells = <2>; | |
62 | #size-cells = <0>; | |
63 | ||
64 | c32ki: c32ki { | |
65 | compatible = "fixed-clock"; | |
66 | clock-frequency = <32768>; | |
67 | #clock-cells = <0>; | |
68 | }; | |
69 | pll3_fo: pll3_fo { | |
70 | compatible = "fixed-factor-clock"; | |
71 | clocks = <&c32ki>; | |
72 | clock-div = <1>; | |
73 | clock-mult = <7000>; | |
74 | #clock-cells = <0>; | |
75 | }; | |
76 | usia_u0_sclkdiv: usia_u0_sclkdiv { | |
77 | compatible = "renesas,emev2-smu-clkdiv"; | |
78 | reg = <0x610 0>; | |
79 | clocks = <&pll3_fo>; | |
80 | #clock-cells = <0>; | |
81 | }; | |
82 | usib_u1_sclkdiv: usib_u1_sclkdiv { | |
83 | compatible = "renesas,emev2-smu-clkdiv"; | |
84 | reg = <0x65c 0>; | |
85 | clocks = <&pll3_fo>; | |
86 | #clock-cells = <0>; | |
87 | }; | |
88 | usib_u2_sclkdiv: usib_u2_sclkdiv { | |
89 | compatible = "renesas,emev2-smu-clkdiv"; | |
90 | reg = <0x65c 16>; | |
91 | clocks = <&pll3_fo>; | |
92 | #clock-cells = <0>; | |
93 | }; | |
94 | usib_u3_sclkdiv: usib_u3_sclkdiv { | |
95 | compatible = "renesas,emev2-smu-clkdiv"; | |
96 | reg = <0x660 0>; | |
97 | clocks = <&pll3_fo>; | |
98 | #clock-cells = <0>; | |
99 | }; | |
100 | usia_u0_sclk: usia_u0_sclk { | |
101 | compatible = "renesas,emev2-smu-gclk"; | |
102 | reg = <0x4a0 1>; | |
103 | clocks = <&usia_u0_sclkdiv>; | |
104 | #clock-cells = <0>; | |
105 | }; | |
106 | usib_u1_sclk: usib_u1_sclk { | |
107 | compatible = "renesas,emev2-smu-gclk"; | |
108 | reg = <0x4b8 1>; | |
109 | clocks = <&usib_u1_sclkdiv>; | |
110 | #clock-cells = <0>; | |
111 | }; | |
112 | usib_u2_sclk: usib_u2_sclk { | |
113 | compatible = "renesas,emev2-smu-gclk"; | |
114 | reg = <0x4bc 1>; | |
115 | clocks = <&usib_u2_sclkdiv>; | |
116 | #clock-cells = <0>; | |
117 | }; | |
118 | usib_u3_sclk: usib_u3_sclk { | |
119 | compatible = "renesas,emev2-smu-gclk"; | |
120 | reg = <0x4c0 1>; | |
121 | clocks = <&usib_u3_sclkdiv>; | |
122 | #clock-cells = <0>; | |
123 | }; | |
124 | sti_sclk: sti_sclk { | |
125 | compatible = "renesas,emev2-smu-gclk"; | |
126 | reg = <0x528 1>; | |
127 | clocks = <&c32ki>; | |
128 | #clock-cells = <0>; | |
129 | }; | |
130 | }; | |
131 | ||
87982b2d | 132 | timer@e0180000 { |
3d5de271 MD |
133 | compatible = "renesas,em-sti"; |
134 | reg = <0xe0180000 0x54>; | |
e05ab0bb | 135 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
fdf6fd22 TY |
136 | clocks = <&sti_sclk>; |
137 | clock-names = "sclk"; | |
3d5de271 MD |
138 | }; |
139 | ||
e87aabaf | 140 | uart0: serial@e1020000 { |
3d5de271 MD |
141 | compatible = "renesas,em-uart"; |
142 | reg = <0xe1020000 0x38>; | |
e05ab0bb | 143 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
fdf6fd22 TY |
144 | clocks = <&usia_u0_sclk>; |
145 | clock-names = "sclk"; | |
3d5de271 MD |
146 | }; |
147 | ||
e87aabaf | 148 | uart1: serial@e1030000 { |
3d5de271 MD |
149 | compatible = "renesas,em-uart"; |
150 | reg = <0xe1030000 0x38>; | |
e05ab0bb | 151 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
fdf6fd22 TY |
152 | clocks = <&usib_u1_sclk>; |
153 | clock-names = "sclk"; | |
3d5de271 MD |
154 | }; |
155 | ||
e87aabaf | 156 | uart2: serial@e1040000 { |
3d5de271 MD |
157 | compatible = "renesas,em-uart"; |
158 | reg = <0xe1040000 0x38>; | |
e05ab0bb | 159 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; |
fdf6fd22 TY |
160 | clocks = <&usib_u2_sclk>; |
161 | clock-names = "sclk"; | |
3d5de271 MD |
162 | }; |
163 | ||
e87aabaf | 164 | uart3: serial@e1050000 { |
3d5de271 MD |
165 | compatible = "renesas,em-uart"; |
166 | reg = <0xe1050000 0x38>; | |
e05ab0bb | 167 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; |
fdf6fd22 TY |
168 | clocks = <&usib_u3_sclk>; |
169 | clock-names = "sclk"; | |
3d5de271 | 170 | }; |
12d035b1 | 171 | |
e7cdf791 NS |
172 | pfc: pfc@e0140200 { |
173 | compatible = "renesas,pfc-emev2"; | |
174 | reg = <0xe0140200 0x100>; | |
175 | }; | |
176 | ||
12d035b1 MD |
177 | gpio0: gpio@e0050000 { |
178 | compatible = "renesas,em-gio"; | |
179 | reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; | |
e05ab0bb LP |
180 | interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>, |
181 | <0 68 IRQ_TYPE_LEVEL_HIGH>; | |
12d035b1 | 182 | gpio-controller; |
e7cdf791 | 183 | gpio-ranges = <&pfc 0 0 32>; |
12d035b1 MD |
184 | #gpio-cells = <2>; |
185 | ngpios = <32>; | |
186 | interrupt-controller; | |
187 | #interrupt-cells = <2>; | |
188 | }; | |
189 | gpio1: gpio@e0050080 { | |
190 | compatible = "renesas,em-gio"; | |
191 | reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; | |
e05ab0bb LP |
192 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>, |
193 | <0 70 IRQ_TYPE_LEVEL_HIGH>; | |
12d035b1 | 194 | gpio-controller; |
e7cdf791 | 195 | gpio-ranges = <&pfc 0 32 32>; |
12d035b1 MD |
196 | #gpio-cells = <2>; |
197 | ngpios = <32>; | |
198 | interrupt-controller; | |
199 | #interrupt-cells = <2>; | |
200 | }; | |
201 | gpio2: gpio@e0050100 { | |
202 | compatible = "renesas,em-gio"; | |
203 | reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; | |
e05ab0bb LP |
204 | interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>, |
205 | <0 72 IRQ_TYPE_LEVEL_HIGH>; | |
12d035b1 | 206 | gpio-controller; |
e7cdf791 | 207 | gpio-ranges = <&pfc 0 64 32>; |
12d035b1 MD |
208 | #gpio-cells = <2>; |
209 | ngpios = <32>; | |
210 | interrupt-controller; | |
211 | #interrupt-cells = <2>; | |
212 | }; | |
213 | gpio3: gpio@e0050180 { | |
214 | compatible = "renesas,em-gio"; | |
215 | reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; | |
e05ab0bb LP |
216 | interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>, |
217 | <0 74 IRQ_TYPE_LEVEL_HIGH>; | |
12d035b1 | 218 | gpio-controller; |
e7cdf791 | 219 | gpio-ranges = <&pfc 0 96 32>; |
12d035b1 MD |
220 | #gpio-cells = <2>; |
221 | ngpios = <32>; | |
222 | interrupt-controller; | |
223 | #interrupt-cells = <2>; | |
224 | }; | |
225 | gpio4: gpio@e0050200 { | |
226 | compatible = "renesas,em-gio"; | |
227 | reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; | |
e05ab0bb LP |
228 | interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>, |
229 | <0 76 IRQ_TYPE_LEVEL_HIGH>; | |
12d035b1 | 230 | gpio-controller; |
e7cdf791 | 231 | gpio-ranges = <&pfc 0 128 31>; |
12d035b1 MD |
232 | #gpio-cells = <2>; |
233 | ngpios = <31>; | |
234 | interrupt-controller; | |
235 | #interrupt-cells = <2>; | |
236 | }; | |
3d5de271 | 237 | }; |