[deliverable/linux.git] / arch / arm / boot / dts / exynos3250.dtsi

/*
 * Samsung's Exynos3250 SoC device tree source
 *
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
 * nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "skeleton.dtsi"
#include "exynos4-cpu-thermal.dtsi"
#include "exynos-syscon-restart.dtsi"
#include <dt-bindings/clock/exynos3250.h>

/ {
	compatible = "samsung,exynos3250";
	interrupt-parent = <&gic>;

	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		mshc0 = &mshc_0;
		mshc1 = &mshc_1;
		mshc2 = &mshc_2;
		spi0 = &spi_0;
		spi1 = &spi_1;
		i2c0 = &i2c_0;
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		i2c4 = &i2c_4;
		i2c5 = &i2c_5;
		i2c6 = &i2c_6;
		i2c7 = &i2c_7;
		serial0 = &serial_0;
		serial1 = &serial_1;
		serial2 = &serial_2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0>;
			clock-frequency = <1000000000>;
			clocks = <&cmu CLK_ARM_CLK>;
			clock-names = "cpu";
			#cooling-cells = <2>;

			operating-points = <
				1000000 1150000
				900000  1112500
				800000  1075000
				700000  1037500
				600000  1000000
				500000  962500
				400000  925000
				300000  887500
				200000  850000
				100000  850000
			>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <1>;
			clock-frequency = <1000000000>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		fixed-rate-clocks {
			#address-cells = <1>;
			#size-cells = <0>;

			xusbxti: clock@0 {
				compatible = "fixed-clock";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xusbxti";
			};

			xxti: clock@1 {
				compatible = "fixed-clock";
				reg = <1>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xxti";
			};

			xtcxo: clock@2 {
				compatible = "fixed-clock";
				reg = <2>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xtcxo";
			};
		};

		sysram@02020000 {
			compatible = "mmio-sram";
			reg = <0x02020000 0x40000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x02020000 0x40000>;

			smp-sysram@0 {
				compatible = "samsung,exynos4210-sysram";
				reg = <0x0 0x1000>;
			};

			smp-sysram@3f000 {
				compatible = "samsung,exynos4210-sysram-ns";
				reg = <0x3f000 0x1000>;
			};
		};

		chipid@10000000 {
			compatible = "samsung,exynos4210-chipid";
			reg = <0x10000000 0x100>;
		};

		sys_reg: syscon@10010000 {
			compatible = "samsung,exynos3-sysreg", "syscon";
			reg = <0x10010000 0x400>;
		};

		pmu_system_controller: system-controller@10020000 {
			compatible = "samsung,exynos3250-pmu", "syscon";
			reg = <0x10020000 0x4000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
		};

		mipi_phy: video-phy {
			compatible = "samsung,s5pv210-mipi-video-phy";
			#phy-cells = <1>;
			syscon = <&pmu_system_controller>;
		};

		pd_cam: cam-power-domain@10023C00 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C00 0x20>;
			#power-domain-cells = <0>;
		};

		pd_mfc: mfc-power-domain@10023C40 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C40 0x20>;
			#power-domain-cells = <0>;
		};

		pd_g3d: g3d-power-domain@10023C60 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C60 0x20>;
			#power-domain-cells = <0>;
		};

		pd_lcd0: lcd0-power-domain@10023C80 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C80 0x20>;
			#power-domain-cells = <0>;
		};

		pd_isp: isp-power-domain@10023CA0 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023CA0 0x20>;
			#power-domain-cells = <0>;
		};

		cmu: clock-controller@10030000 {
			compatible = "samsung,exynos3250-cmu";
			reg = <0x10030000 0x20000>;
			#clock-cells = <1>;
			assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
					  <&cmu CLK_MOUT_ACLK_266_SUB>;
			assigned-clock-parents = <&cmu CLK_FIN_PLL>,
						 <&cmu CLK_FIN_PLL>;
		};

		cmu_dmc: clock-controller@105C0000 {
			compatible = "samsung,exynos3250-cmu-dmc";
			reg = <0x105C0000 0x2000>;
			#clock-cells = <1>;
		};

		rtc: rtc@10070000 {
			compatible = "samsung,s3c6410-rtc";
			reg = <0x10070000 0x100>;
			interrupts = <0 73 0>, <0 74 0>;
			interrupt-parent = <&pmu_system_controller>;
			status = "disabled";
		};

		tmu: tmu@100C0000 {
			compatible = "samsung,exynos3250-tmu";
			reg = <0x100C0000 0x100>;
			interrupts = <0 216 0>;
			clocks = <&cmu CLK_TMU_APBIF>;
			clock-names = "tmu_apbif";
			#include "exynos4412-tmu-sensor-conf.dtsi"
			status = "disabled";
		};

		gic: interrupt-controller@10481000 {
			compatible = "arm,cortex-a15-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x10481000 0x1000>,
			      <0x10482000 0x1000>,
			      <0x10484000 0x2000>,
			      <0x10486000 0x2000>;
			interrupts = <1 9 0xf04>;
		};

		mct@10050000 {
			compatible = "samsung,exynos4210-mct";
			reg = <0x10050000 0x800>;
			interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
				     <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
			clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
			clock-names = "fin_pll", "mct";
		};

		pinctrl_1: pinctrl@11000000 {
			compatible = "samsung,exynos3250-pinctrl";
			reg = <0x11000000 0x1000>;
			interrupts = <0 225 0>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynos4210-wakeup-eint";
				interrupts = <0 48 0>;
			};
		};

		pinctrl_0: pinctrl@11400000 {
			compatible = "samsung,exynos3250-pinctrl";
			reg = <0x11400000 0x1000>;
			interrupts = <0 240 0>;
		};

		jpeg: codec@11830000 {
			compatible = "samsung,exynos3250-jpeg";
			reg = <0x11830000 0x1000>;
			interrupts = <0 171 0>;
			clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
			clock-names = "jpeg", "sclk";
			power-domains = <&pd_cam>;
			assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
			assigned-clock-rates = <0>, <150000000>;
			assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
			iommus = <&sysmmu_jpeg>;
			status = "disabled";
		};

		sysmmu_jpeg: sysmmu@11A60000 {
			compatible = "samsung,exynos-sysmmu";
			reg = <0x11a60000 0x1000>;
			interrupts = <0 156 0>, <0 161 0>;
			clock-names = "sysmmu", "master";
			clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
			power-domains = <&pd_cam>;
			#iommu-cells = <0>;
		};

		fimd: fimd@11c00000 {
			compatible = "samsung,exynos3250-fimd";
			reg = <0x11c00000 0x30000>;
			interrupt-names = "fifo", "vsync", "lcd_sys";
			interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
			clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
			clock-names = "sclk_fimd", "fimd";
			power-domains = <&pd_lcd0>;
			iommus = <&sysmmu_fimd0>;
			samsung,sysreg = <&sys_reg>;
			status = "disabled";
		};

		dsi_0: dsi@11C80000 {
			compatible = "samsung,exynos3250-mipi-dsi";
			reg = <0x11C80000 0x10000>;
			interrupts = <0 83 0>;
			samsung,phy-type = <0>;
			power-domains = <&pd_lcd0>;
			phys = <&mipi_phy 1>;
			phy-names = "dsim";
			clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
			clock-names = "bus_clk", "pll_clk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		sysmmu_fimd0: sysmmu@11E20000 {
			compatible = "samsung,exynos-sysmmu";
			reg = <0x11e20000 0x1000>;
			interrupts = <0 80 0>, <0 81 0>;
			clock-names = "sysmmu", "master";
			clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
			power-domains = <&pd_lcd0>;
			#iommu-cells = <0>;
		};

		hsotg: hsotg@12480000 {
			compatible = "snps,dwc2";
			reg = <0x12480000 0x20000>;
			interrupts = <0 141 0>;
			clocks = <&cmu CLK_USBOTG>;
			clock-names = "otg";
			phys = <&exynos_usbphy 0>;
			phy-names = "usb2-phy";
			status = "disabled";
		};

		mshc_0: mshc@12510000 {
			compatible = "samsung,exynos5420-dw-mshc";
			reg = <0x12510000 0x1000>;
			interrupts = <0 142 0>;
			clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mshc_1: mshc@12520000 {
			compatible = "samsung,exynos5420-dw-mshc";
			reg = <0x12520000 0x1000>;
			interrupts = <0 143 0>;
			clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mshc_2: mshc@12530000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12530000 0x1000>;
			interrupts = <0 144 0>;
			clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		exynos_usbphy: exynos-usbphy@125B0000 {
			compatible = "samsung,exynos3250-usb2-phy";
			reg = <0x125B0000 0x100>;
			samsung,pmureg-phandle = <&pmu_system_controller>;
			clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
			clock-names = "phy", "ref";
			#phy-cells = <1>;
			status = "disabled";
		};

		amba {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			pdma0: pdma@12680000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x12680000 0x1000>;
				interrupts = <0 138 0>;
				clocks = <&cmu CLK_PDMA0>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};

			pdma1: pdma@12690000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x12690000 0x1000>;
				interrupts = <0 139 0>;
				clocks = <&cmu CLK_PDMA1>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};
		};

		adc: adc@126C0000 {
			compatible = "samsung,exynos3250-adc",
				     "samsung,exynos-adc-v2";
			reg = <0x126C0000 0x100>;
			interrupts = <0 137 0>;
			clock-names = "adc", "sclk";
			clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
			#io-channel-cells = <1>;
			io-channel-ranges;
			samsung,syscon-phandle = <&pmu_system_controller>;
			status = "disabled";
		};

		mfc: codec@13400000 {
			compatible = "samsung,mfc-v7";
			reg = <0x13400000 0x10000>;
			interrupts = <0 102 0>;
			clock-names = "mfc", "sclk_mfc";
			clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
			power-domains = <&pd_mfc>;
			iommus = <&sysmmu_mfc>;
			status = "disabled";
		};

		sysmmu_mfc: sysmmu@13620000 {
			compatible = "samsung,exynos-sysmmu";
			reg = <0x13620000 0x1000>;
			interrupts = <0 96 0>, <0 98 0>;
			clock-names = "sysmmu", "master";
			clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
			power-domains = <&pd_mfc>;
			#iommu-cells = <0>;
		};

		serial_0: serial@13800000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13800000 0x100>;
			interrupts = <0 109 0>;
			clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
			clock-names = "uart", "clk_uart_baud0";
			pinctrl-names = "default";
			pinctrl-0 = <&uart0_data &uart0_fctl>;
			status = "disabled";
		};

		serial_1: serial@13810000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13810000 0x100>;
			interrupts = <0 110 0>;
			clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
			clock-names = "uart", "clk_uart_baud0";
			pinctrl-names = "default";
			pinctrl-0 = <&uart1_data>;
			status = "disabled";
		};

		serial_2: serial@13820000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13820000 0x100>;
			interrupts = <0 111 0>;
			clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
			clock-names = "uart", "clk_uart_baud0";
			pinctrl-names = "default";
			pinctrl-0 = <&uart2_data>;
			status = "disabled";
		};

		i2c_0: i2c@13860000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13860000 0x100>;
			interrupts = <0 113 0>;
			clocks = <&cmu CLK_I2C0>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_bus>;
			status = "disabled";
		};

		i2c_1: i2c@13870000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13870000 0x100>;
			interrupts = <0 114 0>;
			clocks = <&cmu CLK_I2C1>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_bus>;
			status = "disabled";
		};

		i2c_2: i2c@13880000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13880000 0x100>;
			interrupts = <0 115 0>;
			clocks = <&cmu CLK_I2C2>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2_bus>;
			status = "disabled";
		};

		i2c_3: i2c@13890000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13890000 0x100>;
			interrupts = <0 116 0>;
			clocks = <&cmu CLK_I2C3>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c3_bus>;
			status = "disabled";
		};

		i2c_4: i2c@138A0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138A0000 0x100>;
			interrupts = <0 117 0>;
			clocks = <&cmu CLK_I2C4>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c4_bus>;
			status = "disabled";
		};

		i2c_5: i2c@138B0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138B0000 0x100>;
			interrupts = <0 118 0>;
			clocks = <&cmu CLK_I2C5>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c5_bus>;
			status = "disabled";
		};

		i2c_6: i2c@138C0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138C0000 0x100>;
			interrupts = <0 119 0>;
			clocks = <&cmu CLK_I2C6>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c6_bus>;
			status = "disabled";
		};

		i2c_7: i2c@138D0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138D0000 0x100>;
			interrupts = <0 120 0>;
			clocks = <&cmu CLK_I2C7>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c7_bus>;
			status = "disabled";
		};

		spi_0: spi@13920000 {
			compatible = "samsung,exynos4210-spi";
			reg = <0x13920000 0x100>;
			interrupts = <0 121 0>;
			dmas = <&pdma0 7>, <&pdma0 6>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
			clock-names = "spi", "spi_busclk0";
			samsung,spi-src-clk = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi0_bus>;
			status = "disabled";
		};

		spi_1: spi@13930000 {
			compatible = "samsung,exynos4210-spi";
			reg = <0x13930000 0x100>;
			interrupts = <0 122 0>;
			dmas = <&pdma1 7>, <&pdma1 6>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
			clock-names = "spi", "spi_busclk0";
			samsung,spi-src-clk = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi1_bus>;
			status = "disabled";
		};

		i2s2: i2s@13970000 {
			compatible = "samsung,s3c6410-i2s";
			reg = <0x13970000 0x100>;
			interrupts = <0 126 0>;
			clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
			clock-names = "iis", "i2s_opclk0";
			dmas = <&pdma0 14>, <&pdma0 13>;
			dma-names = "tx", "rx";
			pinctrl-0 = <&i2s2_bus>;
			pinctrl-names = "default";
			status = "disabled";
		};

		pwm: pwm@139D0000 {
			compatible = "samsung,exynos4210-pwm";
			reg = <0x139D0000 0x1000>;
			interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
				     <0 107 0>, <0 108 0>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		pmu {
			compatible = "arm,cortex-a7-pmu";
			interrupts = <0 18 0>, <0 19 0>;
		};

		ppmu_dmc0: ppmu_dmc0@106a0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x106a0000 0x2000>;
			status = "disabled";
		};

		ppmu_dmc1: ppmu_dmc1@106b0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x106b0000 0x2000>;
			status = "disabled";
		};

		ppmu_cpu: ppmu_cpu@106c0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x106c0000 0x2000>;
			status = "disabled";
		};

		ppmu_rightbus: ppmu_rightbus@112a0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x112a0000 0x2000>;
			clocks = <&cmu CLK_PPMURIGHT>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_leftbus: ppmu_leftbus0@116a0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x116a0000 0x2000>;
			clocks = <&cmu CLK_PPMULEFT>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_camif: ppmu_camif@11ac0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x11ac0000 0x2000>;
			clocks = <&cmu CLK_PPMUCAMIF>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_lcd0: ppmu_lcd0@11e40000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x11e40000 0x2000>;
			clocks = <&cmu CLK_PPMULCD0>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_fsys: ppmu_fsys@12630000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x12630000 0x2000>;
			clocks = <&cmu CLK_PPMUFILE>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_g3d: ppmu_g3d@13220000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x13220000 0x2000>;
			clocks = <&cmu CLK_PPMUG3D>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_mfc: ppmu_mfc@13660000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x13660000 0x2000>;
			clocks = <&cmu CLK_PPMUMFC_L>;
			clock-names = "ppmu";
			status = "disabled";
		};
	};
};

#include "exynos3250-pinctrl.dtsi"
Commit	Line	Data
5a992a9c TF	1	/*
	2	* Samsung's Exynos3250 SoC device tree source
	3	*
	4	* Copyright (c) 2014 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
	8	* based board files can include this file and provide values for board specfic
	9	* bindings.
	10	*
	11	* Note: This file does not include device nodes for all the controllers in
	12	* Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
	13	* nodes can be added to this file.
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19
	20	#include "skeleton.dtsi"
9843a223	21	#include "exynos4-cpu-thermal.dtsi"
1462b137	22	#include "exynos-syscon-restart.dtsi"
5a992a9c TF	23	#include <dt-bindings/clock/exynos3250.h>
	24
	25	/ {
	26	compatible = "samsung,exynos3250";
	27	interrupt-parent = <&gic>;
	28
	29	aliases {
	30	pinctrl0 = &pinctrl_0;
	31	pinctrl1 = &pinctrl_1;
	32	mshc0 = &mshc_0;
	33	mshc1 = &mshc_1;
92173e6a	34	mshc2 = &mshc_2;
5a992a9c TF	35	spi0 = &spi_0;
	36	spi1 = &spi_1;
	37	i2c0 = &i2c_0;
	38	i2c1 = &i2c_1;
	39	i2c2 = &i2c_2;
	40	i2c3 = &i2c_3;
	41	i2c4 = &i2c_4;
	42	i2c5 = &i2c_5;
	43	i2c6 = &i2c_6;
	44	i2c7 = &i2c_7;
1e64f48e TF	45	serial0 = &serial_0;
1e64f48e TF	46	serial1 = &serial_1;
ecaba514	47	serial2 = &serial_2;
5a992a9c TF	48	};
	49
	50	cpus {
	51	#address-cells = <1>;
	52	#size-cells = <0>;
	53
	54	cpu0: cpu@0 {
	55	device_type = "cpu";
	56	compatible = "arm,cortex-a7";
	57	reg = <0>;
	58	clock-frequency = <1000000000>;
48816aff CC	59	clocks = <&cmu CLK_ARM_CLK>;
48816aff CC	60	clock-names = "cpu";
5600f8cc	61	#cooling-cells = <2>;
48816aff CC	62
	63	operating-points = <
	64	1000000 1150000
	65	900000 1112500
	66	800000 1075000
	67	700000 1037500
	68	600000 1000000
	69	500000 962500
	70	400000 925000
	71	300000 887500
	72	200000 850000
	73	100000 850000
	74	>;
5a992a9c TF	75	};
	76
	77	cpu1: cpu@1 {
	78	device_type = "cpu";
	79	compatible = "arm,cortex-a7";
	80	reg = <1>;
	81	clock-frequency = <1000000000>;
	82	};
	83	};
	84
	85	soc: soc {
	86	compatible = "simple-bus";
	87	#address-cells = <1>;
	88	#size-cells = <1>;
	89	ranges;
	90
	91	fixed-rate-clocks {
	92	#address-cells = <1>;
	93	#size-cells = <0>;
	94
	95	xusbxti: clock@0 {
	96	compatible = "fixed-clock";
	97	#address-cells = <1>;
	98	#size-cells = <0>;
	99	reg = <0>;
	100	clock-frequency = <0>;
	101	#clock-cells = <0>;
	102	clock-output-names = "xusbxti";
	103	};
	104
	105	xxti: clock@1 {
	106	compatible = "fixed-clock";
	107	reg = <1>;
	108	clock-frequency = <0>;
	109	#clock-cells = <0>;
	110	clock-output-names = "xxti";
	111	};
	112
	113	xtcxo: clock@2 {
	114	compatible = "fixed-clock";
	115	reg = <2>;
	116	clock-frequency = <0>;
	117	#clock-cells = <0>;
	118	clock-output-names = "xtcxo";
	119	};
	120	};
	121
	122	sysram@02020000 {
	123	compatible = "mmio-sram";
	124	reg = <0x02020000 0x40000>;
	125	#address-cells = <1>;
	126	#size-cells = <1>;
	127	ranges = <0 0x02020000 0x40000>;
	128
	129	smp-sysram@0 {
	130	compatible = "samsung,exynos4210-sysram";
	131	reg = <0x0 0x1000>;
	132	};
	133
	134	smp-sysram@3f000 {
	135	compatible = "samsung,exynos4210-sysram-ns";
	136	reg = <0x3f000 0x1000>;
	137	};
	138	};
139
140	chipid@10000000 {
141	compatible = "samsung,exynos4210-chipid";
142	reg = <0x10000000 0x100>;
143	};
144
145	sys_reg: syscon@10010000 {
146	compatible = "samsung,exynos3-sysreg", "syscon";
147	reg = <0x10010000 0x400>;
148	};
149
25023926 CC	150	pmu_system_controller: system-controller@10020000 {
	151	compatible = "samsung,exynos3250-pmu", "syscon";
	152	reg = <0x10020000 0x4000>;
8b283c02 MZ	153	interrupt-controller;
	154	#interrupt-cells = <3>;
	155	interrupt-parent = <&gic>;
25023926 CC	156	};
25023926 CC	157
bb72cade	158	mipi_phy: video-phy {
9fab9d6a	159	compatible = "samsung,s5pv210-mipi-video-phy";
9fab9d6a	160	#phy-cells = <1>;
1342ff45	161	syscon = <&pmu_system_controller>;
9fab9d6a ID	162	};
9fab9d6a ID	163
5a992a9c TF	164	pd_cam: cam-power-domain@10023C00 {
	165	compatible = "samsung,exynos4210-pd";
	166	reg = <0x10023C00 0x20>;
0da65870	167	#power-domain-cells = <0>;
5a992a9c TF	168	};
	169
	170	pd_mfc: mfc-power-domain@10023C40 {
	171	compatible = "samsung,exynos4210-pd";
	172	reg = <0x10023C40 0x20>;
0da65870	173	#power-domain-cells = <0>;
5a992a9c TF	174	};
	175
	176	pd_g3d: g3d-power-domain@10023C60 {
	177	compatible = "samsung,exynos4210-pd";
	178	reg = <0x10023C60 0x20>;
0da65870	179	#power-domain-cells = <0>;
5a992a9c TF	180	};
	181
	182	pd_lcd0: lcd0-power-domain@10023C80 {
	183	compatible = "samsung,exynos4210-pd";
	184	reg = <0x10023C80 0x20>;
0da65870	185	#power-domain-cells = <0>;
5a992a9c TF	186	};
	187
	188	pd_isp: isp-power-domain@10023CA0 {
	189	compatible = "samsung,exynos4210-pd";
	190	reg = <0x10023CA0 0x20>;
0da65870	191	#power-domain-cells = <0>;
5a992a9c TF	192	};
	193
	194	cmu: clock-controller@10030000 {
	195	compatible = "samsung,exynos3250-cmu";
	196	reg = <0x10030000 0x20000>;
	197	#clock-cells = <1>;
52005dec BM	198	assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
	199	<&cmu CLK_MOUT_ACLK_266_SUB>;
	200	assigned-clock-parents = <&cmu CLK_FIN_PLL>,
	201	<&cmu CLK_FIN_PLL>;
5a992a9c TF	202	};
5a992a9c TF	203
d0e73eaf KK	204	cmu_dmc: clock-controller@105C0000 {
	205	compatible = "samsung,exynos3250-cmu-dmc";
	206	reg = <0x105C0000 0x2000>;
	207	#clock-cells = <1>;
	208	};
	209
5a992a9c	210	rtc: rtc@10070000 {
062f49c4	211	compatible = "samsung,s3c6410-rtc";
5a992a9c TF	212	reg = <0x10070000 0x100>;
5a992a9c TF	213	interrupts = <0 73 0>, <0 74 0>;
8b283c02	214	interrupt-parent = <&pmu_system_controller>;
5a992a9c TF	215	status = "disabled";
	216	};
	217
9dfb3347 CC	218	tmu: tmu@100C0000 {
	219	compatible = "samsung,exynos3250-tmu";
	220	reg = <0x100C0000 0x100>;
	221	interrupts = <0 216 0>;
	222	clocks = <&cmu CLK_TMU_APBIF>;
	223	clock-names = "tmu_apbif";
9843a223	224	#include "exynos4412-tmu-sensor-conf.dtsi"
9dfb3347 CC	225	status = "disabled";
	226	};
	227
5a992a9c TF	228	gic: interrupt-controller@10481000 {
	229	compatible = "arm,cortex-a15-gic";
	230	#interrupt-cells = <3>;
	231	interrupt-controller;
	232	reg = <0x10481000 0x1000>,
	233	<0x10482000 0x1000>,
	234	<0x10484000 0x2000>,
	235	<0x10486000 0x2000>;
	236	interrupts = <1 9 0xf04>;
	237	};
	238
	239	mct@10050000 {
	240	compatible = "samsung,exynos4210-mct";
	241	reg = <0x10050000 0x800>;
	242	interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
	243	<0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
	244	clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
	245	clock-names = "fin_pll", "mct";
	246	};
	247
	248	pinctrl_1: pinctrl@11000000 {
	249	compatible = "samsung,exynos3250-pinctrl";
	250	reg = <0x11000000 0x1000>;
	251	interrupts = <0 225 0>;
	252
	253	wakeup-interrupt-controller {
	254	compatible = "samsung,exynos4210-wakeup-eint";
5a992a9c TF	255	interrupts = <0 48 0>;
	256	};
	257	};
	258
	259	pinctrl_0: pinctrl@11400000 {
	260	compatible = "samsung,exynos3250-pinctrl";
	261	reg = <0x11400000 0x1000>;
	262	interrupts = <0 240 0>;
	263	};
	264
c9c1adfe JA	265	jpeg: codec@11830000 {
	266	compatible = "samsung,exynos3250-jpeg";
	267	reg = <0x11830000 0x1000>;
	268	interrupts = <0 171 0>;
	269	clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
	270	clock-names = "jpeg", "sclk";
	271	power-domains = <&pd_cam>;
	272	assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
	273	assigned-clock-rates = <0>, <150000000>;
	274	assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
f5976ce5	275	iommus = <&sysmmu_jpeg>;
c9c1adfe JA	276	status = "disabled";
	277	};
	278
f5976ce5 MS	279	sysmmu_jpeg: sysmmu@11A60000 {
	280	compatible = "samsung,exynos-sysmmu";
	281	reg = <0x11a60000 0x1000>;
	282	interrupts = <0 156 0>, <0 161 0>;
	283	clock-names = "sysmmu", "master";
	284	clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
	285	power-domains = <&pd_cam>;
	286	#iommu-cells = <0>;
	287	};
	288
03b86c79 ID	289	fimd: fimd@11c00000 {
	290	compatible = "samsung,exynos3250-fimd";
	291	reg = <0x11c00000 0x30000>;
	292	interrupt-names = "fifo", "vsync", "lcd_sys";
	293	interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
	294	clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
	295	clock-names = "sclk_fimd", "fimd";
0da65870	296	power-domains = <&pd_lcd0>;
f5976ce5	297	iommus = <&sysmmu_fimd0>;
03b86c79 ID	298	samsung,sysreg = <&sys_reg>;
	299	status = "disabled";
	300	};
	301
025d8e13 ID	302	dsi_0: dsi@11C80000 {
	303	compatible = "samsung,exynos3250-mipi-dsi";
	304	reg = <0x11C80000 0x10000>;
	305	interrupts = <0 83 0>;
	306	samsung,phy-type = <0>;
0da65870	307	power-domains = <&pd_lcd0>;
025d8e13 ID	308	phys = <&mipi_phy 1>;
	309	phy-names = "dsim";
	310	clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
	311	clock-names = "bus_clk", "pll_clk";
	312	#address-cells = <1>;
	313	#size-cells = <0>;
	314	status = "disabled";
	315	};
	316
f5976ce5 MS	317	sysmmu_fimd0: sysmmu@11E20000 {
	318	compatible = "samsung,exynos-sysmmu";
	319	reg = <0x11e20000 0x1000>;
	320	interrupts = <0 80 0>, <0 81 0>;
	321	clock-names = "sysmmu", "master";
	322	clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
	323	power-domains = <&pd_lcd0>;
	324	#iommu-cells = <0>;
	325	};
	326
e0c6e929 JK	327	hsotg: hsotg@12480000 {
	328	compatible = "snps,dwc2";
	329	reg = <0x12480000 0x20000>;
	330	interrupts = <0 141 0>;
	331	clocks = <&cmu CLK_USBOTG>;
	332	clock-names = "otg";
	333	phys = <&exynos_usbphy 0>;
	334	phy-names = "usb2-phy";
	335	status = "disabled";
	336	};
	337
5a992a9c	338	mshc_0: mshc@12510000 {
b29dd5fa	339	compatible = "samsung,exynos5420-dw-mshc";
5a992a9c TF	340	reg = <0x12510000 0x1000>;
	341	interrupts = <0 142 0>;
	342	clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
	343	clock-names = "biu", "ciu";
	344	fifo-depth = <0x80>;
	345	#address-cells = <1>;
	346	#size-cells = <0>;
	347	status = "disabled";
	348	};
	349
	350	mshc_1: mshc@12520000 {
b29dd5fa	351	compatible = "samsung,exynos5420-dw-mshc";
5a992a9c TF	352	reg = <0x12520000 0x1000>;
	353	interrupts = <0 143 0>;
	354	clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
	355	clock-names = "biu", "ciu";
	356	fifo-depth = <0x80>;
	357	#address-cells = <1>;
	358	#size-cells = <0>;
	359	status = "disabled";
	360	};
	361
92173e6a CC	362	mshc_2: mshc@12530000 {
	363	compatible = "samsung,exynos5250-dw-mshc";
	364	reg = <0x12530000 0x1000>;
	365	interrupts = <0 144 0>;
	366	clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
	367	clock-names = "biu", "ciu";
	368	fifo-depth = <0x80>;
	369	#address-cells = <1>;
	370	#size-cells = <0>;
	371	status = "disabled";
	372	};
	373
11ab02b8 JK	374	exynos_usbphy: exynos-usbphy@125B0000 {
	375	compatible = "samsung,exynos3250-usb2-phy";
	376	reg = <0x125B0000 0x100>;
	377	samsung,pmureg-phandle = <&pmu_system_controller>;
	378	clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
	379	clock-names = "phy", "ref";
	380	#phy-cells = <1>;
	381	status = "disabled";
	382	};
	383
5a992a9c	384	amba {
2ef7d5f3	385	compatible = "simple-bus";
5a992a9c TF	386	#address-cells = <1>;
5a992a9c TF	387	#size-cells = <1>;
5a992a9c TF	388	ranges;
	389
	390	pdma0: pdma@12680000 {
	391	compatible = "arm,pl330", "arm,primecell";
	392	reg = <0x12680000 0x1000>;
	393	interrupts = <0 138 0>;
	394	clocks = <&cmu CLK_PDMA0>;
	395	clock-names = "apb_pclk";
	396	#dma-cells = <1>;
	397	#dma-channels = <8>;
	398	#dma-requests = <32>;
	399	};
	400
	401	pdma1: pdma@12690000 {
	402	compatible = "arm,pl330", "arm,primecell";
	403	reg = <0x12690000 0x1000>;
	404	interrupts = <0 139 0>;
	405	clocks = <&cmu CLK_PDMA1>;
	406	clock-names = "apb_pclk";
	407	#dma-cells = <1>;
	408	#dma-channels = <8>;
	409	#dma-requests = <32>;
	410	};
	411	};
	412
	413	adc: adc@126C0000 {
e6ca2d84 CC	414	compatible = "samsung,exynos3250-adc",
e6ca2d84 CC	415	"samsung,exynos-adc-v2";
db9bf4d6	416	reg = <0x126C0000 0x100>;
5a992a9c	417	interrupts = <0 137 0>;
e6ca2d84	418	clock-names = "adc", "sclk";
5a992a9c TF	419	clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
	420	#io-channel-cells = <1>;
	421	io-channel-ranges;
db9bf4d6	422	samsung,syscon-phandle = <&pmu_system_controller>;
5a992a9c TF	423	status = "disabled";
	424	};
	425
752d3a23 JA	426	mfc: codec@13400000 {
	427	compatible = "samsung,mfc-v7";
	428	reg = <0x13400000 0x10000>;
	429	interrupts = <0 102 0>;
	430	clock-names = "mfc", "sclk_mfc";
	431	clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
0da65870	432	power-domains = <&pd_mfc>;
f5976ce5	433	iommus = <&sysmmu_mfc>;
752d3a23 JA	434	status = "disabled";
	435	};
	436
f5976ce5 MS	437	sysmmu_mfc: sysmmu@13620000 {
	438	compatible = "samsung,exynos-sysmmu";
	439	reg = <0x13620000 0x1000>;
	440	interrupts = <0 96 0>, <0 98 0>;
	441	clock-names = "sysmmu", "master";
	442	clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
	443	power-domains = <&pd_mfc>;
	444	#iommu-cells = <0>;
	445	};
	446
5a992a9c TF	447	serial_0: serial@13800000 {
	448	compatible = "samsung,exynos4210-uart";
	449	reg = <0x13800000 0x100>;
	450	interrupts = <0 109 0>;
	451	clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
	452	clock-names = "uart", "clk_uart_baud0";
a9408a6b CC	453	pinctrl-names = "default";
a9408a6b CC	454	pinctrl-0 = <&uart0_data &uart0_fctl>;
5a992a9c TF	455	status = "disabled";
	456	};
	457
	458	serial_1: serial@13810000 {
	459	compatible = "samsung,exynos4210-uart";
	460	reg = <0x13810000 0x100>;
	461	interrupts = <0 110 0>;
	462	clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
	463	clock-names = "uart", "clk_uart_baud0";
a9408a6b CC	464	pinctrl-names = "default";
a9408a6b CC	465	pinctrl-0 = <&uart1_data>;
5a992a9c TF	466	status = "disabled";
	467	};
	468
ecaba514 PD	469	serial_2: serial@13820000 {
	470	compatible = "samsung,exynos4210-uart";
	471	reg = <0x13820000 0x100>;
	472	interrupts = <0 111 0>;
	473	clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
	474	clock-names = "uart", "clk_uart_baud0";
	475	pinctrl-names = "default";
	476	pinctrl-0 = <&uart2_data>;
	477	status = "disabled";
	478	};
	479
5a992a9c TF	480	i2c_0: i2c@13860000 {
	481	#address-cells = <1>;
	482	#size-cells = <0>;
	483	compatible = "samsung,s3c2440-i2c";
	484	reg = <0x13860000 0x100>;
	485	interrupts = <0 113 0>;
	486	clocks = <&cmu CLK_I2C0>;
	487	clock-names = "i2c";
	488	pinctrl-names = "default";
	489	pinctrl-0 = <&i2c0_bus>;
	490	status = "disabled";
	491	};
	492
	493	i2c_1: i2c@13870000 {
	494	#address-cells = <1>;
	495	#size-cells = <0>;
	496	compatible = "samsung,s3c2440-i2c";
	497	reg = <0x13870000 0x100>;
	498	interrupts = <0 114 0>;
	499	clocks = <&cmu CLK_I2C1>;
	500	clock-names = "i2c";
	501	pinctrl-names = "default";
	502	pinctrl-0 = <&i2c1_bus>;
	503	status = "disabled";
	504	};
	505
	506	i2c_2: i2c@13880000 {
	507	#address-cells = <1>;
	508	#size-cells = <0>;
	509	compatible = "samsung,s3c2440-i2c";
	510	reg = <0x13880000 0x100>;
	511	interrupts = <0 115 0>;
	512	clocks = <&cmu CLK_I2C2>;
	513	clock-names = "i2c";
	514	pinctrl-names = "default";
	515	pinctrl-0 = <&i2c2_bus>;
	516	status = "disabled";
	517	};
	518
	519	i2c_3: i2c@13890000 {
	520	#address-cells = <1>;
	521	#size-cells = <0>;
	522	compatible = "samsung,s3c2440-i2c";
	523	reg = <0x13890000 0x100>;
	524	interrupts = <0 116 0>;
	525	clocks = <&cmu CLK_I2C3>;
	526	clock-names = "i2c";
	527	pinctrl-names = "default";
	528	pinctrl-0 = <&i2c3_bus>;
	529	status = "disabled";
	530	};
	531
	532	i2c_4: i2c@138A0000 {
	533	#address-cells = <1>;
	534	#size-cells = <0>;
	535	compatible = "samsung,s3c2440-i2c";
	536	reg = <0x138A0000 0x100>;
	537	interrupts = <0 117 0>;
	538	clocks = <&cmu CLK_I2C4>;
	539	clock-names = "i2c";
	540	pinctrl-names = "default";
	541	pinctrl-0 = <&i2c4_bus>;
	542	status = "disabled";
	543	};
544
545	i2c_5: i2c@138B0000 {
546	#address-cells = <1>;
547	#size-cells = <0>;
548	compatible = "samsung,s3c2440-i2c";
549	reg = <0x138B0000 0x100>;
550	interrupts = <0 118 0>;
551	clocks = <&cmu CLK_I2C5>;
552	clock-names = "i2c";
553	pinctrl-names = "default";
554	pinctrl-0 = <&i2c5_bus>;
555	status = "disabled";
556	};
557
558	i2c_6: i2c@138C0000 {
559	#address-cells = <1>;
560	#size-cells = <0>;
561	compatible = "samsung,s3c2440-i2c";
562	reg = <0x138C0000 0x100>;
563	interrupts = <0 119 0>;
564	clocks = <&cmu CLK_I2C6>;
565	clock-names = "i2c";
566	pinctrl-names = "default";
567	pinctrl-0 = <&i2c6_bus>;
568	status = "disabled";
569	};
570
571	i2c_7: i2c@138D0000 {
572	#address-cells = <1>;
573	#size-cells = <0>;
574	compatible = "samsung,s3c2440-i2c";
575	reg = <0x138D0000 0x100>;
576	interrupts = <0 120 0>;
577	clocks = <&cmu CLK_I2C7>;
578	clock-names = "i2c";
579	pinctrl-names = "default";
580	pinctrl-0 = <&i2c7_bus>;
581	status = "disabled";
582	};
583
584	spi_0: spi@13920000 {
585	compatible = "samsung,exynos4210-spi";
586	reg = <0x13920000 0x100>;
587	interrupts = <0 121 0>;
588	dmas = <&pdma0 7>, <&pdma0 6>;
589	dma-names = "tx", "rx";
590	#address-cells = <1>;
591	#size-cells = <0>;
592	clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
593	clock-names = "spi", "spi_busclk0";
594	samsung,spi-src-clk = <0>;
595	pinctrl-names = "default";
596	pinctrl-0 = <&spi0_bus>;
597	status = "disabled";
598	};
599
600	spi_1: spi@13930000 {
601	compatible = "samsung,exynos4210-spi";
602	reg = <0x13930000 0x100>;
603	interrupts = <0 122 0>;
604	dmas = <&pdma1 7>, <&pdma1 6>;
605	dma-names = "tx", "rx";
606	#address-cells = <1>;
607	#size-cells = <0>;
608	clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
609	clock-names = "spi", "spi_busclk0";
610	samsung,spi-src-clk = <0>;
611	pinctrl-names = "default";
612	pinctrl-0 = <&spi1_bus>;
613	status = "disabled";
614	};
615
ccaba452 TF	616	i2s2: i2s@13970000 {
	617	compatible = "samsung,s3c6410-i2s";
	618	reg = <0x13970000 0x100>;
	619	interrupts = <0 126 0>;
	620	clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
	621	clock-names = "iis", "i2s_opclk0";
	622	dmas = <&pdma0 14>, <&pdma0 13>;
	623	dma-names = "tx", "rx";
	624	pinctrl-0 = <&i2s2_bus>;
	625	pinctrl-names = "default";
	626	status = "disabled";
	627	};
	628
5a992a9c TF	629	pwm: pwm@139D0000 {
	630	compatible = "samsung,exynos4210-pwm";
	631	reg = <0x139D0000 0x1000>;
	632	interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
	633	<0 107 0>, <0 108 0>;
	634	#pwm-cells = <3>;
	635	status = "disabled";
	636	};
	637
	638	pmu {
	639	compatible = "arm,cortex-a7-pmu";
	640	interrupts = <0 18 0>, <0 19 0>;
	641	};
e4502367 CC	642
	643	ppmu_dmc0: ppmu_dmc0@106a0000 {
	644	compatible = "samsung,exynos-ppmu";
	645	reg = <0x106a0000 0x2000>;
	646	status = "disabled";
	647	};
	648
	649	ppmu_dmc1: ppmu_dmc1@106b0000 {
	650	compatible = "samsung,exynos-ppmu";
	651	reg = <0x106b0000 0x2000>;
	652	status = "disabled";
	653	};
	654
	655	ppmu_cpu: ppmu_cpu@106c0000 {
	656	compatible = "samsung,exynos-ppmu";
	657	reg = <0x106c0000 0x2000>;
	658	status = "disabled";
	659	};
	660
	661	ppmu_rightbus: ppmu_rightbus@112a0000 {
	662	compatible = "samsung,exynos-ppmu";
	663	reg = <0x112a0000 0x2000>;
	664	clocks = <&cmu CLK_PPMURIGHT>;
	665	clock-names = "ppmu";
	666	status = "disabled";
	667	};
	668
	669	ppmu_leftbus: ppmu_leftbus0@116a0000 {
	670	compatible = "samsung,exynos-ppmu";
	671	reg = <0x116a0000 0x2000>;
	672	clocks = <&cmu CLK_PPMULEFT>;
	673	clock-names = "ppmu";
	674	status = "disabled";
	675	};
	676
	677	ppmu_camif: ppmu_camif@11ac0000 {
	678	compatible = "samsung,exynos-ppmu";
	679	reg = <0x11ac0000 0x2000>;
	680	clocks = <&cmu CLK_PPMUCAMIF>;
	681	clock-names = "ppmu";
	682	status = "disabled";
	683	};
	684
	685	ppmu_lcd0: ppmu_lcd0@11e40000 {
	686	compatible = "samsung,exynos-ppmu";
	687	reg = <0x11e40000 0x2000>;
	688	clocks = <&cmu CLK_PPMULCD0>;
	689	clock-names = "ppmu";
	690	status = "disabled";
	691	};
	692
	693	ppmu_fsys: ppmu_fsys@12630000 {
	694	compatible = "samsung,exynos-ppmu";
	695	reg = <0x12630000 0x2000>;
	696	clocks = <&cmu CLK_PPMUFILE>;
	697	clock-names = "ppmu";
	698	status = "disabled";
	699	};
	700
	701	ppmu_g3d: ppmu_g3d@13220000 {
	702	compatible = "samsung,exynos-ppmu";
	703	reg = <0x13220000 0x2000>;
	704	clocks = <&cmu CLK_PPMUG3D>;
	705	clock-names = "ppmu";
706	status = "disabled";
707	};
708
709	ppmu_mfc: ppmu_mfc@13660000 {
710	compatible = "samsung,exynos-ppmu";
711	reg = <0x13660000 0x2000>;
712	clocks = <&cmu CLK_PPMUMFC_L>;
713	clock-names = "ppmu";
714	status = "disabled";
715	};
5a992a9c TF	716	};
	717	};
	718
	719	#include "exynos3250-pinctrl.dtsi"