projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 5a992a9c TF |
1 | /* |
| 2 | * Samsung's Exynos3250 SoC device tree source | |
| 3 | * | |
| 4 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. | |
| 5 | * http://www.samsung.com | |
| 6 | * | |
| 7 | * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 | |
| 8 | * based board files can include this file and provide values for board specfic | |
| 9 | * bindings. | |
| 10 | * | |
| 11 | * Note: This file does not include device nodes for all the controllers in | |
| 12 | * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional | |
| 13 | * nodes can be added to this file. | |
| 14 | * | |
| 15 | * This program is free software; you can redistribute it and/or modify | |
| 16 | * it under the terms of the GNU General Public License version 2 as | |
| 17 | * published by the Free Software Foundation. | |
| 18 | */ | |
| 19 | ||
| 20 | #include "skeleton.dtsi" | |
| 21 | #include <dt-bindings/clock/exynos3250.h> | |
| 22 | ||
| 23 | / { | |
| 24 | compatible = "samsung,exynos3250"; | |
| 25 | interrupt-parent = <&gic>; | |
| 26 | ||
| 27 | aliases { | |
| 28 | pinctrl0 = &pinctrl_0; | |
| 29 | pinctrl1 = &pinctrl_1; | |
| 30 | mshc0 = &mshc_0; | |
| 31 | mshc1 = &mshc_1; | |
| 32 | spi0 = &spi_0; | |
| 33 | spi1 = &spi_1; | |
| 34 | i2c0 = &i2c_0; | |
| 35 | i2c1 = &i2c_1; | |
| 36 | i2c2 = &i2c_2; | |
| 37 | i2c3 = &i2c_3; | |
| 38 | i2c4 = &i2c_4; | |
| 39 | i2c5 = &i2c_5; | |
| 40 | i2c6 = &i2c_6; | |
| 41 | i2c7 = &i2c_7; | |
| 1e64f48e TF |
42 | serial0 = &serial_0; |
| 43 | serial1 = &serial_1; | |
| 5a992a9c TF |
44 | }; |
| 45 | ||
| 46 | cpus { | |
| 47 | #address-cells = <1>; | |
| 48 | #size-cells = <0>; | |
| 49 | ||
| 50 | cpu0: cpu@0 { | |
| 51 | device_type = "cpu"; | |
| 52 | compatible = "arm,cortex-a7"; | |
| 53 | reg = <0>; | |
| 54 | clock-frequency = <1000000000>; | |
| 55 | }; | |
| 56 | ||
| 57 | cpu1: cpu@1 { | |
| 58 | device_type = "cpu"; | |
| 59 | compatible = "arm,cortex-a7"; | |
| 60 | reg = <1>; | |
| 61 | clock-frequency = <1000000000>; | |
| 62 | }; | |
| 63 | }; | |
| 64 | ||
| 65 | soc: soc { | |
| 66 | compatible = "simple-bus"; | |
| 67 | #address-cells = <1>; | |
| 68 | #size-cells = <1>; | |
| 69 | ranges; | |
| 70 | ||
| 71 | fixed-rate-clocks { | |
| 72 | #address-cells = <1>; | |
| 73 | #size-cells = <0>; | |
| 74 | ||
| 75 | xusbxti: clock@0 { | |
| 76 | compatible = "fixed-clock"; | |
| 77 | #address-cells = <1>; | |
| 78 | #size-cells = <0>; | |
| 79 | reg = <0>; | |
| 80 | clock-frequency = <0>; | |
| 81 | #clock-cells = <0>; | |
| 82 | clock-output-names = "xusbxti"; | |
| 83 | }; | |
| 84 | ||
| 85 | xxti: clock@1 { | |
| 86 | compatible = "fixed-clock"; | |
| 87 | reg = <1>; | |
| 88 | clock-frequency = <0>; | |
| 89 | #clock-cells = <0>; | |
| 90 | clock-output-names = "xxti"; | |
| 91 | }; | |
| 92 | ||
| 93 | xtcxo: clock@2 { | |
| 94 | compatible = "fixed-clock"; | |
| 95 | reg = <2>; | |
| 96 | clock-frequency = <0>; | |
| 97 | #clock-cells = <0>; | |
| 98 | clock-output-names = "xtcxo"; | |
| 99 | }; | |
| 100 | }; | |
| 101 | ||
| 102 | sysram@02020000 { | |
| 103 | compatible = "mmio-sram"; | |
| 104 | reg = <0x02020000 0x40000>; | |
| 105 | #address-cells = <1>; | |
| 106 | #size-cells = <1>; | |
| 107 | ranges = <0 0x02020000 0x40000>; | |
| 108 | ||
| 109 | smp-sysram@0 { | |
| 110 | compatible = "samsung,exynos4210-sysram"; | |
| 111 | reg = <0x0 0x1000>; | |
| 112 | }; | |
| 113 | ||
| 114 | smp-sysram@3f000 { | |
| 115 | compatible = "samsung,exynos4210-sysram-ns"; | |
| 116 | reg = <0x3f000 0x1000>; | |
| 117 | }; | |
| 118 | }; | |
| 119 | ||
| 120 | chipid@10000000 { | |
| 121 | compatible = "samsung,exynos4210-chipid"; | |
| 122 | reg = <0x10000000 0x100>; | |
| 123 | }; | |
| 124 | ||
| 125 | sys_reg: syscon@10010000 { | |
| 126 | compatible = "samsung,exynos3-sysreg", "syscon"; | |
| 127 | reg = <0x10010000 0x400>; | |
| 128 | }; | |
| 129 | ||
| 25023926 CC |
130 | pmu_system_controller: system-controller@10020000 { |
| 131 | compatible = "samsung,exynos3250-pmu", "syscon"; | |
| 132 | reg = <0x10020000 0x4000>; | |
| 133 | }; | |
| 134 | ||
| 5a992a9c TF |
135 | pd_cam: cam-power-domain@10023C00 { |
| 136 | compatible = "samsung,exynos4210-pd"; | |
| 137 | reg = <0x10023C00 0x20>; | |
| 138 | }; | |
| 139 | ||
| 140 | pd_mfc: mfc-power-domain@10023C40 { | |
| 141 | compatible = "samsung,exynos4210-pd"; | |
| 142 | reg = <0x10023C40 0x20>; | |
| 143 | }; | |
| 144 | ||
| 145 | pd_g3d: g3d-power-domain@10023C60 { | |
| 146 | compatible = "samsung,exynos4210-pd"; | |
| 147 | reg = <0x10023C60 0x20>; | |
| 148 | }; | |
| 149 | ||
| 150 | pd_lcd0: lcd0-power-domain@10023C80 { | |
| 151 | compatible = "samsung,exynos4210-pd"; | |
| 152 | reg = <0x10023C80 0x20>; | |
| 153 | }; | |
| 154 | ||
| 155 | pd_isp: isp-power-domain@10023CA0 { | |
| 156 | compatible = "samsung,exynos4210-pd"; | |
| 157 | reg = <0x10023CA0 0x20>; | |
| 158 | }; | |
| 159 | ||
| 160 | cmu: clock-controller@10030000 { | |
| 161 | compatible = "samsung,exynos3250-cmu"; | |
| 162 | reg = <0x10030000 0x20000>; | |
| 163 | #clock-cells = <1>; | |
| 164 | }; | |
| 165 | ||
| 166 | rtc: rtc@10070000 { | |
| 167 | compatible = "samsung,s3c6410-rtc"; | |
| 168 | reg = <0x10070000 0x100>; | |
| 169 | interrupts = <0 73 0>, <0 74 0>; | |
| 170 | status = "disabled"; | |
| 171 | }; | |
| 172 | ||
| 9dfb3347 CC |
173 | tmu: tmu@100C0000 { |
| 174 | compatible = "samsung,exynos3250-tmu"; | |
| 175 | reg = <0x100C0000 0x100>; | |
| 176 | interrupts = <0 216 0>; | |
| 177 | clocks = <&cmu CLK_TMU_APBIF>; | |
| 178 | clock-names = "tmu_apbif"; | |
| 179 | status = "disabled"; | |
| 180 | }; | |
| 181 | ||
| 5a992a9c TF |
182 | gic: interrupt-controller@10481000 { |
| 183 | compatible = "arm,cortex-a15-gic"; | |
| 184 | #interrupt-cells = <3>; | |
| 185 | interrupt-controller; | |
| 186 | reg = <0x10481000 0x1000>, | |
| 187 | <0x10482000 0x1000>, | |
| 188 | <0x10484000 0x2000>, | |
| 189 | <0x10486000 0x2000>; | |
| 190 | interrupts = <1 9 0xf04>; | |
| 191 | }; | |
| 192 | ||
| 193 | mct@10050000 { | |
| 194 | compatible = "samsung,exynos4210-mct"; | |
| 195 | reg = <0x10050000 0x800>; | |
| 196 | interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, | |
| 197 | <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; | |
| 198 | clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; | |
| 199 | clock-names = "fin_pll", "mct"; | |
| 200 | }; | |
| 201 | ||
| 202 | pinctrl_1: pinctrl@11000000 { | |
| 203 | compatible = "samsung,exynos3250-pinctrl"; | |
| 204 | reg = <0x11000000 0x1000>; | |
| 205 | interrupts = <0 225 0>; | |
| 206 | ||
| 207 | wakeup-interrupt-controller { | |
| 208 | compatible = "samsung,exynos4210-wakeup-eint"; | |
| 5a992a9c TF |
209 | interrupts = <0 48 0>; |
| 210 | }; | |
| 211 | }; | |
| 212 | ||
| 213 | pinctrl_0: pinctrl@11400000 { | |
| 214 | compatible = "samsung,exynos3250-pinctrl"; | |
| 215 | reg = <0x11400000 0x1000>; | |
| 216 | interrupts = <0 240 0>; | |
| 217 | }; | |
| 218 | ||
| 03b86c79 ID |
219 | fimd: fimd@11c00000 { |
| 220 | compatible = "samsung,exynos3250-fimd"; | |
| 221 | reg = <0x11c00000 0x30000>; | |
| 222 | interrupt-names = "fifo", "vsync", "lcd_sys"; | |
| 223 | interrupts = <0 84 0>, <0 85 0>, <0 86 0>; | |
| 224 | clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; | |
| 225 | clock-names = "sclk_fimd", "fimd"; | |
| 226 | samsung,power-domain = <&pd_lcd0>; | |
| 227 | samsung,sysreg = <&sys_reg>; | |
| 228 | status = "disabled"; | |
| 229 | }; | |
| 230 | ||
| 5a992a9c TF |
231 | mshc_0: mshc@12510000 { |
| 232 | compatible = "samsung,exynos5250-dw-mshc"; | |
| 233 | reg = <0x12510000 0x1000>; | |
| 234 | interrupts = <0 142 0>; | |
| 235 | clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; | |
| 236 | clock-names = "biu", "ciu"; | |
| 237 | fifo-depth = <0x80>; | |
| 238 | #address-cells = <1>; | |
| 239 | #size-cells = <0>; | |
| 240 | status = "disabled"; | |
| 241 | }; | |
| 242 | ||
| 243 | mshc_1: mshc@12520000 { | |
| 244 | compatible = "samsung,exynos5250-dw-mshc"; | |
| 245 | reg = <0x12520000 0x1000>; | |
| 246 | interrupts = <0 143 0>; | |
| 247 | clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; | |
| 248 | clock-names = "biu", "ciu"; | |
| 249 | fifo-depth = <0x80>; | |
| 250 | #address-cells = <1>; | |
| 251 | #size-cells = <0>; | |
| 252 | status = "disabled"; | |
| 253 | }; | |
| 254 | ||
| 255 | amba { | |
| 256 | compatible = "arm,amba-bus"; | |
| 257 | #address-cells = <1>; | |
| 258 | #size-cells = <1>; | |
| 5a992a9c TF |
259 | ranges; |
| 260 | ||
| 261 | pdma0: pdma@12680000 { | |
| 262 | compatible = "arm,pl330", "arm,primecell"; | |
| 263 | reg = <0x12680000 0x1000>; | |
| 264 | interrupts = <0 138 0>; | |
| 265 | clocks = <&cmu CLK_PDMA0>; | |
| 266 | clock-names = "apb_pclk"; | |
| 267 | #dma-cells = <1>; | |
| 268 | #dma-channels = <8>; | |
| 269 | #dma-requests = <32>; | |
| 270 | }; | |
| 271 | ||
| 272 | pdma1: pdma@12690000 { | |
| 273 | compatible = "arm,pl330", "arm,primecell"; | |
| 274 | reg = <0x12690000 0x1000>; | |
| 275 | interrupts = <0 139 0>; | |
| 276 | clocks = <&cmu CLK_PDMA1>; | |
| 277 | clock-names = "apb_pclk"; | |
| 278 | #dma-cells = <1>; | |
| 279 | #dma-channels = <8>; | |
| 280 | #dma-requests = <32>; | |
| 281 | }; | |
| 282 | }; | |
| 283 | ||
| 284 | adc: adc@126C0000 { | |
| e6ca2d84 CC |
285 | compatible = "samsung,exynos3250-adc", |
| 286 | "samsung,exynos-adc-v2"; | |
| 5a992a9c TF |
287 | reg = <0x126C0000 0x100>, <0x10020718 0x4>; |
| 288 | interrupts = <0 137 0>; | |
| e6ca2d84 | 289 | clock-names = "adc", "sclk"; |
| 5a992a9c TF |
290 | clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; |
| 291 | #io-channel-cells = <1>; | |
| 292 | io-channel-ranges; | |
| 293 | status = "disabled"; | |
| 294 | }; | |
| 295 | ||
| 296 | serial_0: serial@13800000 { | |
| 297 | compatible = "samsung,exynos4210-uart"; | |
| 298 | reg = <0x13800000 0x100>; | |
| 299 | interrupts = <0 109 0>; | |
| 300 | clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; | |
| 301 | clock-names = "uart", "clk_uart_baud0"; | |
| a9408a6b CC |
302 | pinctrl-names = "default"; |
| 303 | pinctrl-0 = <&uart0_data &uart0_fctl>; | |
| 5a992a9c TF |
304 | status = "disabled"; |
| 305 | }; | |
| 306 | ||
| 307 | serial_1: serial@13810000 { | |
| 308 | compatible = "samsung,exynos4210-uart"; | |
| 309 | reg = <0x13810000 0x100>; | |
| 310 | interrupts = <0 110 0>; | |
| 311 | clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; | |
| 312 | clock-names = "uart", "clk_uart_baud0"; | |
| a9408a6b CC |
313 | pinctrl-names = "default"; |
| 314 | pinctrl-0 = <&uart1_data>; | |
| 5a992a9c TF |
315 | status = "disabled"; |
| 316 | }; | |
| 317 | ||
| 318 | i2c_0: i2c@13860000 { | |
| 319 | #address-cells = <1>; | |
| 320 | #size-cells = <0>; | |
| 321 | compatible = "samsung,s3c2440-i2c"; | |
| 322 | reg = <0x13860000 0x100>; | |
| 323 | interrupts = <0 113 0>; | |
| 324 | clocks = <&cmu CLK_I2C0>; | |
| 325 | clock-names = "i2c"; | |
| 326 | pinctrl-names = "default"; | |
| 327 | pinctrl-0 = <&i2c0_bus>; | |
| 328 | status = "disabled"; | |
| 329 | }; | |
| 330 | ||
| 331 | i2c_1: i2c@13870000 { | |
| 332 | #address-cells = <1>; | |
| 333 | #size-cells = <0>; | |
| 334 | compatible = "samsung,s3c2440-i2c"; | |
| 335 | reg = <0x13870000 0x100>; | |
| 336 | interrupts = <0 114 0>; | |
| 337 | clocks = <&cmu CLK_I2C1>; | |
| 338 | clock-names = "i2c"; | |
| 339 | pinctrl-names = "default"; | |
| 340 | pinctrl-0 = <&i2c1_bus>; | |
| 341 | status = "disabled"; | |
| 342 | }; | |
| 343 | ||
| 344 | i2c_2: i2c@13880000 { | |
| 345 | #address-cells = <1>; | |
| 346 | #size-cells = <0>; | |
| 347 | compatible = "samsung,s3c2440-i2c"; | |
| 348 | reg = <0x13880000 0x100>; | |
| 349 | interrupts = <0 115 0>; | |
| 350 | clocks = <&cmu CLK_I2C2>; | |
| 351 | clock-names = "i2c"; | |
| 352 | pinctrl-names = "default"; | |
| 353 | pinctrl-0 = <&i2c2_bus>; | |
| 354 | status = "disabled"; | |
| 355 | }; | |
| 356 | ||
| 357 | i2c_3: i2c@13890000 { | |
| 358 | #address-cells = <1>; | |
| 359 | #size-cells = <0>; | |
| 360 | compatible = "samsung,s3c2440-i2c"; | |
| 361 | reg = <0x13890000 0x100>; | |
| 362 | interrupts = <0 116 0>; | |
| 363 | clocks = <&cmu CLK_I2C3>; | |
| 364 | clock-names = "i2c"; | |
| 365 | pinctrl-names = "default"; | |
| 366 | pinctrl-0 = <&i2c3_bus>; | |
| 367 | status = "disabled"; | |
| 368 | }; | |
| 369 | ||
| 370 | i2c_4: i2c@138A0000 { | |
| 371 | #address-cells = <1>; | |
| 372 | #size-cells = <0>; | |
| 373 | compatible = "samsung,s3c2440-i2c"; | |
| 374 | reg = <0x138A0000 0x100>; | |
| 375 | interrupts = <0 117 0>; | |
| 376 | clocks = <&cmu CLK_I2C4>; | |
| 377 | clock-names = "i2c"; | |
| 378 | pinctrl-names = "default"; | |
| 379 | pinctrl-0 = <&i2c4_bus>; | |
| 380 | status = "disabled"; | |
| 381 | }; | |
| 382 | ||
| 383 | i2c_5: i2c@138B0000 { | |
| 384 | #address-cells = <1>; | |
| 385 | #size-cells = <0>; | |
| 386 | compatible = "samsung,s3c2440-i2c"; | |
| 387 | reg = <0x138B0000 0x100>; | |
| 388 | interrupts = <0 118 0>; | |
| 389 | clocks = <&cmu CLK_I2C5>; | |
| 390 | clock-names = "i2c"; | |
| 391 | pinctrl-names = "default"; | |
| 392 | pinctrl-0 = <&i2c5_bus>; | |
| 393 | status = "disabled"; | |
| 394 | }; | |
| 395 | ||
| 396 | i2c_6: i2c@138C0000 { | |
| 397 | #address-cells = <1>; | |
| 398 | #size-cells = <0>; | |
| 399 | compatible = "samsung,s3c2440-i2c"; | |
| 400 | reg = <0x138C0000 0x100>; | |
| 401 | interrupts = <0 119 0>; | |
| 402 | clocks = <&cmu CLK_I2C6>; | |
| 403 | clock-names = "i2c"; | |
| 404 | pinctrl-names = "default"; | |
| 405 | pinctrl-0 = <&i2c6_bus>; | |
| 406 | status = "disabled"; | |
| 407 | }; | |
| 408 | ||
| 409 | i2c_7: i2c@138D0000 { | |
| 410 | #address-cells = <1>; | |
| 411 | #size-cells = <0>; | |
| 412 | compatible = "samsung,s3c2440-i2c"; | |
| 413 | reg = <0x138D0000 0x100>; | |
| 414 | interrupts = <0 120 0>; | |
| 415 | clocks = <&cmu CLK_I2C7>; | |
| 416 | clock-names = "i2c"; | |
| 417 | pinctrl-names = "default"; | |
| 418 | pinctrl-0 = <&i2c7_bus>; | |
| 419 | status = "disabled"; | |
| 420 | }; | |
| 421 | ||
| 422 | spi_0: spi@13920000 { | |
| 423 | compatible = "samsung,exynos4210-spi"; | |
| 424 | reg = <0x13920000 0x100>; | |
| 425 | interrupts = <0 121 0>; | |
| 426 | dmas = <&pdma0 7>, <&pdma0 6>; | |
| 427 | dma-names = "tx", "rx"; | |
| 428 | #address-cells = <1>; | |
| 429 | #size-cells = <0>; | |
| 430 | clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; | |
| 431 | clock-names = "spi", "spi_busclk0"; | |
| 432 | samsung,spi-src-clk = <0>; | |
| 433 | pinctrl-names = "default"; | |
| 434 | pinctrl-0 = <&spi0_bus>; | |
| 435 | status = "disabled"; | |
| 436 | }; | |
| 437 | ||
| 438 | spi_1: spi@13930000 { | |
| 439 | compatible = "samsung,exynos4210-spi"; | |
| 440 | reg = <0x13930000 0x100>; | |
| 441 | interrupts = <0 122 0>; | |
| 442 | dmas = <&pdma1 7>, <&pdma1 6>; | |
| 443 | dma-names = "tx", "rx"; | |
| 444 | #address-cells = <1>; | |
| 445 | #size-cells = <0>; | |
| 446 | clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; | |
| 447 | clock-names = "spi", "spi_busclk0"; | |
| 448 | samsung,spi-src-clk = <0>; | |
| 449 | pinctrl-names = "default"; | |
| 450 | pinctrl-0 = <&spi1_bus>; | |
| 451 | status = "disabled"; | |
| 452 | }; | |
| 453 | ||
| ccaba452 TF |
454 | i2s2: i2s@13970000 { |
| 455 | compatible = "samsung,s3c6410-i2s"; | |
| 456 | reg = <0x13970000 0x100>; | |
| 457 | interrupts = <0 126 0>; | |
| 458 | clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; | |
| 459 | clock-names = "iis", "i2s_opclk0"; | |
| 460 | dmas = <&pdma0 14>, <&pdma0 13>; | |
| 461 | dma-names = "tx", "rx"; | |
| 462 | pinctrl-0 = <&i2s2_bus>; | |
| 463 | pinctrl-names = "default"; | |
| 464 | status = "disabled"; | |
| 465 | }; | |
| 466 | ||
| 5a992a9c TF |
467 | pwm: pwm@139D0000 { |
| 468 | compatible = "samsung,exynos4210-pwm"; | |
| 469 | reg = <0x139D0000 0x1000>; | |
| 470 | interrupts = <0 104 0>, <0 105 0>, <0 106 0>, | |
| 471 | <0 107 0>, <0 108 0>; | |
| 472 | #pwm-cells = <3>; | |
| 473 | status = "disabled"; | |
| 474 | }; | |
| 475 | ||
| 476 | pmu { | |
| 477 | compatible = "arm,cortex-a7-pmu"; | |
| 478 | interrupts = <0 18 0>, <0 19 0>; | |
| 479 | }; | |
| 480 | }; | |
| 481 | }; | |
| 482 | ||
| 483 | #include "exynos3250-pinctrl.dtsi" |