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ARM: dts: Add exynos_usbphy node for exynos3250
[deliverable/linux.git] / arch / arm / boot / dts / exynos3250.dtsi
CommitLineData
5a992a9c
TF		 1/*
2 * Samsung's Exynos3250 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include "skeleton.dtsi"
21#include <dt-bindings/clock/exynos3250.h>
22
23/ {
24 compatible = "samsung,exynos3250";
25 interrupt-parent = <&gic>;
26
27 aliases {
28 pinctrl0 = &pinctrl_0;
29 pinctrl1 = &pinctrl_1;
30 mshc0 = &mshc_0;
31 mshc1 = &mshc_1;
32 spi0 = &spi_0;
33 spi1 = &spi_1;
34 i2c0 = &i2c_0;
35 i2c1 = &i2c_1;
36 i2c2 = &i2c_2;
37 i2c3 = &i2c_3;
38 i2c4 = &i2c_4;
39 i2c5 = &i2c_5;
40 i2c6 = &i2c_6;
41 i2c7 = &i2c_7;
1e64f48e
TF		 42 serial0 = &serial_0;
43 serial1 = &serial_1;
5a992a9c
TF		 44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu0: cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a7";
53 reg = <0>;
54 clock-frequency = <1000000000>;
55 };
56
57 cpu1: cpu@1 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a7";
60 reg = <1>;
61 clock-frequency = <1000000000>;
62 };
63 };
64
65 soc: soc {
66 compatible = "simple-bus";
67 #address-cells = <1>;
68 #size-cells = <1>;
69 ranges;
70
71 fixed-rate-clocks {
72 #address-cells = <1>;
73 #size-cells = <0>;
74
75 xusbxti: clock@0 {
76 compatible = "fixed-clock";
77 #address-cells = <1>;
78 #size-cells = <0>;
79 reg = <0>;
80 clock-frequency = <0>;
81 #clock-cells = <0>;
82 clock-output-names = "xusbxti";
83 };
84
85 xxti: clock@1 {
86 compatible = "fixed-clock";
87 reg = <1>;
88 clock-frequency = <0>;
89 #clock-cells = <0>;
90 clock-output-names = "xxti";
91 };
92
93 xtcxo: clock@2 {
94 compatible = "fixed-clock";
95 reg = <2>;
96 clock-frequency = <0>;
97 #clock-cells = <0>;
98 clock-output-names = "xtcxo";
99 };
100 };
101
102 sysram@02020000 {
103 compatible = "mmio-sram";
104 reg = <0x02020000 0x40000>;
105 #address-cells = <1>;
106 #size-cells = <1>;
107 ranges = <0 0x02020000 0x40000>;
108
109 smp-sysram@0 {
110 compatible = "samsung,exynos4210-sysram";
111 reg = <0x0 0x1000>;
112 };
113
114 smp-sysram@3f000 {
115 compatible = "samsung,exynos4210-sysram-ns";
116 reg = <0x3f000 0x1000>;
117 };
118 };
119
120 chipid@10000000 {
121 compatible = "samsung,exynos4210-chipid";
122 reg = <0x10000000 0x100>;
123 };
124
125 sys_reg: syscon@10010000 {
126 compatible = "samsung,exynos3-sysreg", "syscon";
127 reg = <0x10010000 0x400>;
128 };
129
25023926
CC		 130 pmu_system_controller: system-controller@10020000 {
131 compatible = "samsung,exynos3250-pmu", "syscon";
132 reg = <0x10020000 0x4000>;
133 };
134
9fab9d6a
ID		 135 mipi_phy: video-phy@10020710 {
136 compatible = "samsung,s5pv210-mipi-video-phy";
137 reg = <0x10020710 8>;
138 #phy-cells = <1>;
139 };
140
5a992a9c
TF		 141 pd_cam: cam-power-domain@10023C00 {
142 compatible = "samsung,exynos4210-pd";
143 reg = <0x10023C00 0x20>;
144 };
145
146 pd_mfc: mfc-power-domain@10023C40 {
147 compatible = "samsung,exynos4210-pd";
148 reg = <0x10023C40 0x20>;
149 };
150
151 pd_g3d: g3d-power-domain@10023C60 {
152 compatible = "samsung,exynos4210-pd";
153 reg = <0x10023C60 0x20>;
154 };
155
156 pd_lcd0: lcd0-power-domain@10023C80 {
157 compatible = "samsung,exynos4210-pd";
158 reg = <0x10023C80 0x20>;
159 };
160
161 pd_isp: isp-power-domain@10023CA0 {
162 compatible = "samsung,exynos4210-pd";
163 reg = <0x10023CA0 0x20>;
164 };
165
166 cmu: clock-controller@10030000 {
167 compatible = "samsung,exynos3250-cmu";
168 reg = <0x10030000 0x20000>;
169 #clock-cells = <1>;
170 };
171
d0e73eaf
KK		 172 cmu_dmc: clock-controller@105C0000 {
173 compatible = "samsung,exynos3250-cmu-dmc";
174 reg = <0x105C0000 0x2000>;
175 #clock-cells = <1>;
176 };
177
5a992a9c 178 rtc: rtc@10070000 {
78230477 179 compatible = "samsung,exynos3250-rtc";
5a992a9c
TF		 180 reg = <0x10070000 0x100>;
181 interrupts = <0 73 0>, <0 74 0>;
182 status = "disabled";
183 };
184
9dfb3347
CC		 185 tmu: tmu@100C0000 {
186 compatible = "samsung,exynos3250-tmu";
187 reg = <0x100C0000 0x100>;
188 interrupts = <0 216 0>;
189 clocks = <&cmu CLK_TMU_APBIF>;
190 clock-names = "tmu_apbif";
191 status = "disabled";
192 };
193
5a992a9c
TF		 194 gic: interrupt-controller@10481000 {
195 compatible = "arm,cortex-a15-gic";
196 #interrupt-cells = <3>;
197 interrupt-controller;
198 reg = <0x10481000 0x1000>,
199 <0x10482000 0x1000>,
200 <0x10484000 0x2000>,
201 <0x10486000 0x2000>;
202 interrupts = <1 9 0xf04>;
203 };
204
205 mct@10050000 {
206 compatible = "samsung,exynos4210-mct";
207 reg = <0x10050000 0x800>;
208 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
209 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
210 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
211 clock-names = "fin_pll", "mct";
212 };
213
214 pinctrl_1: pinctrl@11000000 {
215 compatible = "samsung,exynos3250-pinctrl";
216 reg = <0x11000000 0x1000>;
217 interrupts = <0 225 0>;
218
219 wakeup-interrupt-controller {
220 compatible = "samsung,exynos4210-wakeup-eint";
5a992a9c
TF		 221 interrupts = <0 48 0>;
222 };
223 };
224
225 pinctrl_0: pinctrl@11400000 {
226 compatible = "samsung,exynos3250-pinctrl";
227 reg = <0x11400000 0x1000>;
228 interrupts = <0 240 0>;
229 };
230
03b86c79
ID		 231 fimd: fimd@11c00000 {
232 compatible = "samsung,exynos3250-fimd";
233 reg = <0x11c00000 0x30000>;
234 interrupt-names = "fifo", "vsync", "lcd_sys";
235 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
236 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
237 clock-names = "sclk_fimd", "fimd";
238 samsung,power-domain = <&pd_lcd0>;
239 samsung,sysreg = <&sys_reg>;
240 status = "disabled";
241 };
242
025d8e13
ID		 243 dsi_0: dsi@11C80000 {
244 compatible = "samsung,exynos3250-mipi-dsi";
245 reg = <0x11C80000 0x10000>;
246 interrupts = <0 83 0>;
247 samsung,phy-type = <0>;
248 samsung,power-domain = <&pd_lcd0>;
249 phys = <&mipi_phy 1>;
250 phy-names = "dsim";
251 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
252 clock-names = "bus_clk", "pll_clk";
253 #address-cells = <1>;
254 #size-cells = <0>;
255 status = "disabled";
256 };
257
5a992a9c
TF		 258 mshc_0: mshc@12510000 {
259 compatible = "samsung,exynos5250-dw-mshc";
260 reg = <0x12510000 0x1000>;
261 interrupts = <0 142 0>;
262 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
263 clock-names = "biu", "ciu";
264 fifo-depth = <0x80>;
265 #address-cells = <1>;
266 #size-cells = <0>;
267 status = "disabled";
268 };
269
270 mshc_1: mshc@12520000 {
271 compatible = "samsung,exynos5250-dw-mshc";
272 reg = <0x12520000 0x1000>;
273 interrupts = <0 143 0>;
274 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
275 clock-names = "biu", "ciu";
276 fifo-depth = <0x80>;
277 #address-cells = <1>;
278 #size-cells = <0>;
279 status = "disabled";
280 };
281
11ab02b8
JK		 282 exynos_usbphy: exynos-usbphy@125B0000 {
283 compatible = "samsung,exynos3250-usb2-phy";
284 reg = <0x125B0000 0x100>;
285 samsung,pmureg-phandle = <&pmu_system_controller>;
286 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
287 clock-names = "phy", "ref";
288 #phy-cells = <1>;
289 status = "disabled";
290 };
291
5a992a9c
TF		 292 amba {
293 compatible = "arm,amba-bus";
294 #address-cells = <1>;
295 #size-cells = <1>;
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TF		 296 ranges;
297
298 pdma0: pdma@12680000 {
299 compatible = "arm,pl330", "arm,primecell";
300 reg = <0x12680000 0x1000>;
301 interrupts = <0 138 0>;
302 clocks = <&cmu CLK_PDMA0>;
303 clock-names = "apb_pclk";
304 #dma-cells = <1>;
305 #dma-channels = <8>;
306 #dma-requests = <32>;
307 };
308
309 pdma1: pdma@12690000 {
310 compatible = "arm,pl330", "arm,primecell";
311 reg = <0x12690000 0x1000>;
312 interrupts = <0 139 0>;
313 clocks = <&cmu CLK_PDMA1>;
314 clock-names = "apb_pclk";
315 #dma-cells = <1>;
316 #dma-channels = <8>;
317 #dma-requests = <32>;
318 };
319 };
320
321 adc: adc@126C0000 {
e6ca2d84
CC		 322 compatible = "samsung,exynos3250-adc",
323 "samsung,exynos-adc-v2";
db9bf4d6 324 reg = <0x126C0000 0x100>;
5a992a9c 325 interrupts = <0 137 0>;
e6ca2d84 326 clock-names = "adc", "sclk";
5a992a9c
TF		 327 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
328 #io-channel-cells = <1>;
329 io-channel-ranges;
db9bf4d6 330 samsung,syscon-phandle = <&pmu_system_controller>;
5a992a9c
TF		 331 status = "disabled";
332 };
333
752d3a23
JA		 334 mfc: codec@13400000 {
335 compatible = "samsung,mfc-v7";
336 reg = <0x13400000 0x10000>;
337 interrupts = <0 102 0>;
338 clock-names = "mfc", "sclk_mfc";
339 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
340 samsung,power-domain = <&pd_mfc>;
341 status = "disabled";
342 };
343
5a992a9c
TF		 344 serial_0: serial@13800000 {
345 compatible = "samsung,exynos4210-uart";
346 reg = <0x13800000 0x100>;
347 interrupts = <0 109 0>;
348 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
349 clock-names = "uart", "clk_uart_baud0";
a9408a6b
CC		 350 pinctrl-names = "default";
351 pinctrl-0 = <&uart0_data &uart0_fctl>;
5a992a9c
TF		 352 status = "disabled";
353 };
354
355 serial_1: serial@13810000 {
356 compatible = "samsung,exynos4210-uart";
357 reg = <0x13810000 0x100>;
358 interrupts = <0 110 0>;
359 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
360 clock-names = "uart", "clk_uart_baud0";
a9408a6b
CC		 361 pinctrl-names = "default";
362 pinctrl-0 = <&uart1_data>;
5a992a9c
TF		 363 status = "disabled";
364 };
365
366 i2c_0: i2c@13860000 {
367 #address-cells = <1>;
368 #size-cells = <0>;
369 compatible = "samsung,s3c2440-i2c";
370 reg = <0x13860000 0x100>;
371 interrupts = <0 113 0>;
372 clocks = <&cmu CLK_I2C0>;
373 clock-names = "i2c";
374 pinctrl-names = "default";
375 pinctrl-0 = <&i2c0_bus>;
376 status = "disabled";
377 };
378
379 i2c_1: i2c@13870000 {
380 #address-cells = <1>;
381 #size-cells = <0>;
382 compatible = "samsung,s3c2440-i2c";
383 reg = <0x13870000 0x100>;
384 interrupts = <0 114 0>;
385 clocks = <&cmu CLK_I2C1>;
386 clock-names = "i2c";
387 pinctrl-names = "default";
388 pinctrl-0 = <&i2c1_bus>;
389 status = "disabled";
390 };
391
392 i2c_2: i2c@13880000 {
393 #address-cells = <1>;
394 #size-cells = <0>;
395 compatible = "samsung,s3c2440-i2c";
396 reg = <0x13880000 0x100>;
397 interrupts = <0 115 0>;
398 clocks = <&cmu CLK_I2C2>;
399 clock-names = "i2c";
400 pinctrl-names = "default";
401 pinctrl-0 = <&i2c2_bus>;
402 status = "disabled";
403 };
404
405 i2c_3: i2c@13890000 {
406 #address-cells = <1>;
407 #size-cells = <0>;
408 compatible = "samsung,s3c2440-i2c";
409 reg = <0x13890000 0x100>;
410 interrupts = <0 116 0>;
411 clocks = <&cmu CLK_I2C3>;
412 clock-names = "i2c";
413 pinctrl-names = "default";
414 pinctrl-0 = <&i2c3_bus>;
415 status = "disabled";
416 };
417
418 i2c_4: i2c@138A0000 {
419 #address-cells = <1>;
420 #size-cells = <0>;
421 compatible = "samsung,s3c2440-i2c";
422 reg = <0x138A0000 0x100>;
423 interrupts = <0 117 0>;
424 clocks = <&cmu CLK_I2C4>;
425 clock-names = "i2c";
426 pinctrl-names = "default";
427 pinctrl-0 = <&i2c4_bus>;
428 status = "disabled";
429 };
430
431 i2c_5: i2c@138B0000 {
432 #address-cells = <1>;
433 #size-cells = <0>;
434 compatible = "samsung,s3c2440-i2c";
435 reg = <0x138B0000 0x100>;
436 interrupts = <0 118 0>;
437 clocks = <&cmu CLK_I2C5>;
438 clock-names = "i2c";
439 pinctrl-names = "default";
440 pinctrl-0 = <&i2c5_bus>;
441 status = "disabled";
442 };
443
444 i2c_6: i2c@138C0000 {
445 #address-cells = <1>;
446 #size-cells = <0>;
447 compatible = "samsung,s3c2440-i2c";
448 reg = <0x138C0000 0x100>;
449 interrupts = <0 119 0>;
450 clocks = <&cmu CLK_I2C6>;
451 clock-names = "i2c";
452 pinctrl-names = "default";
453 pinctrl-0 = <&i2c6_bus>;
454 status = "disabled";
455 };
456
457 i2c_7: i2c@138D0000 {
458 #address-cells = <1>;
459 #size-cells = <0>;
460 compatible = "samsung,s3c2440-i2c";
461 reg = <0x138D0000 0x100>;
462 interrupts = <0 120 0>;
463 clocks = <&cmu CLK_I2C7>;
464 clock-names = "i2c";
465 pinctrl-names = "default";
466 pinctrl-0 = <&i2c7_bus>;
467 status = "disabled";
468 };
469
470 spi_0: spi@13920000 {
471 compatible = "samsung,exynos4210-spi";
472 reg = <0x13920000 0x100>;
473 interrupts = <0 121 0>;
474 dmas = <&pdma0 7>, <&pdma0 6>;
475 dma-names = "tx", "rx";
476 #address-cells = <1>;
477 #size-cells = <0>;
478 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
479 clock-names = "spi", "spi_busclk0";
480 samsung,spi-src-clk = <0>;
481 pinctrl-names = "default";
482 pinctrl-0 = <&spi0_bus>;
483 status = "disabled";
484 };
485
486 spi_1: spi@13930000 {
487 compatible = "samsung,exynos4210-spi";
488 reg = <0x13930000 0x100>;
489 interrupts = <0 122 0>;
490 dmas = <&pdma1 7>, <&pdma1 6>;
491 dma-names = "tx", "rx";
492 #address-cells = <1>;
493 #size-cells = <0>;
494 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
495 clock-names = "spi", "spi_busclk0";
496 samsung,spi-src-clk = <0>;
497 pinctrl-names = "default";
498 pinctrl-0 = <&spi1_bus>;
499 status = "disabled";
500 };
501
ccaba452
TF		 502 i2s2: i2s@13970000 {
503 compatible = "samsung,s3c6410-i2s";
504 reg = <0x13970000 0x100>;
505 interrupts = <0 126 0>;
506 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
507 clock-names = "iis", "i2s_opclk0";
508 dmas = <&pdma0 14>, <&pdma0 13>;
509 dma-names = "tx", "rx";
510 pinctrl-0 = <&i2s2_bus>;
511 pinctrl-names = "default";
512 status = "disabled";
513 };
514
5a992a9c
TF		 515 pwm: pwm@139D0000 {
516 compatible = "samsung,exynos4210-pwm";
517 reg = <0x139D0000 0x1000>;
518 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
519 <0 107 0>, <0 108 0>;
520 #pwm-cells = <3>;
521 status = "disabled";
522 };
523
524 pmu {
525 compatible = "arm,cortex-a7-pmu";
526 interrupts = <0 18 0>, <0 19 0>;
527 };
528 };
529};
530
531#include "exynos3250-pinctrl.dtsi"
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