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b571abb3 TF |
1 | /* |
2 | * Samsung's Exynos4 SoC series common device tree source | |
3 | * | |
4 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * Copyright (c) 2010-2011 Linaro Ltd. | |
7 | * www.linaro.org | |
8 | * | |
9 | * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular | |
10 | * SoCs from Exynos4 series can include this file and provide values for SoCs | |
11 | * specfic bindings. | |
12 | * | |
13 | * Note: This file does not include device nodes for all the controllers in | |
14 | * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional | |
15 | * nodes can be added to this file. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License version 2 as | |
19 | * published by the Free Software Foundation. | |
20 | */ | |
21 | ||
1c75a78a | 22 | #include <dt-bindings/clock/exynos4.h> |
990a7bfd | 23 | #include <dt-bindings/clock/exynos-audss-clk.h> |
3799279f | 24 | #include "skeleton.dtsi" |
1462b137 | 25 | #include "exynos-syscon-restart.dtsi" |
b571abb3 TF |
26 | |
27 | / { | |
28 | interrupt-parent = <&gic>; | |
29 | ||
30 | aliases { | |
31 | spi0 = &spi_0; | |
32 | spi1 = &spi_1; | |
33 | spi2 = &spi_2; | |
34db4990 DA |
34 | i2c0 = &i2c_0; |
35 | i2c1 = &i2c_1; | |
36 | i2c2 = &i2c_2; | |
37 | i2c3 = &i2c_3; | |
38 | i2c4 = &i2c_4; | |
39 | i2c5 = &i2c_5; | |
40 | i2c6 = &i2c_6; | |
41 | i2c7 = &i2c_7; | |
ed80d4ca | 42 | i2c8 = &i2c_8; |
d1b8a41d SN |
43 | csis0 = &csis_0; |
44 | csis1 = &csis_1; | |
45 | fimc0 = &fimc_0; | |
46 | fimc1 = &fimc_1; | |
47 | fimc2 = &fimc_2; | |
48 | fimc3 = &fimc_3; | |
1e64f48e TF |
49 | serial0 = &serial_0; |
50 | serial1 = &serial_1; | |
51 | serial2 = &serial_2; | |
52 | serial3 = &serial_3; | |
b571abb3 TF |
53 | }; |
54 | ||
990a7bfd SN |
55 | clock_audss: clock-controller@03810000 { |
56 | compatible = "samsung,exynos4210-audss-clock"; | |
57 | reg = <0x03810000 0x0C>; | |
58 | #clock-cells = <1>; | |
59 | }; | |
60 | ||
61 | i2s0: i2s@03830000 { | |
62 | compatible = "samsung,s5pv210-i2s"; | |
63 | reg = <0x03830000 0x100>; | |
64 | clocks = <&clock_audss EXYNOS_I2S_BUS>; | |
65 | clock-names = "iis"; | |
3635acef SN |
66 | #clock-cells = <1>; |
67 | clock-output-names = "i2s_cdclk0"; | |
990a7bfd SN |
68 | dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; |
69 | dma-names = "tx", "rx", "tx-sec"; | |
70 | samsung,idma-addr = <0x03000000>; | |
16696337 | 71 | #sound-dai-cells = <1>; |
990a7bfd SN |
72 | status = "disabled"; |
73 | }; | |
74 | ||
096ee6ad TA |
75 | chipid@10000000 { |
76 | compatible = "samsung,exynos4210-chipid"; | |
77 | reg = <0x10000000 0x100>; | |
78 | }; | |
79 | ||
4d7820b0 PD |
80 | memory-controller@12570000 { |
81 | compatible = "samsung,exynos4210-srom"; | |
df4400ac PD |
82 | reg = <0x12570000 0x14>; |
83 | }; | |
84 | ||
72c4b2b6 | 85 | mipi_phy: video-phy { |
21b190d2 | 86 | compatible = "samsung,s5pv210-mipi-video-phy"; |
21b190d2 | 87 | #phy-cells = <1>; |
c8ef0bee | 88 | syscon = <&pmu_system_controller>; |
21b190d2 SN |
89 | }; |
90 | ||
91d88f03 TF |
91 | pd_mfc: mfc-power-domain@10023C40 { |
92 | compatible = "samsung,exynos4210-pd"; | |
93 | reg = <0x10023C40 0x20>; | |
0da65870 | 94 | #power-domain-cells = <0>; |
91d88f03 TF |
95 | }; |
96 | ||
97 | pd_g3d: g3d-power-domain@10023C60 { | |
98 | compatible = "samsung,exynos4210-pd"; | |
99 | reg = <0x10023C60 0x20>; | |
0da65870 | 100 | #power-domain-cells = <0>; |
91d88f03 TF |
101 | }; |
102 | ||
103 | pd_lcd0: lcd0-power-domain@10023C80 { | |
104 | compatible = "samsung,exynos4210-pd"; | |
105 | reg = <0x10023C80 0x20>; | |
0da65870 | 106 | #power-domain-cells = <0>; |
91d88f03 TF |
107 | }; |
108 | ||
109 | pd_tv: tv-power-domain@10023C20 { | |
110 | compatible = "samsung,exynos4210-pd"; | |
111 | reg = <0x10023C20 0x20>; | |
0da65870 | 112 | #power-domain-cells = <0>; |
ec459c0c | 113 | power-domains = <&pd_lcd0>; |
91d88f03 TF |
114 | }; |
115 | ||
116 | pd_cam: cam-power-domain@10023C00 { | |
117 | compatible = "samsung,exynos4210-pd"; | |
118 | reg = <0x10023C00 0x20>; | |
0da65870 | 119 | #power-domain-cells = <0>; |
91d88f03 TF |
120 | }; |
121 | ||
122 | pd_gps: gps-power-domain@10023CE0 { | |
123 | compatible = "samsung,exynos4210-pd"; | |
124 | reg = <0x10023CE0 0x20>; | |
0da65870 | 125 | #power-domain-cells = <0>; |
b571abb3 TF |
126 | }; |
127 | ||
10ea1f18 CC |
128 | pd_gps_alive: gps-alive-power-domain@10023D00 { |
129 | compatible = "samsung,exynos4210-pd"; | |
130 | reg = <0x10023D00 0x20>; | |
0da65870 | 131 | #power-domain-cells = <0>; |
10ea1f18 CC |
132 | }; |
133 | ||
0572b725 | 134 | gic: interrupt-controller@10490000 { |
b571abb3 TF |
135 | compatible = "arm,cortex-a9-gic"; |
136 | #interrupt-cells = <3>; | |
137 | interrupt-controller; | |
cf286b40 | 138 | reg = <0x10490000 0x10000>, <0x10480000 0x10000>; |
b571abb3 TF |
139 | }; |
140 | ||
0572b725 | 141 | combiner: interrupt-controller@10440000 { |
b571abb3 TF |
142 | compatible = "samsung,exynos4210-combiner"; |
143 | #interrupt-cells = <2>; | |
144 | interrupt-controller; | |
145 | reg = <0x10440000 0x1000>; | |
146 | }; | |
147 | ||
6f4b82a3 CP |
148 | pmu { |
149 | compatible = "arm,cortex-a9-pmu"; | |
150 | interrupt-parent = <&combiner>; | |
151 | interrupts = <2 2>, <3 2>; | |
152 | }; | |
153 | ||
9f052d0c | 154 | sys_reg: syscon@10010000 { |
a64b1b22 SN |
155 | compatible = "samsung,exynos4-sysreg", "syscon"; |
156 | reg = <0x10010000 0x400>; | |
157 | }; | |
158 | ||
7b9613ac CP |
159 | pmu_system_controller: system-controller@10020000 { |
160 | compatible = "samsung,exynos4210-pmu", "syscon"; | |
161 | reg = <0x10020000 0x4000>; | |
8b283c02 MZ |
162 | interrupt-controller; |
163 | #interrupt-cells = <3>; | |
164 | interrupt-parent = <&gic>; | |
7b9613ac CP |
165 | }; |
166 | ||
8b7dd64c AH |
167 | dsi_0: dsi@11C80000 { |
168 | compatible = "samsung,exynos4210-mipi-dsi"; | |
169 | reg = <0x11C80000 0x10000>; | |
170 | interrupts = <0 79 0>; | |
0da65870 | 171 | power-domains = <&pd_lcd0>; |
8b7dd64c AH |
172 | phys = <&mipi_phy 1>; |
173 | phy-names = "dsim"; | |
c8366bac | 174 | clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; |
4f01e650 | 175 | clock-names = "bus_clk", "sclk_mipi"; |
8b7dd64c AH |
176 | status = "disabled"; |
177 | #address-cells = <1>; | |
178 | #size-cells = <0>; | |
179 | }; | |
180 | ||
d1b8a41d SN |
181 | camera { |
182 | compatible = "samsung,fimc", "simple-bus"; | |
183 | status = "disabled"; | |
184 | #address-cells = <1>; | |
185 | #size-cells = <1>; | |
ee5eda64 SN |
186 | #clock-cells = <1>; |
187 | clock-output-names = "cam_a_clkout", "cam_b_clkout"; | |
d1b8a41d SN |
188 | ranges; |
189 | ||
d1b8a41d SN |
190 | fimc_0: fimc@11800000 { |
191 | compatible = "samsung,exynos4210-fimc"; | |
192 | reg = <0x11800000 0x1000>; | |
193 | interrupts = <0 84 0>; | |
1c75a78a | 194 | clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; |
d1b8a41d | 195 | clock-names = "fimc", "sclk_fimc"; |
0da65870 | 196 | power-domains = <&pd_cam>; |
d1b8a41d | 197 | samsung,sysreg = <&sys_reg>; |
71d3a9fb | 198 | iommus = <&sysmmu_fimc0>; |
d1b8a41d SN |
199 | status = "disabled"; |
200 | }; | |
201 | ||
202 | fimc_1: fimc@11810000 { | |
203 | compatible = "samsung,exynos4210-fimc"; | |
204 | reg = <0x11810000 0x1000>; | |
205 | interrupts = <0 85 0>; | |
1c75a78a | 206 | clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>; |
d1b8a41d | 207 | clock-names = "fimc", "sclk_fimc"; |
0da65870 | 208 | power-domains = <&pd_cam>; |
d1b8a41d | 209 | samsung,sysreg = <&sys_reg>; |
71d3a9fb | 210 | iommus = <&sysmmu_fimc1>; |
d1b8a41d SN |
211 | status = "disabled"; |
212 | }; | |
213 | ||
214 | fimc_2: fimc@11820000 { | |
215 | compatible = "samsung,exynos4210-fimc"; | |
216 | reg = <0x11820000 0x1000>; | |
217 | interrupts = <0 86 0>; | |
1c75a78a | 218 | clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>; |
d1b8a41d | 219 | clock-names = "fimc", "sclk_fimc"; |
0da65870 | 220 | power-domains = <&pd_cam>; |
d1b8a41d | 221 | samsung,sysreg = <&sys_reg>; |
71d3a9fb | 222 | iommus = <&sysmmu_fimc2>; |
d1b8a41d SN |
223 | status = "disabled"; |
224 | }; | |
225 | ||
226 | fimc_3: fimc@11830000 { | |
227 | compatible = "samsung,exynos4210-fimc"; | |
228 | reg = <0x11830000 0x1000>; | |
229 | interrupts = <0 87 0>; | |
1c75a78a | 230 | clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>; |
d1b8a41d | 231 | clock-names = "fimc", "sclk_fimc"; |
0da65870 | 232 | power-domains = <&pd_cam>; |
d1b8a41d | 233 | samsung,sysreg = <&sys_reg>; |
71d3a9fb | 234 | iommus = <&sysmmu_fimc3>; |
d1b8a41d SN |
235 | status = "disabled"; |
236 | }; | |
237 | ||
238 | csis_0: csis@11880000 { | |
239 | compatible = "samsung,exynos4210-csis"; | |
240 | reg = <0x11880000 0x4000>; | |
241 | interrupts = <0 78 0>; | |
1c75a78a | 242 | clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; |
d1b8a41d SN |
243 | clock-names = "csis", "sclk_csis"; |
244 | bus-width = <4>; | |
0da65870 | 245 | power-domains = <&pd_cam>; |
21b190d2 SN |
246 | phys = <&mipi_phy 0>; |
247 | phy-names = "csis"; | |
d1b8a41d SN |
248 | status = "disabled"; |
249 | #address-cells = <1>; | |
250 | #size-cells = <0>; | |
251 | }; | |
252 | ||
253 | csis_1: csis@11890000 { | |
254 | compatible = "samsung,exynos4210-csis"; | |
255 | reg = <0x11890000 0x4000>; | |
256 | interrupts = <0 80 0>; | |
1c75a78a | 257 | clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>; |
d1b8a41d SN |
258 | clock-names = "csis", "sclk_csis"; |
259 | bus-width = <2>; | |
0da65870 | 260 | power-domains = <&pd_cam>; |
21b190d2 SN |
261 | phys = <&mipi_phy 2>; |
262 | phy-names = "csis"; | |
d1b8a41d SN |
263 | status = "disabled"; |
264 | #address-cells = <1>; | |
265 | #size-cells = <0>; | |
266 | }; | |
267 | }; | |
268 | ||
9c41221e | 269 | watchdog: watchdog@10060000 { |
b571abb3 TF |
270 | compatible = "samsung,s3c2410-wdt"; |
271 | reg = <0x10060000 0x100>; | |
272 | interrupts = <0 43 0>; | |
1c75a78a | 273 | clocks = <&clock CLK_WDT>; |
7ad34337 | 274 | clock-names = "watchdog"; |
c9e23f00 | 275 | status = "disabled"; |
b571abb3 TF |
276 | }; |
277 | ||
ce9940a9 | 278 | rtc: rtc@10070000 { |
b571abb3 TF |
279 | compatible = "samsung,s3c6410-rtc"; |
280 | reg = <0x10070000 0x100>; | |
8b283c02 | 281 | interrupt-parent = <&pmu_system_controller>; |
b571abb3 | 282 | interrupts = <0 44 0>, <0 45 0>; |
1c75a78a | 283 | clocks = <&clock CLK_RTC>; |
7ad34337 | 284 | clock-names = "rtc"; |
c9e23f00 | 285 | status = "disabled"; |
b571abb3 TF |
286 | }; |
287 | ||
9c41221e | 288 | keypad: keypad@100A0000 { |
b571abb3 TF |
289 | compatible = "samsung,s5pv210-keypad"; |
290 | reg = <0x100A0000 0x100>; | |
291 | interrupts = <0 109 0>; | |
1c75a78a | 292 | clocks = <&clock CLK_KEYIF>; |
7ad34337 | 293 | clock-names = "keypad"; |
c9e23f00 | 294 | status = "disabled"; |
b571abb3 TF |
295 | }; |
296 | ||
9c41221e | 297 | sdhci_0: sdhci@12510000 { |
b571abb3 TF |
298 | compatible = "samsung,exynos4210-sdhci"; |
299 | reg = <0x12510000 0x100>; | |
300 | interrupts = <0 73 0>; | |
1c75a78a | 301 | clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; |
7ad34337 | 302 | clock-names = "hsmmc", "mmc_busclk.2"; |
c9e23f00 | 303 | status = "disabled"; |
b571abb3 TF |
304 | }; |
305 | ||
9c41221e | 306 | sdhci_1: sdhci@12520000 { |
b571abb3 TF |
307 | compatible = "samsung,exynos4210-sdhci"; |
308 | reg = <0x12520000 0x100>; | |
309 | interrupts = <0 74 0>; | |
1c75a78a | 310 | clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; |
7ad34337 | 311 | clock-names = "hsmmc", "mmc_busclk.2"; |
c9e23f00 | 312 | status = "disabled"; |
b571abb3 TF |
313 | }; |
314 | ||
9c41221e | 315 | sdhci_2: sdhci@12530000 { |
b571abb3 TF |
316 | compatible = "samsung,exynos4210-sdhci"; |
317 | reg = <0x12530000 0x100>; | |
318 | interrupts = <0 75 0>; | |
1c75a78a | 319 | clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; |
7ad34337 | 320 | clock-names = "hsmmc", "mmc_busclk.2"; |
c9e23f00 | 321 | status = "disabled"; |
b571abb3 TF |
322 | }; |
323 | ||
9c41221e | 324 | sdhci_3: sdhci@12540000 { |
b571abb3 TF |
325 | compatible = "samsung,exynos4210-sdhci"; |
326 | reg = <0x12540000 0x100>; | |
327 | interrupts = <0 76 0>; | |
1c75a78a | 328 | clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; |
7ad34337 | 329 | clock-names = "hsmmc", "mmc_busclk.2"; |
c9e23f00 | 330 | status = "disabled"; |
26bbd41f CP |
331 | }; |
332 | ||
333 | exynos_usbphy: exynos-usbphy@125B0000 { | |
334 | compatible = "samsung,exynos4210-usb2-phy"; | |
335 | reg = <0x125B0000 0x100>; | |
336 | samsung,pmureg-phandle = <&pmu_system_controller>; | |
337 | clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; | |
338 | clock-names = "phy", "ref"; | |
339 | #phy-cells = <1>; | |
340 | status = "disabled"; | |
ef14d94c CP |
341 | }; |
342 | ||
9c41221e | 343 | hsotg: hsotg@12480000 { |
ef14d94c CP |
344 | compatible = "samsung,s3c6400-hsotg"; |
345 | reg = <0x12480000 0x20000>; | |
346 | interrupts = <0 71 0>; | |
347 | clocks = <&clock CLK_USB_DEVICE>; | |
348 | clock-names = "otg"; | |
349 | phys = <&exynos_usbphy 0>; | |
350 | phy-names = "usb2-phy"; | |
351 | status = "disabled"; | |
b571abb3 TF |
352 | }; |
353 | ||
9c41221e | 354 | ehci: ehci@12580000 { |
6f9d02a0 DK |
355 | compatible = "samsung,exynos4210-ehci"; |
356 | reg = <0x12580000 0x100>; | |
357 | interrupts = <0 70 0>; | |
1c75a78a | 358 | clocks = <&clock CLK_USB_HOST>; |
6f9d02a0 DK |
359 | clock-names = "usbhost"; |
360 | status = "disabled"; | |
366126d5 MS |
361 | #address-cells = <1>; |
362 | #size-cells = <0>; | |
363 | port@0 { | |
364 | reg = <0>; | |
365 | phys = <&exynos_usbphy 1>; | |
366 | status = "disabled"; | |
367 | }; | |
368 | port@1 { | |
369 | reg = <1>; | |
370 | phys = <&exynos_usbphy 2>; | |
371 | status = "disabled"; | |
372 | }; | |
373 | port@2 { | |
374 | reg = <2>; | |
375 | phys = <&exynos_usbphy 3>; | |
376 | status = "disabled"; | |
377 | }; | |
6f9d02a0 DK |
378 | }; |
379 | ||
9c41221e | 380 | ohci: ohci@12590000 { |
6f9d02a0 DK |
381 | compatible = "samsung,exynos4210-ohci"; |
382 | reg = <0x12590000 0x100>; | |
383 | interrupts = <0 70 0>; | |
1c75a78a | 384 | clocks = <&clock CLK_USB_HOST>; |
6f9d02a0 DK |
385 | clock-names = "usbhost"; |
386 | status = "disabled"; | |
366126d5 MS |
387 | #address-cells = <1>; |
388 | #size-cells = <0>; | |
389 | port@0 { | |
390 | reg = <0>; | |
391 | phys = <&exynos_usbphy 1>; | |
392 | status = "disabled"; | |
393 | }; | |
6f9d02a0 DK |
394 | }; |
395 | ||
990a7bfd | 396 | i2s1: i2s@13960000 { |
fddcd300 | 397 | compatible = "samsung,s3c6410-i2s"; |
990a7bfd SN |
398 | reg = <0x13960000 0x100>; |
399 | clocks = <&clock CLK_I2S1>; | |
400 | clock-names = "iis"; | |
3635acef SN |
401 | #clock-cells = <1>; |
402 | clock-output-names = "i2s_cdclk1"; | |
990a7bfd SN |
403 | dmas = <&pdma1 12>, <&pdma1 11>; |
404 | dma-names = "tx", "rx"; | |
16696337 | 405 | #sound-dai-cells = <1>; |
990a7bfd SN |
406 | status = "disabled"; |
407 | }; | |
408 | ||
409 | i2s2: i2s@13970000 { | |
fddcd300 | 410 | compatible = "samsung,s3c6410-i2s"; |
990a7bfd SN |
411 | reg = <0x13970000 0x100>; |
412 | clocks = <&clock CLK_I2S2>; | |
413 | clock-names = "iis"; | |
3635acef SN |
414 | #clock-cells = <1>; |
415 | clock-output-names = "i2s_cdclk2"; | |
990a7bfd SN |
416 | dmas = <&pdma0 14>, <&pdma0 13>; |
417 | dma-names = "tx", "rx"; | |
16696337 | 418 | #sound-dai-cells = <1>; |
990a7bfd SN |
419 | status = "disabled"; |
420 | }; | |
421 | ||
20901f74 SK |
422 | mfc: codec@13400000 { |
423 | compatible = "samsung,mfc-v5"; | |
424 | reg = <0x13400000 0x10000>; | |
425 | interrupts = <0 94 0>; | |
0da65870 | 426 | power-domains = <&pd_mfc>; |
e7160bfc MS |
427 | clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; |
428 | clock-names = "mfc", "sclk_mfc"; | |
71d3a9fb MS |
429 | iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; |
430 | iommu-names = "left", "right"; | |
20901f74 SK |
431 | }; |
432 | ||
1e64f48e | 433 | serial_0: serial@13800000 { |
b571abb3 TF |
434 | compatible = "samsung,exynos4210-uart"; |
435 | reg = <0x13800000 0x100>; | |
436 | interrupts = <0 52 0>; | |
1c75a78a | 437 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; |
7ad34337 | 438 | clock-names = "uart", "clk_uart_baud0"; |
22374fbe RB |
439 | dmas = <&pdma0 15>, <&pdma0 16>; |
440 | dma-names = "rx", "tx"; | |
c9e23f00 | 441 | status = "disabled"; |
b571abb3 TF |
442 | }; |
443 | ||
1e64f48e | 444 | serial_1: serial@13810000 { |
b571abb3 TF |
445 | compatible = "samsung,exynos4210-uart"; |
446 | reg = <0x13810000 0x100>; | |
447 | interrupts = <0 53 0>; | |
1c75a78a | 448 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; |
7ad34337 | 449 | clock-names = "uart", "clk_uart_baud0"; |
22374fbe RB |
450 | dmas = <&pdma1 15>, <&pdma1 16>; |
451 | dma-names = "rx", "tx"; | |
c9e23f00 | 452 | status = "disabled"; |
b571abb3 TF |
453 | }; |
454 | ||
1e64f48e | 455 | serial_2: serial@13820000 { |
b571abb3 TF |
456 | compatible = "samsung,exynos4210-uart"; |
457 | reg = <0x13820000 0x100>; | |
458 | interrupts = <0 54 0>; | |
1c75a78a | 459 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
7ad34337 | 460 | clock-names = "uart", "clk_uart_baud0"; |
22374fbe RB |
461 | dmas = <&pdma0 17>, <&pdma0 18>; |
462 | dma-names = "rx", "tx"; | |
c9e23f00 | 463 | status = "disabled"; |
b571abb3 TF |
464 | }; |
465 | ||
1e64f48e | 466 | serial_3: serial@13830000 { |
b571abb3 TF |
467 | compatible = "samsung,exynos4210-uart"; |
468 | reg = <0x13830000 0x100>; | |
469 | interrupts = <0 55 0>; | |
1c75a78a | 470 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; |
7ad34337 | 471 | clock-names = "uart", "clk_uart_baud0"; |
22374fbe RB |
472 | dmas = <&pdma1 17>, <&pdma1 18>; |
473 | dma-names = "rx", "tx"; | |
c9e23f00 | 474 | status = "disabled"; |
b571abb3 TF |
475 | }; |
476 | ||
34db4990 | 477 | i2c_0: i2c@13860000 { |
1b198d56 TF |
478 | #address-cells = <1>; |
479 | #size-cells = <0>; | |
b571abb3 TF |
480 | compatible = "samsung,s3c2440-i2c"; |
481 | reg = <0x13860000 0x100>; | |
482 | interrupts = <0 58 0>; | |
1c75a78a | 483 | clocks = <&clock CLK_I2C0>; |
7ad34337 | 484 | clock-names = "i2c"; |
045c8f63 TA |
485 | pinctrl-names = "default"; |
486 | pinctrl-0 = <&i2c0_bus>; | |
c9e23f00 | 487 | status = "disabled"; |
b571abb3 TF |
488 | }; |
489 | ||
34db4990 | 490 | i2c_1: i2c@13870000 { |
1b198d56 TF |
491 | #address-cells = <1>; |
492 | #size-cells = <0>; | |
b571abb3 TF |
493 | compatible = "samsung,s3c2440-i2c"; |
494 | reg = <0x13870000 0x100>; | |
495 | interrupts = <0 59 0>; | |
1c75a78a | 496 | clocks = <&clock CLK_I2C1>; |
7ad34337 | 497 | clock-names = "i2c"; |
045c8f63 TA |
498 | pinctrl-names = "default"; |
499 | pinctrl-0 = <&i2c1_bus>; | |
c9e23f00 | 500 | status = "disabled"; |
b571abb3 TF |
501 | }; |
502 | ||
34db4990 | 503 | i2c_2: i2c@13880000 { |
1b198d56 TF |
504 | #address-cells = <1>; |
505 | #size-cells = <0>; | |
b571abb3 TF |
506 | compatible = "samsung,s3c2440-i2c"; |
507 | reg = <0x13880000 0x100>; | |
508 | interrupts = <0 60 0>; | |
1c75a78a | 509 | clocks = <&clock CLK_I2C2>; |
7ad34337 | 510 | clock-names = "i2c"; |
9c869d1f TS |
511 | pinctrl-names = "default"; |
512 | pinctrl-0 = <&i2c2_bus>; | |
c9e23f00 | 513 | status = "disabled"; |
b571abb3 TF |
514 | }; |
515 | ||
34db4990 | 516 | i2c_3: i2c@13890000 { |
1b198d56 TF |
517 | #address-cells = <1>; |
518 | #size-cells = <0>; | |
b571abb3 TF |
519 | compatible = "samsung,s3c2440-i2c"; |
520 | reg = <0x13890000 0x100>; | |
521 | interrupts = <0 61 0>; | |
1c75a78a | 522 | clocks = <&clock CLK_I2C3>; |
7ad34337 | 523 | clock-names = "i2c"; |
9c869d1f TS |
524 | pinctrl-names = "default"; |
525 | pinctrl-0 = <&i2c3_bus>; | |
c9e23f00 | 526 | status = "disabled"; |
b571abb3 TF |
527 | }; |
528 | ||
34db4990 | 529 | i2c_4: i2c@138A0000 { |
1b198d56 TF |
530 | #address-cells = <1>; |
531 | #size-cells = <0>; | |
b571abb3 TF |
532 | compatible = "samsung,s3c2440-i2c"; |
533 | reg = <0x138A0000 0x100>; | |
534 | interrupts = <0 62 0>; | |
1c75a78a | 535 | clocks = <&clock CLK_I2C4>; |
7ad34337 | 536 | clock-names = "i2c"; |
9c869d1f TS |
537 | pinctrl-names = "default"; |
538 | pinctrl-0 = <&i2c4_bus>; | |
c9e23f00 | 539 | status = "disabled"; |
b571abb3 TF |
540 | }; |
541 | ||
34db4990 | 542 | i2c_5: i2c@138B0000 { |
1b198d56 TF |
543 | #address-cells = <1>; |
544 | #size-cells = <0>; | |
b571abb3 TF |
545 | compatible = "samsung,s3c2440-i2c"; |
546 | reg = <0x138B0000 0x100>; | |
547 | interrupts = <0 63 0>; | |
1c75a78a | 548 | clocks = <&clock CLK_I2C5>; |
7ad34337 | 549 | clock-names = "i2c"; |
9c869d1f TS |
550 | pinctrl-names = "default"; |
551 | pinctrl-0 = <&i2c5_bus>; | |
c9e23f00 | 552 | status = "disabled"; |
b571abb3 TF |
553 | }; |
554 | ||
34db4990 | 555 | i2c_6: i2c@138C0000 { |
1b198d56 TF |
556 | #address-cells = <1>; |
557 | #size-cells = <0>; | |
b571abb3 TF |
558 | compatible = "samsung,s3c2440-i2c"; |
559 | reg = <0x138C0000 0x100>; | |
560 | interrupts = <0 64 0>; | |
1c75a78a | 561 | clocks = <&clock CLK_I2C6>; |
7ad34337 | 562 | clock-names = "i2c"; |
9c869d1f TS |
563 | pinctrl-names = "default"; |
564 | pinctrl-0 = <&i2c6_bus>; | |
c9e23f00 | 565 | status = "disabled"; |
b571abb3 TF |
566 | }; |
567 | ||
34db4990 | 568 | i2c_7: i2c@138D0000 { |
1b198d56 TF |
569 | #address-cells = <1>; |
570 | #size-cells = <0>; | |
b571abb3 TF |
571 | compatible = "samsung,s3c2440-i2c"; |
572 | reg = <0x138D0000 0x100>; | |
573 | interrupts = <0 65 0>; | |
1c75a78a | 574 | clocks = <&clock CLK_I2C7>; |
7ad34337 | 575 | clock-names = "i2c"; |
9c869d1f TS |
576 | pinctrl-names = "default"; |
577 | pinctrl-0 = <&i2c7_bus>; | |
c9e23f00 | 578 | status = "disabled"; |
b571abb3 TF |
579 | }; |
580 | ||
ed80d4ca MS |
581 | i2c_8: i2c@138E0000 { |
582 | #address-cells = <1>; | |
583 | #size-cells = <0>; | |
584 | compatible = "samsung,s3c2440-hdmiphy-i2c"; | |
585 | reg = <0x138E0000 0x100>; | |
586 | interrupts = <0 93 0>; | |
587 | clocks = <&clock CLK_I2C_HDMI>; | |
588 | clock-names = "i2c"; | |
589 | status = "disabled"; | |
590 | ||
591 | hdmi_i2c_phy: hdmiphy@38 { | |
592 | compatible = "exynos4210-hdmiphy"; | |
593 | reg = <0x38>; | |
594 | }; | |
595 | }; | |
596 | ||
b571abb3 TF |
597 | spi_0: spi@13920000 { |
598 | compatible = "samsung,exynos4210-spi"; | |
599 | reg = <0x13920000 0x100>; | |
600 | interrupts = <0 66 0>; | |
48b3af1e SN |
601 | dmas = <&pdma0 7>, <&pdma0 6>; |
602 | dma-names = "tx", "rx"; | |
b571abb3 TF |
603 | #address-cells = <1>; |
604 | #size-cells = <0>; | |
1c75a78a | 605 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; |
7ad34337 | 606 | clock-names = "spi", "spi_busclk0"; |
045c8f63 TA |
607 | pinctrl-names = "default"; |
608 | pinctrl-0 = <&spi0_bus>; | |
c9e23f00 | 609 | status = "disabled"; |
b571abb3 TF |
610 | }; |
611 | ||
612 | spi_1: spi@13930000 { | |
613 | compatible = "samsung,exynos4210-spi"; | |
614 | reg = <0x13930000 0x100>; | |
615 | interrupts = <0 67 0>; | |
48b3af1e SN |
616 | dmas = <&pdma1 7>, <&pdma1 6>; |
617 | dma-names = "tx", "rx"; | |
b571abb3 TF |
618 | #address-cells = <1>; |
619 | #size-cells = <0>; | |
1c75a78a | 620 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; |
7ad34337 | 621 | clock-names = "spi", "spi_busclk0"; |
045c8f63 TA |
622 | pinctrl-names = "default"; |
623 | pinctrl-0 = <&spi1_bus>; | |
c9e23f00 | 624 | status = "disabled"; |
b571abb3 TF |
625 | }; |
626 | ||
627 | spi_2: spi@13940000 { | |
628 | compatible = "samsung,exynos4210-spi"; | |
629 | reg = <0x13940000 0x100>; | |
630 | interrupts = <0 68 0>; | |
48b3af1e SN |
631 | dmas = <&pdma0 9>, <&pdma0 8>; |
632 | dma-names = "tx", "rx"; | |
b571abb3 TF |
633 | #address-cells = <1>; |
634 | #size-cells = <0>; | |
1c75a78a | 635 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; |
7ad34337 | 636 | clock-names = "spi", "spi_busclk0"; |
045c8f63 TA |
637 | pinctrl-names = "default"; |
638 | pinctrl-0 = <&spi2_bus>; | |
c9e23f00 | 639 | status = "disabled"; |
b571abb3 TF |
640 | }; |
641 | ||
9c41221e | 642 | pwm: pwm@139D0000 { |
cc4193ea TF |
643 | compatible = "samsung,exynos4210-pwm"; |
644 | reg = <0x139D0000 0x1000>; | |
645 | interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; | |
1c75a78a | 646 | clocks = <&clock CLK_PWM>; |
ec06dbe7 | 647 | clock-names = "timers"; |
2fd82d33 | 648 | #pwm-cells = <3>; |
cc4193ea TF |
649 | status = "disabled"; |
650 | }; | |
651 | ||
b571abb3 TF |
652 | amba { |
653 | #address-cells = <1>; | |
654 | #size-cells = <1>; | |
2ef7d5f3 | 655 | compatible = "simple-bus"; |
b571abb3 TF |
656 | interrupt-parent = <&gic>; |
657 | ranges; | |
658 | ||
659 | pdma0: pdma@12680000 { | |
660 | compatible = "arm,pl330", "arm,primecell"; | |
661 | reg = <0x12680000 0x1000>; | |
662 | interrupts = <0 35 0>; | |
1c75a78a | 663 | clocks = <&clock CLK_PDMA0>; |
7ad34337 | 664 | clock-names = "apb_pclk"; |
0a96d4d3 PV |
665 | #dma-cells = <1>; |
666 | #dma-channels = <8>; | |
667 | #dma-requests = <32>; | |
b571abb3 TF |
668 | }; |
669 | ||
670 | pdma1: pdma@12690000 { | |
671 | compatible = "arm,pl330", "arm,primecell"; | |
672 | reg = <0x12690000 0x1000>; | |
673 | interrupts = <0 36 0>; | |
1c75a78a | 674 | clocks = <&clock CLK_PDMA1>; |
7ad34337 | 675 | clock-names = "apb_pclk"; |
0a96d4d3 PV |
676 | #dma-cells = <1>; |
677 | #dma-channels = <8>; | |
678 | #dma-requests = <32>; | |
b571abb3 | 679 | }; |
f7e758af BZ |
680 | |
681 | mdma1: mdma@12850000 { | |
682 | compatible = "arm,pl330", "arm,primecell"; | |
683 | reg = <0x12850000 0x1000>; | |
684 | interrupts = <0 34 0>; | |
1c75a78a | 685 | clocks = <&clock CLK_MDMA>; |
7ad34337 | 686 | clock-names = "apb_pclk"; |
0a96d4d3 PV |
687 | #dma-cells = <1>; |
688 | #dma-channels = <8>; | |
689 | #dma-requests = <1>; | |
f7e758af | 690 | }; |
b571abb3 | 691 | }; |
768c3a56 VS |
692 | |
693 | fimd: fimd@11c00000 { | |
694 | compatible = "samsung,exynos4210-fimd"; | |
695 | interrupt-parent = <&combiner>; | |
696 | reg = <0x11c00000 0x20000>; | |
697 | interrupt-names = "fifo", "vsync", "lcd_sys"; | |
698 | interrupts = <11 0>, <11 1>, <11 2>; | |
1c75a78a | 699 | clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; |
768c3a56 | 700 | clock-names = "sclk_fimd", "fimd"; |
0da65870 | 701 | power-domains = <&pd_lcd0>; |
71d3a9fb | 702 | iommus = <&sysmmu_fimd0>; |
2eb62941 | 703 | samsung,sysreg = <&sys_reg>; |
768c3a56 VS |
704 | status = "disabled"; |
705 | }; | |
30e0e476 | 706 | |
9843a223 LM |
707 | tmu: tmu@100C0000 { |
708 | #include "exynos4412-tmu-sensor-conf.dtsi" | |
709 | }; | |
710 | ||
9c41221e | 711 | jpeg_codec: jpeg-codec@11840000 { |
f470b859 MS |
712 | compatible = "samsung,exynos4210-jpeg"; |
713 | reg = <0x11840000 0x1000>; | |
714 | interrupts = <0 88 0>; | |
715 | clocks = <&clock CLK_JPEG>; | |
716 | clock-names = "jpeg"; | |
717 | power-domains = <&pd_cam>; | |
ba032795 | 718 | iommus = <&sysmmu_jpeg>; |
f470b859 MS |
719 | }; |
720 | ||
0c7e90b5 MS |
721 | rotator: rotator@12810000 { |
722 | compatible = "samsung,exynos4210-rotator"; | |
723 | reg = <0x12810000 0x64>; | |
724 | interrupts = <0 83 0>; | |
725 | clocks = <&clock CLK_ROTATOR>; | |
726 | clock-names = "rotator"; | |
727 | iommus = <&sysmmu_rotator>; | |
728 | }; | |
729 | ||
ed80d4ca MS |
730 | hdmi: hdmi@12D00000 { |
731 | compatible = "samsung,exynos4210-hdmi"; | |
732 | reg = <0x12D00000 0x70000>; | |
733 | interrupts = <0 92 0>; | |
734 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", | |
735 | "mout_hdmi"; | |
736 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, | |
737 | <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, | |
738 | <&clock CLK_MOUT_HDMI>; | |
739 | phy = <&hdmi_i2c_phy>; | |
740 | power-domains = <&pd_tv>; | |
741 | samsung,syscon-phandle = <&pmu_system_controller>; | |
742 | status = "disabled"; | |
c795c88d KD |
743 | }; |
744 | ||
745 | hdmicec: cec@100B0000 { | |
746 | compatible = "samsung,s5p-cec"; | |
747 | reg = <0x100B0000 0x200>; | |
748 | interrupts = <0 114 0>; | |
749 | clocks = <&clock CLK_HDMI_CEC>; | |
750 | clock-names = "hdmicec"; | |
751 | samsung,syscon-phandle = <&pmu_system_controller>; | |
752 | pinctrl-names = "default"; | |
753 | pinctrl-0 = <&hdmi_cec>; | |
754 | status = "disabled"; | |
ed80d4ca MS |
755 | }; |
756 | ||
757 | mixer: mixer@12C10000 { | |
758 | compatible = "samsung,exynos4210-mixer"; | |
759 | interrupts = <0 91 0>; | |
760 | reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; | |
761 | power-domains = <&pd_tv>; | |
71d3a9fb | 762 | iommus = <&sysmmu_tv>; |
ed80d4ca MS |
763 | status = "disabled"; |
764 | }; | |
765 | ||
30e0e476 CC |
766 | ppmu_dmc0: ppmu_dmc0@106a0000 { |
767 | compatible = "samsung,exynos-ppmu"; | |
768 | reg = <0x106a0000 0x2000>; | |
769 | clocks = <&clock CLK_PPMUDMC0>; | |
770 | clock-names = "ppmu"; | |
771 | status = "disabled"; | |
772 | }; | |
773 | ||
774 | ppmu_dmc1: ppmu_dmc1@106b0000 { | |
775 | compatible = "samsung,exynos-ppmu"; | |
776 | reg = <0x106b0000 0x2000>; | |
777 | clocks = <&clock CLK_PPMUDMC1>; | |
778 | clock-names = "ppmu"; | |
779 | status = "disabled"; | |
780 | }; | |
781 | ||
782 | ppmu_cpu: ppmu_cpu@106c0000 { | |
783 | compatible = "samsung,exynos-ppmu"; | |
784 | reg = <0x106c0000 0x2000>; | |
785 | clocks = <&clock CLK_PPMUCPU>; | |
786 | clock-names = "ppmu"; | |
787 | status = "disabled"; | |
788 | }; | |
789 | ||
790 | ppmu_acp: ppmu_acp@10ae0000 { | |
791 | compatible = "samsung,exynos-ppmu"; | |
792 | reg = <0x106e0000 0x2000>; | |
793 | status = "disabled"; | |
794 | }; | |
795 | ||
796 | ppmu_rightbus: ppmu_rightbus@112a0000 { | |
797 | compatible = "samsung,exynos-ppmu"; | |
798 | reg = <0x112a0000 0x2000>; | |
799 | clocks = <&clock CLK_PPMURIGHT>; | |
800 | clock-names = "ppmu"; | |
801 | status = "disabled"; | |
802 | }; | |
803 | ||
804 | ppmu_leftbus: ppmu_leftbus0@116a0000 { | |
805 | compatible = "samsung,exynos-ppmu"; | |
806 | reg = <0x116a0000 0x2000>; | |
807 | clocks = <&clock CLK_PPMULEFT>; | |
808 | clock-names = "ppmu"; | |
809 | status = "disabled"; | |
810 | }; | |
811 | ||
812 | ppmu_camif: ppmu_camif@11ac0000 { | |
813 | compatible = "samsung,exynos-ppmu"; | |
814 | reg = <0x11ac0000 0x2000>; | |
815 | clocks = <&clock CLK_PPMUCAMIF>; | |
816 | clock-names = "ppmu"; | |
817 | status = "disabled"; | |
818 | }; | |
819 | ||
820 | ppmu_lcd0: ppmu_lcd0@11e40000 { | |
821 | compatible = "samsung,exynos-ppmu"; | |
822 | reg = <0x11e40000 0x2000>; | |
823 | clocks = <&clock CLK_PPMULCD0>; | |
824 | clock-names = "ppmu"; | |
825 | status = "disabled"; | |
826 | }; | |
827 | ||
828 | ppmu_fsys: ppmu_g3d@12630000 { | |
829 | compatible = "samsung,exynos-ppmu"; | |
830 | reg = <0x12630000 0x2000>; | |
831 | status = "disabled"; | |
832 | }; | |
833 | ||
834 | ppmu_image: ppmu_image@12aa0000 { | |
835 | compatible = "samsung,exynos-ppmu"; | |
836 | reg = <0x12aa0000 0x2000>; | |
837 | clocks = <&clock CLK_PPMUIMAGE>; | |
838 | clock-names = "ppmu"; | |
839 | status = "disabled"; | |
840 | }; | |
841 | ||
842 | ppmu_tv: ppmu_tv@12e40000 { | |
843 | compatible = "samsung,exynos-ppmu"; | |
844 | reg = <0x12e40000 0x2000>; | |
845 | clocks = <&clock CLK_PPMUTV>; | |
846 | clock-names = "ppmu"; | |
847 | status = "disabled"; | |
848 | }; | |
849 | ||
850 | ppmu_g3d: ppmu_g3d@13220000 { | |
851 | compatible = "samsung,exynos-ppmu"; | |
852 | reg = <0x13220000 0x2000>; | |
853 | clocks = <&clock CLK_PPMUG3D>; | |
854 | clock-names = "ppmu"; | |
855 | status = "disabled"; | |
856 | }; | |
857 | ||
858 | ppmu_mfc_left: ppmu_mfc_left@13660000 { | |
859 | compatible = "samsung,exynos-ppmu"; | |
860 | reg = <0x13660000 0x2000>; | |
861 | clocks = <&clock CLK_PPMUMFC_L>; | |
862 | clock-names = "ppmu"; | |
863 | status = "disabled"; | |
864 | }; | |
865 | ||
866 | ppmu_mfc_right: ppmu_mfc_right@13670000 { | |
867 | compatible = "samsung,exynos-ppmu"; | |
868 | reg = <0x13670000 0x2000>; | |
869 | clocks = <&clock CLK_PPMUMFC_R>; | |
870 | clock-names = "ppmu"; | |
871 | status = "disabled"; | |
872 | }; | |
71d3a9fb MS |
873 | |
874 | sysmmu_mfc_l: sysmmu@13620000 { | |
875 | compatible = "samsung,exynos-sysmmu"; | |
876 | reg = <0x13620000 0x1000>; | |
877 | interrupt-parent = <&combiner>; | |
878 | interrupts = <5 5>; | |
879 | clock-names = "sysmmu", "master"; | |
880 | clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; | |
881 | power-domains = <&pd_mfc>; | |
882 | #iommu-cells = <0>; | |
883 | }; | |
884 | ||
885 | sysmmu_mfc_r: sysmmu@13630000 { | |
886 | compatible = "samsung,exynos-sysmmu"; | |
887 | reg = <0x13630000 0x1000>; | |
888 | interrupt-parent = <&combiner>; | |
889 | interrupts = <5 6>; | |
890 | clock-names = "sysmmu", "master"; | |
891 | clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; | |
892 | power-domains = <&pd_mfc>; | |
893 | #iommu-cells = <0>; | |
894 | }; | |
895 | ||
896 | sysmmu_tv: sysmmu@12E20000 { | |
897 | compatible = "samsung,exynos-sysmmu"; | |
898 | reg = <0x12E20000 0x1000>; | |
899 | interrupt-parent = <&combiner>; | |
900 | interrupts = <5 4>; | |
901 | clock-names = "sysmmu", "master"; | |
902 | clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; | |
903 | power-domains = <&pd_tv>; | |
904 | #iommu-cells = <0>; | |
905 | }; | |
906 | ||
907 | sysmmu_fimc0: sysmmu@11A20000 { | |
908 | compatible = "samsung,exynos-sysmmu"; | |
909 | reg = <0x11A20000 0x1000>; | |
910 | interrupt-parent = <&combiner>; | |
911 | interrupts = <4 2>; | |
912 | clock-names = "sysmmu", "master"; | |
913 | clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>; | |
914 | power-domains = <&pd_cam>; | |
915 | #iommu-cells = <0>; | |
916 | }; | |
917 | ||
918 | sysmmu_fimc1: sysmmu@11A30000 { | |
919 | compatible = "samsung,exynos-sysmmu"; | |
920 | reg = <0x11A30000 0x1000>; | |
921 | interrupt-parent = <&combiner>; | |
922 | interrupts = <4 3>; | |
923 | clock-names = "sysmmu", "master"; | |
924 | clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>; | |
925 | power-domains = <&pd_cam>; | |
926 | #iommu-cells = <0>; | |
927 | }; | |
928 | ||
929 | sysmmu_fimc2: sysmmu@11A40000 { | |
930 | compatible = "samsung,exynos-sysmmu"; | |
931 | reg = <0x11A40000 0x1000>; | |
932 | interrupt-parent = <&combiner>; | |
933 | interrupts = <4 4>; | |
934 | clock-names = "sysmmu", "master"; | |
935 | clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>; | |
936 | power-domains = <&pd_cam>; | |
937 | #iommu-cells = <0>; | |
938 | }; | |
939 | ||
940 | sysmmu_fimc3: sysmmu@11A50000 { | |
941 | compatible = "samsung,exynos-sysmmu"; | |
942 | reg = <0x11A50000 0x1000>; | |
943 | interrupt-parent = <&combiner>; | |
944 | interrupts = <4 5>; | |
945 | clock-names = "sysmmu", "master"; | |
946 | clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>; | |
947 | power-domains = <&pd_cam>; | |
948 | #iommu-cells = <0>; | |
949 | }; | |
950 | ||
951 | sysmmu_jpeg: sysmmu@11A60000 { | |
952 | compatible = "samsung,exynos-sysmmu"; | |
953 | reg = <0x11A60000 0x1000>; | |
954 | interrupt-parent = <&combiner>; | |
955 | interrupts = <4 6>; | |
956 | clock-names = "sysmmu", "master"; | |
957 | clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; | |
958 | power-domains = <&pd_cam>; | |
959 | #iommu-cells = <0>; | |
960 | }; | |
961 | ||
962 | sysmmu_rotator: sysmmu@12A30000 { | |
963 | compatible = "samsung,exynos-sysmmu"; | |
964 | reg = <0x12A30000 0x1000>; | |
965 | interrupt-parent = <&combiner>; | |
966 | interrupts = <5 0>; | |
967 | clock-names = "sysmmu", "master"; | |
968 | clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; | |
71d3a9fb MS |
969 | #iommu-cells = <0>; |
970 | }; | |
971 | ||
972 | sysmmu_fimd0: sysmmu@11E20000 { | |
973 | compatible = "samsung,exynos-sysmmu"; | |
974 | reg = <0x11E20000 0x1000>; | |
975 | interrupt-parent = <&combiner>; | |
976 | interrupts = <5 2>; | |
977 | clock-names = "sysmmu", "master"; | |
978 | clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>; | |
979 | power-domains = <&pd_lcd0>; | |
980 | #iommu-cells = <0>; | |
981 | }; | |
a452977c | 982 | |
6c5eb1db KK |
983 | sss: sss@10830000 { |
984 | compatible = "samsung,exynos4210-secss"; | |
985 | reg = <0x10830000 0x300>; | |
986 | interrupts = <0 112 0>; | |
987 | clocks = <&clock CLK_SSS>; | |
988 | clock-names = "secss"; | |
6c5eb1db KK |
989 | }; |
990 | ||
a452977c KK |
991 | prng: rng@10830400 { |
992 | compatible = "samsung,exynos4-rng"; | |
993 | reg = <0x10830400 0x200>; | |
994 | clocks = <&clock CLK_SSS>; | |
995 | clock-names = "secss"; | |
a452977c | 996 | }; |
b571abb3 | 997 | }; |