[deliverable/linux.git] / arch / arm / boot / dts / exynos4210.dtsi

/*
 * Samsung's Exynos4210 SoC device tree source
 *
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 * Copyright (c) 2010-2011 Linaro Ltd.
 *		www.linaro.org
 *
 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
 * nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include "exynos4.dtsi"
#include "exynos4210-pinctrl.dtsi"
#include "exynos4-cpu-thermal.dtsi"

/ {
	compatible = "samsung,exynos4210", "samsung,exynos4";

	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		pinctrl2 = &pinctrl_2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@900 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0x900>;
			cooling-min-level = <4>;
			cooling-max-level = <2>;
			#cooling-cells = <2>; /* min followed by max */
		};

		cpu@901 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0x901>;
		};
	};

	sysram: sysram@02020000 {
		compatible = "mmio-sram";
		reg = <0x02020000 0x20000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x02020000 0x20000>;

		smp-sysram@0 {
			compatible = "samsung,exynos4210-sysram";
			reg = <0x0 0x1000>;
		};

		smp-sysram@1f000 {
			compatible = "samsung,exynos4210-sysram-ns";
			reg = <0x1f000 0x1000>;
		};
	};

	pd_lcd1: lcd1-power-domain@10023CA0 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10023CA0 0x20>;
		#power-domain-cells = <0>;
	};

	l2c: l2-cache-controller@10502000 {
		compatible = "arm,pl310-cache";
		reg = <0x10502000 0x1000>;
		cache-unified;
		cache-level = <2>;
		arm,tag-latency = <2 2 1>;
		arm,data-latency = <2 2 1>;
	};

	mct: mct@10050000 {
		compatible = "samsung,exynos4210-mct";
		reg = <0x10050000 0x800>;
		interrupt-parent = <&mct_map>;
		interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
		clock-names = "fin_pll", "mct";

		mct_map: mct-map {
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = <0 &gic 0 57 0>,
					<1 &gic 0 69 0>,
					<2 &combiner 12 6>,
					<3 &combiner 12 7>,
					<4 &gic 0 42 0>,
					<5 &gic 0 48 0>;
		};
	};

	clock: clock-controller@10030000 {
		compatible = "samsung,exynos4210-clock";
		reg = <0x10030000 0x20000>;
		#clock-cells = <1>;
	};

	pinctrl_0: pinctrl@11400000 {
		compatible = "samsung,exynos4210-pinctrl";
		reg = <0x11400000 0x1000>;
		interrupts = <0 47 0>;
	};

	pinctrl_1: pinctrl@11000000 {
		compatible = "samsung,exynos4210-pinctrl";
		reg = <0x11000000 0x1000>;
		interrupts = <0 46 0>;

		wakup_eint: wakeup-interrupt-controller {
			compatible = "samsung,exynos4210-wakeup-eint";
			interrupt-parent = <&gic>;
			interrupts = <0 32 0>;
		};
	};

	pinctrl_2: pinctrl@03860000 {
		compatible = "samsung,exynos4210-pinctrl";
		reg = <0x03860000 0x1000>;
	};

	tmu: tmu@100C0000 {
		compatible = "samsung,exynos4210-tmu";
		interrupt-parent = <&combiner>;
		reg = <0x100C0000 0x100>;
		interrupts = <2 4>;
		clocks = <&clock CLK_TMU_APBIF>;
		clock-names = "tmu_apbif";
		samsung,tmu_gain = <15>;
		samsung,tmu_reference_voltage = <7>;
		status = "disabled";
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tmu 0>;

			trips {
			      cpu_alert0: cpu-alert-0 {
				      temperature = <85000>; /* millicelsius */
			      };
			      cpu_alert1: cpu-alert-1 {
				      temperature = <100000>; /* millicelsius */
			      };
			      cpu_alert2: cpu-alert-2 {
				      temperature = <110000>; /* millicelsius */
			      };
			};
		};
	};

	g2d: g2d@12800000 {
		compatible = "samsung,s5pv210-g2d";
		reg = <0x12800000 0x1000>;
		interrupts = <0 89 0>;
		clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
		clock-names = "sclk_fimg2d", "fimg2d";
		iommus = <&sysmmu_g2d>;
		status = "disabled";
	};

	camera {
		clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
			 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
		clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";

		fimc_0: fimc@11800000 {
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,cam-if;
		};

		fimc_1: fimc@11810000 {
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,cam-if;
		};

		fimc_2: fimc@11820000 {
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,lcd-wb;
		};

		fimc_3: fimc@11830000 {
			samsung,pix-limits = <1920 8192 1366 1920>;
			samsung,rotators = <0>;
			samsung,mainscaler-ext;
			samsung,lcd-wb;
		};
	};

	mixer: mixer@12C10000 {
		clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
			"sclk_mixer";
		clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
			<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
			<&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
	};

	ppmu_lcd1: ppmu_lcd1@12240000 {
		compatible = "samsung,exynos-ppmu";
		reg = <0x12240000 0x2000>;
		clocks = <&clock CLK_PPMULCD1>;
		clock-names = "ppmu";
		status = "disabled";
	};

	sysmmu_g2d: sysmmu@12A20000 {
		compatible = "samsung,exynos-sysmmu";
		reg = <0x12A20000 0x1000>;
		interrupt-parent = <&combiner>;
		interrupts = <4 7>;
		clock-names = "sysmmu", "master";
		clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
		power-domains = <&pd_lcd0>;
		#iommu-cells = <0>;
	};

	sysmmu_fimd1: sysmmu@12220000 {
		compatible = "samsung,exynos-sysmmu";
		interrupt-parent = <&combiner>;
		reg = <0x12220000 0x1000>;
		interrupts = <5 3>;
		clock-names = "sysmmu", "master";
		clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
		power-domains = <&pd_lcd1>;
		#iommu-cells = <0>;
	};
};

&gic {
	cpu-offset = <0x8000>;
};

&combiner {
	samsung,combiner-nr = <16>;
	interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
		     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
		     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
		     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
};

&pmu_system_controller {
	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
			"clkout4", "clkout8", "clkout9";
	clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
		<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
		<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
	#clock-cells = <1>;
};
Commit	Line	Data
0561ceab TA	1	/*
	2	* Samsung's Exynos4210 SoC device tree source
	3	*
	4	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	* Copyright (c) 2010-2011 Linaro Ltd.
	7	* www.linaro.org
	8	*
	9	* Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
	10	* based board files can include this file and provide values for board specfic
	11	* bindings.
	12	*
	13	* Note: This file does not include device nodes for all the controllers in
	14	* Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
	15	* nodes can be added to this file.
	16	*
	17	* This program is free software; you can redistribute it and/or modify
	18	* it under the terms of the GNU General Public License version 2 as
	19	* published by the Free Software Foundation.
	20	*/
	21
3799279f PV	22	#include "exynos4.dtsi"
3799279f PV	23	#include "exynos4210-pinctrl.dtsi"
9843a223	24	#include "exynos4-cpu-thermal.dtsi"
0561ceab TA	25
0561ceab TA	26	/ {
8bdb31b4	27	compatible = "samsung,exynos4210", "samsung,exynos4";
0561ceab	28
4980c39b	29	aliases {
87711d8c TA	30	pinctrl0 = &pinctrl_0;
	31	pinctrl1 = &pinctrl_1;
	32	pinctrl2 = &pinctrl_2;
4980c39b TA	33	};
4980c39b TA	34
e540920c BZ	35	cpus {
	36	#address-cells = <1>;
	37	#size-cells = <0>;
	38
bf4a0bed	39	cpu0: cpu@900 {
e540920c BZ	40	device_type = "cpu";
	41	compatible = "arm,cortex-a9";
	42	reg = <0x900>;
bf4a0bed LM	43	cooling-min-level = <4>;
	44	cooling-max-level = <2>;
	45	#cooling-cells = <2>; /* min followed by max */
e540920c BZ	46	};
	47
	48	cpu@901 {
	49	device_type = "cpu";
	50	compatible = "arm,cortex-a9";
	51	reg = <0x901>;
	52	};
	53	};
	54
9c41221e	55	sysram: sysram@02020000 {
b3205dea SK	56	compatible = "mmio-sram";
	57	reg = <0x02020000 0x20000>;
	58	#address-cells = <1>;
	59	#size-cells = <1>;
	60	ranges = <0 0x02020000 0x20000>;
	61
	62	smp-sysram@0 {
	63	compatible = "samsung,exynos4210-sysram";
	64	reg = <0x0 0x1000>;
	65	};
	66
	67	smp-sysram@1f000 {
	68	compatible = "samsung,exynos4210-sysram-ns";
	69	reg = <0x1f000 0x1000>;
	70	};
	71	};
	72
91d88f03 TF	73	pd_lcd1: lcd1-power-domain@10023CA0 {
	74	compatible = "samsung,exynos4210-pd";
	75	reg = <0x10023CA0 0x20>;
0da65870	76	#power-domain-cells = <0>;
91d88f03 TF	77	};
91d88f03 TF	78
56b60b8b TF	79	l2c: l2-cache-controller@10502000 {
	80	compatible = "arm,pl310-cache";
	81	reg = <0x10502000 0x1000>;
	82	cache-unified;
	83	cache-level = <2>;
	84	arm,tag-latency = <2 2 1>;
	85	arm,data-latency = <2 2 1>;
	86	};
	87
9c41221e	88	mct: mct@10050000 {
bbd9700a TA	89	compatible = "samsung,exynos4210-mct";
bbd9700a TA	90	reg = <0x10050000 0x800>;
bbd9700a	91	interrupt-parent = <&mct_map>;
84ee1c15	92	interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
1c75a78a	93	clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
7ad34337	94	clock-names = "fin_pll", "mct";
bbd9700a TA	95
bbd9700a TA	96	mct_map: mct-map {
84ee1c15	97	#interrupt-cells = <1>;
bbd9700a TA	98	#address-cells = <0>;
bbd9700a TA	99	#size-cells = <0>;
84ee1c15 TF	100	interrupt-map = <0 &gic 0 57 0>,
	101	<1 &gic 0 69 0>,
	102	<2 &combiner 12 6>,
	103	<3 &combiner 12 7>,
	104	<4 &gic 0 42 0>,
	105	<5 &gic 0 48 0>;
bbd9700a TA	106	};
	107	};
	108
e7787aed	109	clock: clock-controller@10030000 {
d8bafc87 TA	110	compatible = "samsung,exynos4210-clock";
	111	reg = <0x10030000 0x20000>;
	112	#clock-cells = <1>;
	113	};
	114
87711d8c	115	pinctrl_0: pinctrl@11400000 {
b533c868	116	compatible = "samsung,exynos4210-pinctrl";
87711d8c TA	117	reg = <0x11400000 0x1000>;
87711d8c TA	118	interrupts = <0 47 0>;
87711d8c TA	119	};
	120
	121	pinctrl_1: pinctrl@11000000 {
b533c868	122	compatible = "samsung,exynos4210-pinctrl";
87711d8c TA	123	reg = <0x11000000 0x1000>;
87711d8c TA	124	interrupts = <0 46 0>;
87711d8c TA	125
	126	wakup_eint: wakeup-interrupt-controller {
	127	compatible = "samsung,exynos4210-wakeup-eint";
	128	interrupt-parent = <&gic>;
a04b07c0	129	interrupts = <0 32 0>;
87711d8c TA	130	};
	131	};
	132
	133	pinctrl_2: pinctrl@03860000 {
b533c868	134	compatible = "samsung,exynos4210-pinctrl";
87711d8c TA	135	reg = <0x03860000 0x1000>;
	136	};
	137
9843a223	138	tmu: tmu@100C0000 {
8d4155db ADK	139	compatible = "samsung,exynos4210-tmu";
	140	interrupt-parent = <&combiner>;
	141	reg = <0x100C0000 0x100>;
	142	interrupts = <2 4>;
1c75a78a	143	clocks = <&clock CLK_TMU_APBIF>;
e6199af6	144	clock-names = "tmu_apbif";
9843a223 LM	145	samsung,tmu_gain = <15>;
9843a223 LM	146	samsung,tmu_reference_voltage = <7>;
e6199af6	147	status = "disabled";
8d4155db	148	};
66d302ac	149
9843a223 LM	150	thermal-zones {
	151	cpu_thermal: cpu-thermal {
	152	polling-delay-passive = <0>;
	153	polling-delay = <0>;
	154	thermal-sensors = <&tmu 0>;
	155
	156	trips {
	157	cpu_alert0: cpu-alert-0 {
	158	temperature = <85000>; /* millicelsius */
	159	};
	160	cpu_alert1: cpu-alert-1 {
	161	temperature = <100000>; /* millicelsius */
	162	};
	163	cpu_alert2: cpu-alert-2 {
	164	temperature = <110000>; /* millicelsius */
	165	};
	166	};
	167	};
	168	};
	169
9c41221e	170	g2d: g2d@12800000 {
66d302ac SK	171	compatible = "samsung,s5pv210-g2d";
	172	reg = <0x12800000 0x1000>;
	173	interrupts = <0 89 0>;
1c75a78a	174	clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
37bf5796	175	clock-names = "sclk_fimg2d", "fimg2d";
71d3a9fb	176	iommus = <&sysmmu_g2d>;
66d302ac SK	177	status = "disabled";
66d302ac SK	178	};
54a8896a SN	179
54a8896a SN	180	camera {
1c75a78a AH	181	clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
1c75a78a AH	182	<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
54a8896a SN	183	clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
	184
	185	fimc_0: fimc@11800000 {
	186	samsung,pix-limits = <4224 8192 1920 4224>;
	187	samsung,mainscaler-ext;
	188	samsung,cam-if;
	189	};
	190
	191	fimc_1: fimc@11810000 {
	192	samsung,pix-limits = <4224 8192 1920 4224>;
	193	samsung,mainscaler-ext;
	194	samsung,cam-if;
	195	};
	196
	197	fimc_2: fimc@11820000 {
	198	samsung,pix-limits = <4224 8192 1920 4224>;
	199	samsung,mainscaler-ext;
	200	samsung,lcd-wb;
	201	};
	202
	203	fimc_3: fimc@11830000 {
	204	samsung,pix-limits = <1920 8192 1366 1920>;
	205	samsung,rotators = <0>;
	206	samsung,mainscaler-ext;
	207	samsung,lcd-wb;
	208	};
	209	};
30e0e476	210
ed80d4ca MS	211	mixer: mixer@12C10000 {
	212	clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
	213	"sclk_mixer";
	214	clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
	215	<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
	216	<&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
	217	};
	218
30e0e476 CC	219	ppmu_lcd1: ppmu_lcd1@12240000 {
	220	compatible = "samsung,exynos-ppmu";
	221	reg = <0x12240000 0x2000>;
	222	clocks = <&clock CLK_PPMULCD1>;
	223	clock-names = "ppmu";
	224	status = "disabled";
	225	};
71d3a9fb MS	226
	227	sysmmu_g2d: sysmmu@12A20000 {
	228	compatible = "samsung,exynos-sysmmu";
	229	reg = <0x12A20000 0x1000>;
	230	interrupt-parent = <&combiner>;
	231	interrupts = <4 7>;
	232	clock-names = "sysmmu", "master";
	233	clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
	234	power-domains = <&pd_lcd0>;
	235	#iommu-cells = <0>;
	236	};
	237
	238	sysmmu_fimd1: sysmmu@12220000 {
	239	compatible = "samsung,exynos-sysmmu";
	240	interrupt-parent = <&combiner>;
	241	reg = <0x12220000 0x1000>;
	242	interrupts = <5 3>;
	243	clock-names = "sysmmu", "master";
	244	clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
	245	power-domains = <&pd_lcd1>;
	246	#iommu-cells = <0>;
	247	};
0561ceab	248	};
070bb0f0 KK	249
	250	&gic {
	251	cpu-offset = <0x8000>;
	252	};
	253
	254	&combiner {
	255	samsung,combiner-nr = <16>;
	256	interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
	257	<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
	258	<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
	259	<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
	260	};
	261
	262	&pmu_system_controller {
	263	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
	264	"clkout4", "clkout8", "clkout9";
	265	clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
	266	<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
	267	<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
	268	#clock-cells = <1>;
	269	};