projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 0f7238a1 TF |
1 | /* |
| 2 | * Samsung's Exynos4412 SoC device tree source | |
| 3 | * | |
| 4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
| 5 | * http://www.samsung.com | |
| 6 | * | |
| 7 | * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 | |
| 8 | * based board files can include this file and provide values for board specfic | |
| 9 | * bindings. | |
| 10 | * | |
| 11 | * Note: This file does not include device nodes for all the controllers in | |
| 12 | * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional | |
| 13 | * nodes can be added to this file. | |
| 14 | * | |
| 15 | * This program is free software; you can redistribute it and/or modify | |
| 16 | * it under the terms of the GNU General Public License version 2 as | |
| 17 | * published by the Free Software Foundation. | |
| 18 | */ | |
| 19 | ||
| 3799279f | 20 | #include "exynos4x12.dtsi" |
| 0f7238a1 TF |
21 | |
| 22 | / { | |
| 8bdb31b4 | 23 | compatible = "samsung,exynos4412", "samsung,exynos4"; |
| 0f7238a1 | 24 | |
| e540920c BZ |
25 | cpus { |
| 26 | #address-cells = <1>; | |
| 27 | #size-cells = <0>; | |
| 28 | ||
| bf4a0bed | 29 | cpu0: cpu@A00 { |
| e540920c BZ |
30 | device_type = "cpu"; |
| 31 | compatible = "arm,cortex-a9"; | |
| 32 | reg = <0xA00>; | |
| f4499741 BZ |
33 | clocks = <&clock CLK_ARM_CLK>; |
| 34 | clock-names = "cpu"; | |
| 35 | operating-points-v2 = <&cpu0_opp_table>; | |
| bf4a0bed LM |
36 | cooling-min-level = <13>; |
| 37 | cooling-max-level = <7>; | |
| 38 | #cooling-cells = <2>; /* min followed by max */ | |
| e540920c BZ |
39 | }; |
| 40 | ||
| 41 | cpu@A01 { | |
| 42 | device_type = "cpu"; | |
| 43 | compatible = "arm,cortex-a9"; | |
| 44 | reg = <0xA01>; | |
| f4499741 | 45 | operating-points-v2 = <&cpu0_opp_table>; |
| e540920c BZ |
46 | }; |
| 47 | ||
| 48 | cpu@A02 { | |
| 49 | device_type = "cpu"; | |
| 50 | compatible = "arm,cortex-a9"; | |
| 51 | reg = <0xA02>; | |
| f4499741 | 52 | operating-points-v2 = <&cpu0_opp_table>; |
| e540920c BZ |
53 | }; |
| 54 | ||
| 55 | cpu@A03 { | |
| 56 | device_type = "cpu"; | |
| 57 | compatible = "arm,cortex-a9"; | |
| 58 | reg = <0xA03>; | |
| f4499741 BZ |
59 | operating-points-v2 = <&cpu0_opp_table>; |
| 60 | }; | |
| 61 | }; | |
| 62 | ||
| 63 | cpu0_opp_table: opp_table0 { | |
| 64 | compatible = "operating-points-v2"; | |
| 65 | opp-shared; | |
| 66 | ||
| 67 | opp00 { | |
| 68 | opp-hz = /bits/ 64 <200000000>; | |
| 69 | opp-microvolt = <900000>; | |
| 70 | clock-latency-ns = <200000>; | |
| 71 | }; | |
| 72 | opp01 { | |
| 73 | opp-hz = /bits/ 64 <300000000>; | |
| 74 | opp-microvolt = <900000>; | |
| 75 | clock-latency-ns = <200000>; | |
| 76 | }; | |
| 77 | opp02 { | |
| 78 | opp-hz = /bits/ 64 <400000000>; | |
| 79 | opp-microvolt = <925000>; | |
| 80 | clock-latency-ns = <200000>; | |
| 81 | }; | |
| 82 | opp03 { | |
| 83 | opp-hz = /bits/ 64 <500000000>; | |
| 84 | opp-microvolt = <950000>; | |
| 85 | clock-latency-ns = <200000>; | |
| 86 | }; | |
| 87 | opp04 { | |
| 88 | opp-hz = /bits/ 64 <600000000>; | |
| 89 | opp-microvolt = <975000>; | |
| 90 | clock-latency-ns = <200000>; | |
| 91 | }; | |
| 92 | opp05 { | |
| 93 | opp-hz = /bits/ 64 <700000000>; | |
| 94 | opp-microvolt = <987500>; | |
| 95 | clock-latency-ns = <200000>; | |
| 96 | }; | |
| 97 | opp06 { | |
| 98 | opp-hz = /bits/ 64 <800000000>; | |
| 99 | opp-microvolt = <1000000>; | |
| 100 | clock-latency-ns = <200000>; | |
| 101 | }; | |
| 102 | opp07 { | |
| 103 | opp-hz = /bits/ 64 <900000000>; | |
| 104 | opp-microvolt = <1037500>; | |
| 105 | clock-latency-ns = <200000>; | |
| 106 | }; | |
| 107 | opp08 { | |
| 108 | opp-hz = /bits/ 64 <1000000000>; | |
| 109 | opp-microvolt = <1087500>; | |
| 110 | clock-latency-ns = <200000>; | |
| 111 | }; | |
| 112 | opp09 { | |
| 113 | opp-hz = /bits/ 64 <1100000000>; | |
| 114 | opp-microvolt = <1137500>; | |
| 115 | clock-latency-ns = <200000>; | |
| 116 | }; | |
| 117 | opp10 { | |
| 118 | opp-hz = /bits/ 64 <1200000000>; | |
| 119 | opp-microvolt = <1187500>; | |
| 120 | clock-latency-ns = <200000>; | |
| 121 | }; | |
| 122 | opp11 { | |
| 123 | opp-hz = /bits/ 64 <1300000000>; | |
| 124 | opp-microvolt = <1250000>; | |
| 125 | clock-latency-ns = <200000>; | |
| 126 | }; | |
| 127 | opp12 { | |
| 128 | opp-hz = /bits/ 64 <1400000000>; | |
| 129 | opp-microvolt = <1287500>; | |
| 130 | clock-latency-ns = <200000>; | |
| 131 | }; | |
| 132 | opp13 { | |
| 133 | opp-hz = /bits/ 64 <1500000000>; | |
| 134 | opp-microvolt = <1350000>; | |
| 135 | clock-latency-ns = <200000>; | |
| 136 | turbo-mode; | |
| e540920c BZ |
137 | }; |
| 138 | }; | |
| 139 | ||
| 6f4b82a3 CP |
140 | pmu { |
| 141 | interrupts = <2 2>, <3 2>, <18 2>, <19 2>; | |
| 142 | }; | |
| 08c4b441 | 143 | }; |
| 6f4b82a3 | 144 | |
| 08c4b441 KK |
145 | &pmu_system_controller { |
| 146 | compatible = "samsung,exynos4412-pmu", "syscon"; | |
| 147 | }; | |
| 7b9613ac | 148 | |
| 08c4b441 KK |
149 | &combiner { |
| 150 | samsung,combiner-nr = <20>; | |
| 151 | }; | |
| 152 | ||
| 153 | &gic { | |
| 154 | cpu-offset = <0x4000>; | |
| 0f7238a1 | 155 | }; |