[deliverable/linux.git] / arch / arm / boot / dts / exynos4415.dtsi

/*
 * Samsung's Exynos4415 SoC device tree source
 *
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
 *
 * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415
 * based board files can include this file and provide values for board
 * specific bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional
 * nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "skeleton.dtsi"
#include <dt-bindings/clock/exynos4415.h>
#include <dt-bindings/clock/exynos-audss-clk.h>

/ {
	compatible = "samsung,exynos4415";
	interrupt-parent = <&gic>;

	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		pinctrl2 = &pinctrl_2;
		mshc0 = &mshc_0;
		mshc1 = &mshc_1;
		mshc2 = &mshc_2;
		spi0 = &spi_0;
		spi1 = &spi_1;
		spi2 = &spi_2;
		i2c0 = &i2c_0;
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		i2c4 = &i2c_4;
		i2c5 = &i2c_5;
		i2c6 = &i2c_6;
		i2c7 = &i2c_7;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@a00 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0xa00>;
			clock-frequency = <1600000000>;
		};

		cpu1: cpu@a01 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0xa01>;
			clock-frequency = <1600000000>;
		};

		cpu2: cpu@a02 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0xa02>;
			clock-frequency = <1600000000>;
		};

		cpu3: cpu@a03 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0xa03>;
			clock-frequency = <1600000000>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		sysram@02020000 {
			compatible = "mmio-sram";
			reg = <0x02020000 0x50000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x02020000 0x50000>;

			smp-sysram@0 {
				compatible = "samsung,exynos4210-sysram";
				reg = <0x0 0x1000>;
			};

			smp-sysram@4f000 {
				compatible = "samsung,exynos4210-sysram-ns";
				reg = <0x4f000 0x1000>;
			};
		};

		pinctrl_2: pinctrl@03860000 {
			compatible = "samsung,exynos4415-pinctrl";
			reg = <0x03860000 0x1000>;
			interrupts = <0 242 0>;
		};

		chipid@10000000 {
			compatible = "samsung,exynos4210-chipid";
			reg = <0x10000000 0x100>;
		};

		sysreg_system_controller: syscon@10010000 {
			compatible = "samsung,exynos4-sysreg", "syscon";
			reg = <0x10010000 0x400>;
		};

		pmu_system_controller: system-controller@10020000 {
			compatible = "samsung,exynos4415-pmu", "syscon";
			reg = <0x10020000 0x4000>;
		};

		mipi_phy: video-phy@10020710 {
			compatible = "samsung,s5pv210-mipi-video-phy";
			reg = <0x10020710 8>;
			#phy-cells = <1>;
		};

		pd_cam: cam-power-domain@10024000 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10024000 0x20>;
			#power-domain-cells = <0>;
		};

		pd_tv: tv-power-domain@10024020 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10024020 0x20>;
			#power-domain-cells = <0>;
		};

		pd_mfc: mfc-power-domain@10024040 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10024040 0x20>;
			#power-domain-cells = <0>;
		};

		pd_g3d: g3d-power-domain@10024060 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10024060 0x20>;
			#power-domain-cells = <0>;
		};

		pd_lcd0: lcd0-power-domain@10024080 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10024080 0x20>;
			#power-domain-cells = <0>;
		};

		pd_isp0: isp0-power-domain@100240A0 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x100240A0 0x20>;
			#power-domain-cells = <0>;
		};

		pd_isp1: isp1-power-domain@100240E0 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x100240E0 0x20>;
			#power-domain-cells = <0>;
		};

		cmu: clock-controller@10030000 {
			compatible = "samsung,exynos4415-cmu";
			reg = <0x10030000 0x18000>;
			#clock-cells = <1>;
		};

		rtc: rtc@10070000 {
			compatible = "samsung,exynos3250-rtc";
			reg = <0x10070000 0x100>;
			interrupts = <0 73 0>, <0 74 0>;
			status = "disabled";
		};

		mct@10050000 {
			compatible = "samsung,exynos4210-mct";
			reg = <0x10050000 0x800>;
			interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
				     <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
			clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
			clock-names = "fin_pll", "mct";
		};

		gic: interrupt-controller@10481000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x10481000 0x1000>,
			      <0x10482000 0x1000>,
			      <0x10484000 0x2000>,
			      <0x10486000 0x2000>;
			interrupts = <1 9 0xf04>;
		};

		l2c: l2-cache-controller@10502000 {
			compatible = "arm,pl310-cache";
			reg = <0x10502000 0x1000>;
			cache-unified;
			cache-level = <2>;
			arm,tag-latency = <2 2 1>;
			arm,data-latency = <3 2 1>;
			arm,double-linefill = <1>;
			arm,double-linefill-incr = <0>;
			arm,double-linefill-wrap = <1>;
			arm,prefetch-drop = <1>;
			arm,prefetch-offset = <7>;
		};

		cmu_dmc: clock-controller@105C0000 {
			compatible = "samsung,exynos4415-cmu-dmc";
			reg = <0x105C0000 0x3000>;
			#clock-cells = <1>;
		};

		pinctrl_1: pinctrl@11000000 {
			compatible = "samsung,exynos4415-pinctrl";
			reg = <0x11000000 0x1000>;
			interrupts = <0 225 0>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynos4210-wakeup-eint";
				interrupt-parent = <&gic>;
				interrupts = <0 48 0>;
			};
		};

		pinctrl_0: pinctrl@11400000 {
			compatible = "samsung,exynos4415-pinctrl";
			reg = <0x11400000 0x1000>;
			interrupts = <0 240 0>;
		};

		hsotg: hsotg@12480000 {
			compatible = "samsung,s3c6400-hsotg";
			reg = <0x12480000 0x20000>;
			interrupts = <0 141 0>;
			clocks = <&cmu CLK_USBDEVICE>;
			clock-names = "otg";
			phys = <&exynos_usbphy 0>;
			phy-names = "usb2-phy";
			status = "disabled";
		};

		mshc_0: mshc@12510000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12510000 0x1000>;
			interrupts = <0 142 0>;
			clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mshc_1: mshc@12520000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12520000 0x1000>;
			interrupts = <0 143 0>;
			clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mshc_2: mshc@12530000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12530000 0x1000>;
			interrupts = <0 144 0>;
			clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		ehci: ehci@12580000 {
			compatible = "samsung,exynos4210-ehci";
			reg = <0x12580000 0x100>;
			interrupts = <0 140 0>;
			clocks = <&cmu CLK_USBHOST>;
			clock-names = "usbhost";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				phys = <&exynos_usbphy 1>;
				status = "disabled";
			};
			port@1 {
				reg = <1>;
				phys = <&exynos_usbphy 2>;
				status = "disabled";
			};
			port@2 {
				reg = <2>;
				phys = <&exynos_usbphy 3>;
				status = "disabled";
			};
		};

		ohci: ohci@12590000 {
			compatible = "samsung,exynos4210-ohci";
			reg = <0x12590000 0x100>;
			interrupts = <0 140 0>;
			clocks = <&cmu CLK_USBHOST>;
			clock-names = "usbhost";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				phys = <&exynos_usbphy 1>;
				status = "disabled";
			};
		};

		exynos_usbphy: exynos-usbphy@125B0000 {
			compatible = "samsung,exynos4x12-usb2-phy";
			reg = <0x125B0000 0x100>;
			samsung,pmureg-phandle = <&pmu_system_controller>;
			samsung,sysreg-phandle = <&sysreg_system_controller>;
			clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>;
			clock-names = "phy", "ref";
			#phy-cells = <1>;
			status = "disabled";
		};

		amba {
			compatible = "arm,amba-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			interrupt-parent = <&gic>;
			ranges;

			pdma0: pdma@12680000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x12680000 0x1000>;
				interrupts = <0 138 0>;
				clocks = <&cmu CLK_PDMA0>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};

			pdma1: pdma@12690000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x12690000 0x1000>;
				interrupts = <0 139 0>;
				clocks = <&cmu CLK_PDMA1>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};
		};

		adc: adc@126C0000 {
			compatible = "samsung,exynos3250-adc",
				     "samsung,exynos-adc-v2";
			reg = <0x126C0000 0x100>, <0x10020718 0x4>;
			interrupts = <0 137 0>;
			clock-names = "adc", "sclk";
			clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
			#io-channel-cells = <1>;
			io-channel-ranges;
			status = "disabled";
		};

		serial_0: serial@13800000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13800000 0x100>;
			interrupts = <0 109 0>;
			clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		serial_1: serial@13810000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13810000 0x100>;
			interrupts = <0 110 0>;
			clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		serial_2: serial@13820000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13820000 0x100>;
			interrupts = <0 111 0>;
			clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		serial_3: serial@13830000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13830000 0x100>;
			interrupts = <0 112 0>;
			clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		i2c_0: i2c@13860000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13860000 0x100>;
			interrupts = <0 113 0>;
			clocks = <&cmu CLK_I2C0>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_bus>;
			status = "disabled";
		};

		i2c_1: i2c@13870000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13870000 0x100>;
			interrupts = <0 114 0>;
			clocks = <&cmu CLK_I2C1>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_bus>;
			status = "disabled";
		};

		i2c_2: i2c@13880000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13880000 0x100>;
			interrupts = <0 115 0>;
			clocks = <&cmu CLK_I2C2>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2_bus>;
			status = "disabled";
		};

		i2c_3: i2c@13890000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13890000 0x100>;
			interrupts = <0 116 0>;
			clocks = <&cmu CLK_I2C3>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c3_bus>;
			status = "disabled";
		};

		i2c_4: i2c@138A0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138A0000 0x100>;
			interrupts = <0 117 0>;
			clocks = <&cmu CLK_I2C4>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c4_bus>;
			status = "disabled";
		};

		i2c_5: i2c@138B0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138B0000 0x100>;
			interrupts = <0 118 0>;
			clocks = <&cmu CLK_I2C5>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c5_bus>;
			status = "disabled";
		};

		i2c_6: i2c@138C0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138C0000 0x100>;
			interrupts = <0 119 0>;
			clocks = <&cmu CLK_I2C6>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c6_bus>;
			status = "disabled";
		};

		i2c_7: i2c@138D0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138D0000 0x100>;
			interrupts = <0 120 0>;
			clocks = <&cmu CLK_I2C7>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c7_bus>;
			status = "disabled";
		};

		spi_0: spi@13920000 {
			compatible = "samsung,exynos4210-spi";
			reg = <0x13920000 0x100>;
			interrupts = <0 121 0>;
			dmas = <&pdma0 7>, <&pdma0 6>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
			clock-names = "spi", "spi_busclk0";
			samsung,spi-src-clk = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi0_bus>;
			status = "disabled";
		};

		spi_1: spi@13930000 {
			compatible = "samsung,exynos4210-spi";
			reg = <0x13930000 0x100>;
			interrupts = <0 122 0>;
			dmas = <&pdma1 7>, <&pdma1 6>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
			clock-names = "spi", "spi_busclk0";
			samsung,spi-src-clk = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi1_bus>;
			status = "disabled";
		};

		spi_2: spi@13940000 {
			compatible = "samsung,exynos4210-spi";
			reg = <0x13940000 0x100>;
			interrupts = <0 123 0>;
			dmas = <&pdma0 9>, <&pdma0 8>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>;
			clock-names = "spi", "spi_busclk0";
			samsung,spi-src-clk = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi2_bus>;
			status = "disabled";
		};

		clock_audss: clock-controller@03810000 {
			compatible = "samsung,exynos4210-audss-clock";
			reg = <0x03810000 0x0C>;
			#clock-cells = <1>;
		};

		i2s0: i2s@3830000 {
			compatible = "samsung,s5pv210-i2s";
			reg = <0x03830000 0x100>;
			interrupts = <0 124 0>;
			clocks = <&clock_audss EXYNOS_I2S_BUS>,
				<&clock_audss EXYNOS_SCLK_I2S>;
			clock-names = "iis", "i2s_opclk0";
			dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>;
			dma-names = "tx", "rx", "tx-sec";
			pinctrl-names = "default";
			pinctrl-0 = <&i2s0_bus>;
			samsung,idma-addr = <0x03000000>;
			status = "disabled";
		};

		pwm: pwm@139D0000 {
			compatible = "samsung,exynos4210-pwm";
			reg = <0x139D0000 0x1000>;
			interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
				     <0 107 0>, <0 108 0>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		pmu {
			compatible = "arm,cortex-a9-pmu";
			interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
		};
	};
};

#include "exynos4415-pinctrl.dtsi"
Commit	Line	Data
9246e7ff CC	1	/*
	2	* Samsung's Exynos4415 SoC device tree source
	3	*
	4	* Copyright (c) 2014 Samsung Electronics Co., Ltd.
	5	*
	6	* Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415
	7	* based board files can include this file and provide values for board
	8	* specific bindings.
	9	*
	10	* Note: This file does not include device nodes for all the controllers in
	11	* Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional
	12	* nodes can be added to this file.
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License version 2 as
	16	* published by the Free Software Foundation.
	17	*/
	18
	19	#include "skeleton.dtsi"
	20	#include <dt-bindings/clock/exynos4415.h>
	21	#include <dt-bindings/clock/exynos-audss-clk.h>
	22
	23	/ {
	24	compatible = "samsung,exynos4415";
	25	interrupt-parent = <&gic>;
	26
	27	aliases {
	28	pinctrl0 = &pinctrl_0;
	29	pinctrl1 = &pinctrl_1;
	30	pinctrl2 = &pinctrl_2;
	31	mshc0 = &mshc_0;
	32	mshc1 = &mshc_1;
	33	mshc2 = &mshc_2;
	34	spi0 = &spi_0;
	35	spi1 = &spi_1;
	36	spi2 = &spi_2;
	37	i2c0 = &i2c_0;
	38	i2c1 = &i2c_1;
	39	i2c2 = &i2c_2;
	40	i2c3 = &i2c_3;
	41	i2c4 = &i2c_4;
	42	i2c5 = &i2c_5;
	43	i2c6 = &i2c_6;
	44	i2c7 = &i2c_7;
	45	};
	46
	47	cpus {
	48	#address-cells = <1>;
	49	#size-cells = <0>;
	50
	51	cpu0: cpu@a00 {
	52	device_type = "cpu";
	53	compatible = "arm,cortex-a9";
	54	reg = <0xa00>;
	55	clock-frequency = <1600000000>;
	56	};
	57
	58	cpu1: cpu@a01 {
	59	device_type = "cpu";
	60	compatible = "arm,cortex-a9";
	61	reg = <0xa01>;
	62	clock-frequency = <1600000000>;
	63	};
	64
65	cpu2: cpu@a02 {
66	device_type = "cpu";
67	compatible = "arm,cortex-a9";
68	reg = <0xa02>;
69	clock-frequency = <1600000000>;
70	};
71
72	cpu3: cpu@a03 {
73	device_type = "cpu";
74	compatible = "arm,cortex-a9";
75	reg = <0xa03>;
76	clock-frequency = <1600000000>;
77	};
78	};
79
80	soc: soc {
81	compatible = "simple-bus";
82	#address-cells = <1>;
83	#size-cells = <1>;
84	ranges;
85
86	sysram@02020000 {
87	compatible = "mmio-sram";
88	reg = <0x02020000 0x50000>;
89	#address-cells = <1>;
90	#size-cells = <1>;
91	ranges = <0 0x02020000 0x50000>;
92
93	smp-sysram@0 {
94	compatible = "samsung,exynos4210-sysram";
95	reg = <0x0 0x1000>;
96	};
97
98	smp-sysram@4f000 {
99	compatible = "samsung,exynos4210-sysram-ns";
100	reg = <0x4f000 0x1000>;
101	};
102	};
103
104	pinctrl_2: pinctrl@03860000 {
105	compatible = "samsung,exynos4415-pinctrl";
106	reg = <0x03860000 0x1000>;
107	interrupts = <0 242 0>;
108	};
109
110	chipid@10000000 {
111	compatible = "samsung,exynos4210-chipid";
112	reg = <0x10000000 0x100>;
113	};
114
115	sysreg_system_controller: syscon@10010000 {
116	compatible = "samsung,exynos4-sysreg", "syscon";
117	reg = <0x10010000 0x400>;
118	};
119
120	pmu_system_controller: system-controller@10020000 {
121	compatible = "samsung,exynos4415-pmu", "syscon";
122	reg = <0x10020000 0x4000>;
123	};
124
125	mipi_phy: video-phy@10020710 {
126	compatible = "samsung,s5pv210-mipi-video-phy";
127	reg = <0x10020710 8>;
128	#phy-cells = <1>;
129	};
130
131	pd_cam: cam-power-domain@10024000 {
132	compatible = "samsung,exynos4210-pd";
133	reg = <0x10024000 0x20>;
0da65870	134	#power-domain-cells = <0>;
9246e7ff CC	135	};
	136
	137	pd_tv: tv-power-domain@10024020 {
	138	compatible = "samsung,exynos4210-pd";
	139	reg = <0x10024020 0x20>;
0da65870	140	#power-domain-cells = <0>;
9246e7ff CC	141	};
	142
	143	pd_mfc: mfc-power-domain@10024040 {
	144	compatible = "samsung,exynos4210-pd";
	145	reg = <0x10024040 0x20>;
0da65870	146	#power-domain-cells = <0>;
9246e7ff CC	147	};
	148
	149	pd_g3d: g3d-power-domain@10024060 {
	150	compatible = "samsung,exynos4210-pd";
	151	reg = <0x10024060 0x20>;
0da65870	152	#power-domain-cells = <0>;
9246e7ff CC	153	};
	154
	155	pd_lcd0: lcd0-power-domain@10024080 {
	156	compatible = "samsung,exynos4210-pd";
	157	reg = <0x10024080 0x20>;
0da65870	158	#power-domain-cells = <0>;
9246e7ff CC	159	};
	160
	161	pd_isp0: isp0-power-domain@100240A0 {
	162	compatible = "samsung,exynos4210-pd";
	163	reg = <0x100240A0 0x20>;
0da65870	164	#power-domain-cells = <0>;
9246e7ff CC	165	};
	166
	167	pd_isp1: isp1-power-domain@100240E0 {
	168	compatible = "samsung,exynos4210-pd";
	169	reg = <0x100240E0 0x20>;
0da65870	170	#power-domain-cells = <0>;
9246e7ff CC	171	};
	172
	173	cmu: clock-controller@10030000 {
	174	compatible = "samsung,exynos4415-cmu";
	175	reg = <0x10030000 0x18000>;
	176	#clock-cells = <1>;
	177	};
	178
	179	rtc: rtc@10070000 {
	180	compatible = "samsung,exynos3250-rtc";
	181	reg = <0x10070000 0x100>;
	182	interrupts = <0 73 0>, <0 74 0>;
	183	status = "disabled";
	184	};
	185
	186	mct@10050000 {
	187	compatible = "samsung,exynos4210-mct";
	188	reg = <0x10050000 0x800>;
	189	interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
	190	<0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
	191	clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
	192	clock-names = "fin_pll", "mct";
	193	};
	194
	195	gic: interrupt-controller@10481000 {
	196	compatible = "arm,cortex-a9-gic";
	197	#interrupt-cells = <3>;
	198	interrupt-controller;
	199	reg = <0x10481000 0x1000>,
	200	<0x10482000 0x1000>,
	201	<0x10484000 0x2000>,
	202	<0x10486000 0x2000>;
	203	interrupts = <1 9 0xf04>;
	204	};
	205
	206	l2c: l2-cache-controller@10502000 {
	207	compatible = "arm,pl310-cache";
	208	reg = <0x10502000 0x1000>;
	209	cache-unified;
	210	cache-level = <2>;
	211	arm,tag-latency = <2 2 1>;
	212	arm,data-latency = <3 2 1>;
	213	arm,double-linefill = <1>;
	214	arm,double-linefill-incr = <0>;
	215	arm,double-linefill-wrap = <1>;
	216	arm,prefetch-drop = <1>;
	217	arm,prefetch-offset = <7>;
	218	};
	219
	220	cmu_dmc: clock-controller@105C0000 {
	221	compatible = "samsung,exynos4415-cmu-dmc";
	222	reg = <0x105C0000 0x3000>;
	223	#clock-cells = <1>;
	224	};
	225
	226	pinctrl_1: pinctrl@11000000 {
	227	compatible = "samsung,exynos4415-pinctrl";
	228	reg = <0x11000000 0x1000>;
	229	interrupts = <0 225 0>;
	230
	231	wakeup-interrupt-controller {
	232	compatible = "samsung,exynos4210-wakeup-eint";
	233	interrupt-parent = <&gic>;
	234	interrupts = <0 48 0>;
235	};
236	};
237
238	pinctrl_0: pinctrl@11400000 {
239	compatible = "samsung,exynos4415-pinctrl";
240	reg = <0x11400000 0x1000>;
241	interrupts = <0 240 0>;
242	};
243
244	hsotg: hsotg@12480000 {
245	compatible = "samsung,s3c6400-hsotg";
246	reg = <0x12480000 0x20000>;
247	interrupts = <0 141 0>;
248	clocks = <&cmu CLK_USBDEVICE>;
249	clock-names = "otg";
250	phys = <&exynos_usbphy 0>;
251	phy-names = "usb2-phy";
252	status = "disabled";
253	};
254
255	mshc_0: mshc@12510000 {
256	compatible = "samsung,exynos5250-dw-mshc";
257	reg = <0x12510000 0x1000>;
258	interrupts = <0 142 0>;
259	clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
260	clock-names = "biu", "ciu";
261	fifo-depth = <0x80>;
262	#address-cells = <1>;
263	#size-cells = <0>;
264	status = "disabled";
265	};
266
267	mshc_1: mshc@12520000 {
268	compatible = "samsung,exynos5250-dw-mshc";
269	reg = <0x12520000 0x1000>;
270	interrupts = <0 143 0>;
271	clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
272	clock-names = "biu", "ciu";
273	fifo-depth = <0x80>;
274	#address-cells = <1>;
275	#size-cells = <0>;
276	status = "disabled";
277	};
278
279	mshc_2: mshc@12530000 {
280	compatible = "samsung,exynos5250-dw-mshc";
281	reg = <0x12530000 0x1000>;
282	interrupts = <0 144 0>;
283	clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
284	clock-names = "biu", "ciu";
285	fifo-depth = <0x80>;
286	#address-cells = <1>;
287	#size-cells = <0>;
288	status = "disabled";
289	};
290
291	ehci: ehci@12580000 {
292	compatible = "samsung,exynos4210-ehci";
293	reg = <0x12580000 0x100>;
294	interrupts = <0 140 0>;
295	clocks = <&cmu CLK_USBHOST>;
296	clock-names = "usbhost";
297	status = "disabled";
298	#address-cells = <1>;
299	#size-cells = <0>;
300	port@0 {
301	reg = <0>;
302	phys = <&exynos_usbphy 1>;
303	status = "disabled";
304	};
305	port@1 {
306	reg = <1>;
307	phys = <&exynos_usbphy 2>;
308	status = "disabled";
309	};
310	port@2 {
311	reg = <2>;
312	phys = <&exynos_usbphy 3>;
313	status = "disabled";
314	};
315	};
316
317	ohci: ohci@12590000 {
318	compatible = "samsung,exynos4210-ohci";
319	reg = <0x12590000 0x100>;
320	interrupts = <0 140 0>;
321	clocks = <&cmu CLK_USBHOST>;
322	clock-names = "usbhost";
323	status = "disabled";
324	#address-cells = <1>;
325	#size-cells = <0>;
326	port@0 {
327	reg = <0>;
328	phys = <&exynos_usbphy 1>;
329	status = "disabled";
330	};
331	};
332
333	exynos_usbphy: exynos-usbphy@125B0000 {
334	compatible = "samsung,exynos4x12-usb2-phy";
335	reg = <0x125B0000 0x100>;
336	samsung,pmureg-phandle = <&pmu_system_controller>;
337	samsung,sysreg-phandle = <&sysreg_system_controller>;
338	clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>;
339	clock-names = "phy", "ref";
340	#phy-cells = <1>;
341	status = "disabled";
342	};
343
344	amba {
345	compatible = "arm,amba-bus";
346	#address-cells = <1>;
347	#size-cells = <1>;
348	interrupt-parent = <&gic>;
349	ranges;
350
351	pdma0: pdma@12680000 {
352	compatible = "arm,pl330", "arm,primecell";
353	reg = <0x12680000 0x1000>;
354	interrupts = <0 138 0>;
355	clocks = <&cmu CLK_PDMA0>;
356	clock-names = "apb_pclk";
357	#dma-cells = <1>;
358	#dma-channels = <8>;
359	#dma-requests = <32>;
360	};
361
362	pdma1: pdma@12690000 {
363	compatible = "arm,pl330", "arm,primecell";
364	reg = <0x12690000 0x1000>;
365	interrupts = <0 139 0>;
366	clocks = <&cmu CLK_PDMA1>;
367	clock-names = "apb_pclk";
368	#dma-cells = <1>;
369	#dma-channels = <8>;
370	#dma-requests = <32>;
371	};
372	};
373
374	adc: adc@126C0000 {
375	compatible = "samsung,exynos3250-adc",
376	"samsung,exynos-adc-v2";
377	reg = <0x126C0000 0x100>, <0x10020718 0x4>;
378	interrupts = <0 137 0>;
379	clock-names = "adc", "sclk";
380	clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
381	#io-channel-cells = <1>;
382	io-channel-ranges;
383	status = "disabled";
384	};
385
386	serial_0: serial@13800000 {
387	compatible = "samsung,exynos4210-uart";
388	reg = <0x13800000 0x100>;
389	interrupts = <0 109 0>;
390	clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
391	clock-names = "uart", "clk_uart_baud0";
392	status = "disabled";
393	};
394
395	serial_1: serial@13810000 {
396	compatible = "samsung,exynos4210-uart";
397	reg = <0x13810000 0x100>;
398	interrupts = <0 110 0>;
399	clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
400	clock-names = "uart", "clk_uart_baud0";
401	status = "disabled";
402	};
403
404	serial_2: serial@13820000 {
405	compatible = "samsung,exynos4210-uart";
406	reg = <0x13820000 0x100>;
407	interrupts = <0 111 0>;
408	clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
409	clock-names = "uart", "clk_uart_baud0";
410	status = "disabled";
411	};
412
413	serial_3: serial@13830000 {
414	compatible = "samsung,exynos4210-uart";
415	reg = <0x13830000 0x100>;
416	interrupts = <0 112 0>;
417	clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
418	clock-names = "uart", "clk_uart_baud0";
419	status = "disabled";
420	};
421
422	i2c_0: i2c@13860000 {
423	#address-cells = <1>;
424	#size-cells = <0>;
425	compatible = "samsung,s3c2440-i2c";
426	reg = <0x13860000 0x100>;
427	interrupts = <0 113 0>;
428	clocks = <&cmu CLK_I2C0>;
429	clock-names = "i2c";
430	pinctrl-names = "default";
431	pinctrl-0 = <&i2c0_bus>;
432	status = "disabled";
433	};
434
435	i2c_1: i2c@13870000 {
436	#address-cells = <1>;
437	#size-cells = <0>;
438	compatible = "samsung,s3c2440-i2c";
439	reg = <0x13870000 0x100>;
440	interrupts = <0 114 0>;
441	clocks = <&cmu CLK_I2C1>;
442	clock-names = "i2c";
443	pinctrl-names = "default";
444	pinctrl-0 = <&i2c1_bus>;
445	status = "disabled";
446	};
447
448	i2c_2: i2c@13880000 {
449	#address-cells = <1>;
450	#size-cells = <0>;
451	compatible = "samsung,s3c2440-i2c";
452	reg = <0x13880000 0x100>;
453	interrupts = <0 115 0>;
454	clocks = <&cmu CLK_I2C2>;
455	clock-names = "i2c";
456	pinctrl-names = "default";
457	pinctrl-0 = <&i2c2_bus>;
458	status = "disabled";
459	};
460
461	i2c_3: i2c@13890000 {
462	#address-cells = <1>;
463	#size-cells = <0>;
464	compatible = "samsung,s3c2440-i2c";
465	reg = <0x13890000 0x100>;
466	interrupts = <0 116 0>;
467	clocks = <&cmu CLK_I2C3>;
468	clock-names = "i2c";
469	pinctrl-names = "default";
470	pinctrl-0 = <&i2c3_bus>;
471	status = "disabled";
472	};
473
474	i2c_4: i2c@138A0000 {
475	#address-cells = <1>;
476	#size-cells = <0>;
477	compatible = "samsung,s3c2440-i2c";
478	reg = <0x138A0000 0x100>;
479	interrupts = <0 117 0>;
480	clocks = <&cmu CLK_I2C4>;
481	clock-names = "i2c";
482	pinctrl-names = "default";
483	pinctrl-0 = <&i2c4_bus>;
484	status = "disabled";
485	};
486
487	i2c_5: i2c@138B0000 {
488	#address-cells = <1>;
489	#size-cells = <0>;
490	compatible = "samsung,s3c2440-i2c";
491	reg = <0x138B0000 0x100>;
492	interrupts = <0 118 0>;
493	clocks = <&cmu CLK_I2C5>;
494	clock-names = "i2c";
495	pinctrl-names = "default";
496	pinctrl-0 = <&i2c5_bus>;
497	status = "disabled";
498	};
499
500	i2c_6: i2c@138C0000 {
501	#address-cells = <1>;
502	#size-cells = <0>;
503	compatible = "samsung,s3c2440-i2c";
504	reg = <0x138C0000 0x100>;
505	interrupts = <0 119 0>;
506	clocks = <&cmu CLK_I2C6>;
507	clock-names = "i2c";
508	pinctrl-names = "default";
509	pinctrl-0 = <&i2c6_bus>;
510	status = "disabled";
511	};
512
513	i2c_7: i2c@138D0000 {
514	#address-cells = <1>;
515	#size-cells = <0>;
516	compatible = "samsung,s3c2440-i2c";
517	reg = <0x138D0000 0x100>;
518	interrupts = <0 120 0>;
519	clocks = <&cmu CLK_I2C7>;
520	clock-names = "i2c";
521	pinctrl-names = "default";
522	pinctrl-0 = <&i2c7_bus>;
523	status = "disabled";
524	};
525
526	spi_0: spi@13920000 {
527	compatible = "samsung,exynos4210-spi";
528	reg = <0x13920000 0x100>;
529	interrupts = <0 121 0>;
530	dmas = <&pdma0 7>, <&pdma0 6>;
531	dma-names = "tx", "rx";
532	#address-cells = <1>;
533	#size-cells = <0>;
534	clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
535	clock-names = "spi", "spi_busclk0";
536	samsung,spi-src-clk = <0>;
537	pinctrl-names = "default";
538	pinctrl-0 = <&spi0_bus>;
539	status = "disabled";
540	};
541
542	spi_1: spi@13930000 {
543	compatible = "samsung,exynos4210-spi";
544	reg = <0x13930000 0x100>;
545	interrupts = <0 122 0>;
546	dmas = <&pdma1 7>, <&pdma1 6>;
547	dma-names = "tx", "rx";
548	#address-cells = <1>;
549	#size-cells = <0>;
550	clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
551	clock-names = "spi", "spi_busclk0";
552	samsung,spi-src-clk = <0>;
553	pinctrl-names = "default";
554	pinctrl-0 = <&spi1_bus>;
555	status = "disabled";
556	};
557
558	spi_2: spi@13940000 {
559	compatible = "samsung,exynos4210-spi";
560	reg = <0x13940000 0x100>;
561	interrupts = <0 123 0>;
562	dmas = <&pdma0 9>, <&pdma0 8>;
563	dma-names = "tx", "rx";
564	#address-cells = <1>;
565	#size-cells = <0>;
566	clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>;
567	clock-names = "spi", "spi_busclk0";
568	samsung,spi-src-clk = <0>;
569	pinctrl-names = "default";
570	pinctrl-0 = <&spi2_bus>;
571	status = "disabled";
572	};
573
574	clock_audss: clock-controller@03810000 {
575	compatible = "samsung,exynos4210-audss-clock";
576	reg = <0x03810000 0x0C>;
577	#clock-cells = <1>;
578	};
579
580	i2s0: i2s@3830000 {
581	compatible = "samsung,s5pv210-i2s";
582	reg = <0x03830000 0x100>;
583	interrupts = <0 124 0>;
584	clocks = <&clock_audss EXYNOS_I2S_BUS>,
585	<&clock_audss EXYNOS_SCLK_I2S>;
586	clock-names = "iis", "i2s_opclk0";
587	dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>;
588	dma-names = "tx", "rx", "tx-sec";
589	pinctrl-names = "default";
590	pinctrl-0 = <&i2s0_bus>;
591	samsung,idma-addr = <0x03000000>;
592	status = "disabled";
593	};
594
595	pwm: pwm@139D0000 {
596	compatible = "samsung,exynos4210-pwm";
597	reg = <0x139D0000 0x1000>;
598	interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
599	<0 107 0>, <0 108 0>;
600	#pwm-cells = <3>;
601	status = "disabled";
602	};
603
604	pmu {
605	compatible = "arm,cortex-a9-pmu";
606	interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
607	};
608	};
609	};
610
611	#include "exynos4415-pinctrl.dtsi"