[deliverable/linux.git] / arch / arm / boot / dts / exynos4x12.dtsi

/*
 * Samsung's Exynos4x12 SoCs device tree source
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
 * nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include "exynos4.dtsi"
#include "exynos4x12-pinctrl.dtsi"

/ {
	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		pinctrl2 = &pinctrl_2;
		pinctrl3 = &pinctrl_3;
		fimc-lite0 = &fimc_lite_0;
		fimc-lite1 = &fimc_lite_1;
		mshc0 = &mshc_0;
	};

	sysram@02020000 {
		compatible = "mmio-sram";
		reg = <0x02020000 0x40000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x02020000 0x40000>;

		smp-sysram@0 {
			compatible = "samsung,exynos4210-sysram";
			reg = <0x0 0x1000>;
		};

		smp-sysram@2f000 {
			compatible = "samsung,exynos4210-sysram-ns";
			reg = <0x2f000 0x1000>;
		};
	};

	pd_isp: isp-power-domain@10023CA0 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10023CA0 0x20>;
		#power-domain-cells = <0>;
	};

	l2c: l2-cache-controller@10502000 {
		compatible = "arm,pl310-cache";
		reg = <0x10502000 0x1000>;
		cache-unified;
		cache-level = <2>;
		arm,tag-latency = <2 2 1>;
		arm,data-latency = <3 2 1>;
		arm,double-linefill = <1>;
		arm,double-linefill-incr = <0>;
		arm,double-linefill-wrap = <1>;
		arm,prefetch-drop = <1>;
		arm,prefetch-offset = <7>;
	};

	clock: clock-controller@10030000 {
		compatible = "samsung,exynos4412-clock";
		reg = <0x10030000 0x20000>;
		#clock-cells = <1>;
	};

	mct@10050000 {
		compatible = "samsung,exynos4412-mct";
		reg = <0x10050000 0x800>;
		interrupt-parent = <&mct_map>;
		interrupts = <0>, <1>, <2>, <3>, <4>;
		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
		clock-names = "fin_pll", "mct";

		mct_map: mct-map {
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = <0 &gic 0 57 0>,
					<1 &combiner 12 5>,
					<2 &combiner 12 6>,
					<3 &combiner 12 7>,
					<4 &gic 1 12 0>;
		};
	};

	combiner: interrupt-controller@10440000 {
		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
			     <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
	};

	pinctrl_0: pinctrl@11400000 {
		compatible = "samsung,exynos4x12-pinctrl";
		reg = <0x11400000 0x1000>;
		interrupts = <0 47 0>;
	};

	pinctrl_1: pinctrl@11000000 {
		compatible = "samsung,exynos4x12-pinctrl";
		reg = <0x11000000 0x1000>;
		interrupts = <0 46 0>;

		wakup_eint: wakeup-interrupt-controller {
			compatible = "samsung,exynos4210-wakeup-eint";
			interrupt-parent = <&gic>;
			interrupts = <0 32 0>;
		};
	};

	adc: adc@126C0000 {
		compatible = "samsung,exynos-adc-v1";
		reg = <0x126C0000 0x100>;
		interrupt-parent = <&combiner>;
		interrupts = <10 3>;
		clocks = <&clock CLK_TSADC>;
		clock-names = "adc";
		#io-channel-cells = <1>;
		io-channel-ranges;
		samsung,syscon-phandle = <&pmu_system_controller>;
		status = "disabled";
	};

	pinctrl_2: pinctrl@03860000 {
		compatible = "samsung,exynos4x12-pinctrl";
		reg = <0x03860000 0x1000>;
		interrupt-parent = <&combiner>;
		interrupts = <10 0>;
	};

	pinctrl_3: pinctrl@106E0000 {
		compatible = "samsung,exynos4x12-pinctrl";
		reg = <0x106E0000 0x1000>;
		interrupts = <0 72 0>;
	};

	pmu_system_controller: system-controller@10020000 {
		compatible = "samsung,exynos4212-pmu", "syscon";
		clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
				"clkout4", "clkout8", "clkout9";
		clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
			<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
			<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
			<&clock CLK_XUSBXTI>;
		#clock-cells = <1>;
	};

	g2d@10800000 {
		compatible = "samsung,exynos4212-g2d";
		reg = <0x10800000 0x1000>;
		interrupts = <0 89 0>;
		clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
		clock-names = "sclk_fimg2d", "fimg2d";
		status = "disabled";
	};

	camera {
		clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
			 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
		clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";

		fimc_0: fimc@11800000 {
			compatible = "samsung,exynos4212-fimc";
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,isp-wb;
			samsung,cam-if;
		};

		fimc_1: fimc@11810000 {
			compatible = "samsung,exynos4212-fimc";
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,isp-wb;
			samsung,cam-if;
		};

		fimc_2: fimc@11820000 {
			compatible = "samsung,exynos4212-fimc";
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,isp-wb;
			samsung,lcd-wb;
			samsung,cam-if;
		};

		fimc_3: fimc@11830000 {
			compatible = "samsung,exynos4212-fimc";
			samsung,pix-limits = <1920 8192 1366 1920>;
			samsung,rotators = <0>;
			samsung,mainscaler-ext;
			samsung,isp-wb;
			samsung,lcd-wb;
		};

		fimc_lite_0: fimc-lite@12390000 {
			compatible = "samsung,exynos4212-fimc-lite";
			reg = <0x12390000 0x1000>;
			interrupts = <0 105 0>;
			power-domains = <&pd_isp>;
			clocks = <&clock CLK_FIMC_LITE0>;
			clock-names = "flite";
			status = "disabled";
		};

		fimc_lite_1: fimc-lite@123A0000 {
			compatible = "samsung,exynos4212-fimc-lite";
			reg = <0x123A0000 0x1000>;
			interrupts = <0 106 0>;
			power-domains = <&pd_isp>;
			clocks = <&clock CLK_FIMC_LITE1>;
			clock-names = "flite";
			status = "disabled";
		};

		fimc_is: fimc-is@12000000 {
			compatible = "samsung,exynos4212-fimc-is", "simple-bus";
			reg = <0x12000000 0x260000>;
			interrupts = <0 90 0>, <0 95 0>;
			power-domains = <&pd_isp>;
			clocks = <&clock CLK_FIMC_LITE0>,
				 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
				 <&clock CLK_PPMUISPMX>,
				 <&clock CLK_MOUT_MPLL_USER_T>,
				 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
				 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
				 <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
				 <&clock CLK_DIV_MCUISP0>,
				 <&clock CLK_DIV_MCUISP1>,
				 <&clock CLK_UART_ISP_SCLK>,
				 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
				 <&clock CLK_ACLK400_MCUISP>,
				 <&clock CLK_DIV_ACLK400_MCUISP>;
			clock-names = "lite0", "lite1", "ppmuispx",
				      "ppmuispmx", "mpll", "isp",
				      "drc", "fd", "mcuisp",
				      "ispdiv0", "ispdiv1", "mcuispdiv0",
				      "mcuispdiv1", "uart", "aclk200",
				      "div_aclk200", "aclk400mcuisp",
				      "div_aclk400mcuisp";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			status = "disabled";

			pmu {
				reg = <0x10020000 0x3000>;
			};

			i2c1_isp: i2c-isp@12140000 {
				compatible = "samsung,exynos4212-i2c-isp";
				reg = <0x12140000 0x100>;
				clocks = <&clock CLK_I2C1_ISP>;
				clock-names = "i2c_isp";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};
	};

	mshc_0: mmc@12550000 {
		compatible = "samsung,exynos4412-dw-mshc";
		reg = <0x12550000 0x1000>;
		interrupts = <0 77 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		fifo-depth = <0x80>;
		clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
		clock-names = "biu", "ciu";
		status = "disabled";
	};

	exynos-usbphy@125B0000 {
		compatible = "samsung,exynos4x12-usb2-phy";
		samsung,sysreg-phandle = <&sys_reg>;
	};

	tmu@100C0000 {
		compatible = "samsung,exynos4412-tmu";
		interrupt-parent = <&combiner>;
		interrupts = <2 4>;
		reg = <0x100C0000 0x100>;
		clocks = <&clock 383>;
		clock-names = "tmu_apbif";
		status = "disabled";
	};
};
Commit	Line	Data
0f7238a1 TF	1	/*
	2	* Samsung's Exynos4x12 SoCs device tree source
	3	*
	4	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
	8	* based board files can include this file and provide values for board specfic
	9	* bindings.
	10	*
	11	* Note: This file does not include device nodes for all the controllers in
	12	* Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
	13	* nodes can be added to this file.
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19
3799279f PV	20	#include "exynos4.dtsi"
3799279f PV	21	#include "exynos4x12-pinctrl.dtsi"
0f7238a1 TF	22
0f7238a1 TF	23	/ {
64a57434 TF	24	aliases {
	25	pinctrl0 = &pinctrl_0;
	26	pinctrl1 = &pinctrl_1;
	27	pinctrl2 = &pinctrl_2;
	28	pinctrl3 = &pinctrl_3;
582435b3 SN	29	fimc-lite0 = &fimc_lite_0;
582435b3 SN	30	fimc-lite1 = &fimc_lite_1;
56d52bfb	31	mshc0 = &mshc_0;
64a57434 TF	32	};
64a57434 TF	33
b3205dea SK	34	sysram@02020000 {
	35	compatible = "mmio-sram";
	36	reg = <0x02020000 0x40000>;
	37	#address-cells = <1>;
	38	#size-cells = <1>;
	39	ranges = <0 0x02020000 0x40000>;
	40
	41	smp-sysram@0 {
	42	compatible = "samsung,exynos4210-sysram";
	43	reg = <0x0 0x1000>;
	44	};
	45
	46	smp-sysram@2f000 {
	47	compatible = "samsung,exynos4210-sysram-ns";
	48	reg = <0x2f000 0x1000>;
	49	};
	50	};
	51
2ab9f3c0 SN	52	pd_isp: isp-power-domain@10023CA0 {
	53	compatible = "samsung,exynos4210-pd";
	54	reg = <0x10023CA0 0x20>;
0da65870	55	#power-domain-cells = <0>;
64a57434 TF	56	};
64a57434 TF	57
56b60b8b TF	58	l2c: l2-cache-controller@10502000 {
	59	compatible = "arm,pl310-cache";
	60	reg = <0x10502000 0x1000>;
	61	cache-unified;
	62	cache-level = <2>;
	63	arm,tag-latency = <2 2 1>;
	64	arm,data-latency = <3 2 1>;
	65	arm,double-linefill = <1>;
	66	arm,double-linefill-incr = <0>;
	67	arm,double-linefill-wrap = <1>;
	68	arm,prefetch-drop = <1>;
	69	arm,prefetch-offset = <7>;
	70	};
	71
1fd9a015	72	clock: clock-controller@10030000 {
d8bafc87 TA	73	compatible = "samsung,exynos4412-clock";
	74	reg = <0x10030000 0x20000>;
	75	#clock-cells = <1>;
	76	};
	77
39e596f0 TF	78	mct@10050000 {
	79	compatible = "samsung,exynos4412-mct";
	80	reg = <0x10050000 0x800>;
	81	interrupt-parent = <&mct_map>;
84ee1c15	82	interrupts = <0>, <1>, <2>, <3>, <4>;
1c75a78a	83	clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
39e596f0 TF	84	clock-names = "fin_pll", "mct";
	85
	86	mct_map: mct-map {
84ee1c15	87	#interrupt-cells = <1>;
39e596f0 TF	88	#address-cells = <0>;
39e596f0 TF	89	#size-cells = <0>;
84ee1c15 TF	90	interrupt-map = <0 &gic 0 57 0>,
	91	<1 &combiner 12 5>,
	92	<2 &combiner 12 6>,
	93	<3 &combiner 12 7>,
	94	<4 &gic 1 12 0>;
39e596f0 TF	95	};
	96	};
	97
8bdfa203 CC	98	combiner: interrupt-controller@10440000 {
	99	interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
	100	<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
	101	<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
	102	<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
	103	<0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
	104	};
	105
64a57434	106	pinctrl_0: pinctrl@11400000 {
b533c868	107	compatible = "samsung,exynos4x12-pinctrl";
64a57434 TF	108	reg = <0x11400000 0x1000>;
	109	interrupts = <0 47 0>;
	110	};
	111
	112	pinctrl_1: pinctrl@11000000 {
b533c868	113	compatible = "samsung,exynos4x12-pinctrl";
64a57434 TF	114	reg = <0x11000000 0x1000>;
	115	interrupts = <0 46 0>;
	116
	117	wakup_eint: wakeup-interrupt-controller {
	118	compatible = "samsung,exynos4210-wakeup-eint";
	119	interrupt-parent = <&gic>;
	120	interrupts = <0 32 0>;
	121	};
	122	};
	123
c63c5743 CC	124	adc: adc@126C0000 {
c63c5743 CC	125	compatible = "samsung,exynos-adc-v1";
db9bf4d6	126	reg = <0x126C0000 0x100>;
c63c5743 CC	127	interrupt-parent = <&combiner>;
	128	interrupts = <10 3>;
	129	clocks = <&clock CLK_TSADC>;
	130	clock-names = "adc";
	131	#io-channel-cells = <1>;
	132	io-channel-ranges;
db9bf4d6	133	samsung,syscon-phandle = <&pmu_system_controller>;
c63c5743 CC	134	status = "disabled";
	135	};
	136
64a57434	137	pinctrl_2: pinctrl@03860000 {
b533c868	138	compatible = "samsung,exynos4x12-pinctrl";
64a57434 TF	139	reg = <0x03860000 0x1000>;
	140	interrupt-parent = <&combiner>;
	141	interrupts = <10 0>;
	142	};
	143
	144	pinctrl_3: pinctrl@106E0000 {
b533c868	145	compatible = "samsung,exynos4x12-pinctrl";
64a57434 TF	146	reg = <0x106E0000 0x1000>;
	147	interrupts = <0 72 0>;
	148	};
3a0d48f6	149
7b9613ac CP	150	pmu_system_controller: system-controller@10020000 {
7b9613ac CP	151	compatible = "samsung,exynos4212-pmu", "syscon";
d19bb397 TF	152	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
	153	"clkout4", "clkout8", "clkout9";
	154	clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
	155	<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
	156	<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
	157	<&clock CLK_XUSBXTI>;
	158	#clock-cells = <1>;
7b9613ac CP	159	};
7b9613ac CP	160
3a0d48f6 SK	161	g2d@10800000 {
	162	compatible = "samsung,exynos4212-g2d";
	163	reg = <0x10800000 0x1000>;
	164	interrupts = <0 89 0>;
1c75a78a	165	clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
cfc5652d	166	clock-names = "sclk_fimg2d", "fimg2d";
3a0d48f6 SK	167	status = "disabled";
3a0d48f6 SK	168	};
582435b3 SN	169
582435b3 SN	170	camera {
1c75a78a AH	171	clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
1c75a78a AH	172	<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
582435b3 SN	173	clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
	174
	175	fimc_0: fimc@11800000 {
	176	compatible = "samsung,exynos4212-fimc";
	177	samsung,pix-limits = <4224 8192 1920 4224>;
	178	samsung,mainscaler-ext;
	179	samsung,isp-wb;
	180	samsung,cam-if;
	181	};
	182
	183	fimc_1: fimc@11810000 {
	184	compatible = "samsung,exynos4212-fimc";
	185	samsung,pix-limits = <4224 8192 1920 4224>;
	186	samsung,mainscaler-ext;
	187	samsung,isp-wb;
	188	samsung,cam-if;
	189	};
	190
	191	fimc_2: fimc@11820000 {
	192	compatible = "samsung,exynos4212-fimc";
	193	samsung,pix-limits = <4224 8192 1920 4224>;
	194	samsung,mainscaler-ext;
	195	samsung,isp-wb;
	196	samsung,lcd-wb;
	197	samsung,cam-if;
	198	};
	199
	200	fimc_3: fimc@11830000 {
	201	compatible = "samsung,exynos4212-fimc";
	202	samsung,pix-limits = <1920 8192 1366 1920>;
	203	samsung,rotators = <0>;
	204	samsung,mainscaler-ext;
	205	samsung,isp-wb;
	206	samsung,lcd-wb;
	207	};
	208
	209	fimc_lite_0: fimc-lite@12390000 {
	210	compatible = "samsung,exynos4212-fimc-lite";
	211	reg = <0x12390000 0x1000>;
	212	interrupts = <0 105 0>;
0da65870	213	power-domains = <&pd_isp>;
1c75a78a	214	clocks = <&clock CLK_FIMC_LITE0>;
582435b3 SN	215	clock-names = "flite";
	216	status = "disabled";
	217	};
	218
	219	fimc_lite_1: fimc-lite@123A0000 {
	220	compatible = "samsung,exynos4212-fimc-lite";
	221	reg = <0x123A0000 0x1000>;
	222	interrupts = <0 106 0>;
0da65870	223	power-domains = <&pd_isp>;
1c75a78a	224	clocks = <&clock CLK_FIMC_LITE1>;
582435b3 SN	225	clock-names = "flite";
	226	status = "disabled";
	227	};
	228
	229	fimc_is: fimc-is@12000000 {
	230	compatible = "samsung,exynos4212-fimc-is", "simple-bus";
	231	reg = <0x12000000 0x260000>;
	232	interrupts = <0 90 0>, <0 95 0>;
0da65870	233	power-domains = <&pd_isp>;
1c75a78a AH	234	clocks = <&clock CLK_FIMC_LITE0>,
	235	<&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
	236	<&clock CLK_PPMUISPMX>,
	237	<&clock CLK_MOUT_MPLL_USER_T>,
	238	<&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
	239	<&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
	240	<&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
	241	<&clock CLK_DIV_MCUISP0>,
	242	<&clock CLK_DIV_MCUISP1>,
79f3c37c	243	<&clock CLK_UART_ISP_SCLK>,
1c75a78a AH	244	<&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
	245	<&clock CLK_ACLK400_MCUISP>,
	246	<&clock CLK_DIV_ACLK400_MCUISP>;
582435b3 SN	247	clock-names = "lite0", "lite1", "ppmuispx",
	248	"ppmuispmx", "mpll", "isp",
	249	"drc", "fd", "mcuisp",
	250	"ispdiv0", "ispdiv1", "mcuispdiv0",
	251	"mcuispdiv1", "uart", "aclk200",
	252	"div_aclk200", "aclk400mcuisp",
	253	"div_aclk400mcuisp";
	254	#address-cells = <1>;
	255	#size-cells = <1>;
	256	ranges;
	257	status = "disabled";
	258
	259	pmu {
	260	reg = <0x10020000 0x3000>;
	261	};
	262
	263	i2c1_isp: i2c-isp@12140000 {
	264	compatible = "samsung,exynos4212-i2c-isp";
	265	reg = <0x12140000 0x100>;
1c75a78a	266	clocks = <&clock CLK_I2C1_ISP>;
582435b3 SN	267	clock-names = "i2c_isp";
	268	#address-cells = <1>;
	269	#size-cells = <0>;
	270	};
	271	};
	272	};
56d52bfb TF	273
	274	mshc_0: mmc@12550000 {
	275	compatible = "samsung,exynos4412-dw-mshc";
	276	reg = <0x12550000 0x1000>;
	277	interrupts = <0 77 0>;
	278	#address-cells = <1>;
	279	#size-cells = <0>;
	280	fifo-depth = <0x80>;
1c75a78a	281	clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
56d52bfb TF	282	clock-names = "biu", "ciu";
	283	status = "disabled";
	284	};
26bbd41f CP	285
	286	exynos-usbphy@125B0000 {
	287	compatible = "samsung,exynos4x12-usb2-phy";
	288	samsung,sysreg-phandle = <&sys_reg>;
	289	};
bf61eed9 LM	290
	291	tmu@100C0000 {
	292	compatible = "samsung,exynos4412-tmu";
	293	interrupt-parent = <&combiner>;
	294	interrupts = <2 4>;
	295	reg = <0x100C0000 0x100>;
	296	clocks = <&clock 383>;
	297	clock-names = "tmu_apbif";
	298	status = "disabled";
	299	};
0f7238a1	300	};