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1 | /* |
2 | * Samsung's Exynos5 SoC series common device tree source | |
3 | * | |
4 | * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular | |
8 | * SoCs from Exynos5 series can include this file and provide values for SoCs | |
9 | * specfic bindings. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include "skeleton.dtsi" | |
17 | ||
18 | / { | |
19 | interrupt-parent = <&gic>; | |
20 | ||
21 | chipid@10000000 { | |
22 | compatible = "samsung,exynos4210-chipid"; | |
23 | reg = <0x10000000 0x100>; | |
24 | }; | |
25 | ||
26 | combiner:interrupt-controller@10440000 { | |
27 | compatible = "samsung,exynos4210-combiner"; | |
28 | #interrupt-cells = <2>; | |
29 | interrupt-controller; | |
30 | samsung,combiner-nr = <32>; | |
31 | reg = <0x10440000 0x1000>; | |
32 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, | |
33 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, | |
34 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, | |
35 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, | |
36 | <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, | |
37 | <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, | |
38 | <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, | |
39 | <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; | |
40 | }; | |
41 | ||
42 | gic:interrupt-controller@10481000 { | |
43 | compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; | |
44 | #interrupt-cells = <3>; | |
45 | interrupt-controller; | |
46 | reg = <0x10481000 0x1000>, | |
47 | <0x10482000 0x1000>, | |
48 | <0x10484000 0x2000>, | |
49 | <0x10486000 0x2000>; | |
50 | interrupts = <1 9 0xf04>; | |
51 | }; | |
52 | ||
53 | dwmmc_0: dwmmc0@12200000 { | |
54 | compatible = "samsung,exynos5250-dw-mshc"; | |
55 | interrupts = <0 75 0>; | |
56 | #address-cells = <1>; | |
57 | #size-cells = <0>; | |
58 | }; | |
59 | ||
60 | dwmmc_1: dwmmc1@12210000 { | |
61 | compatible = "samsung,exynos5250-dw-mshc"; | |
62 | interrupts = <0 76 0>; | |
63 | #address-cells = <1>; | |
64 | #size-cells = <0>; | |
65 | }; | |
66 | ||
67 | dwmmc_2: dwmmc2@12220000 { | |
68 | compatible = "samsung,exynos5250-dw-mshc"; | |
69 | interrupts = <0 77 0>; | |
70 | #address-cells = <1>; | |
71 | #size-cells = <0>; | |
72 | }; | |
73 | ||
74 | serial@12C00000 { | |
75 | compatible = "samsung,exynos4210-uart"; | |
76 | reg = <0x12C00000 0x100>; | |
77 | interrupts = <0 51 0>; | |
78 | }; | |
79 | ||
80 | serial@12C10000 { | |
81 | compatible = "samsung,exynos4210-uart"; | |
82 | reg = <0x12C10000 0x100>; | |
83 | interrupts = <0 52 0>; | |
84 | }; | |
85 | ||
86 | serial@12C20000 { | |
87 | compatible = "samsung,exynos4210-uart"; | |
88 | reg = <0x12C20000 0x100>; | |
89 | interrupts = <0 53 0>; | |
90 | }; | |
91 | ||
92 | serial@12C30000 { | |
93 | compatible = "samsung,exynos4210-uart"; | |
94 | reg = <0x12C30000 0x100>; | |
95 | interrupts = <0 54 0>; | |
96 | }; | |
97 | ||
98 | rtc { | |
99 | compatible = "samsung,s3c6410-rtc"; | |
100 | reg = <0x101E0000 0x100>; | |
101 | interrupts = <0 43 0>, <0 44 0>; | |
102 | status = "disabled"; | |
103 | }; | |
104 | ||
105 | watchdog { | |
106 | compatible = "samsung,s3c2410-wdt"; | |
107 | reg = <0x101D0000 0x100>; | |
108 | interrupts = <0 42 0>; | |
109 | status = "disabled"; | |
110 | }; | |
111 | }; |