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b074abb7 KK |
1 | /* |
2 | * SAMSUNG EXYNOS5250 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. | |
8 | * EXYNOS5250 based board files can include this file and provide | |
9 | * values for board specfic bindings. | |
10 | * | |
11 | * Note: This file does not include device nodes for all the controllers in | |
12 | * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, | |
13 | * additional nodes can be added to this file. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
20 | /include/ "skeleton.dtsi" | |
f8bfe2b0 | 21 | /include/ "exynos5250-pinctrl.dtsi" |
b074abb7 KK |
22 | |
23 | / { | |
24 | compatible = "samsung,exynos5250"; | |
25 | interrupt-parent = <&gic>; | |
26 | ||
79989ba3 TA |
27 | aliases { |
28 | spi0 = &spi_0; | |
29 | spi1 = &spi_1; | |
30 | spi2 = &spi_2; | |
1128658a SAB |
31 | gsc0 = &gsc_0; |
32 | gsc1 = &gsc_1; | |
33 | gsc2 = &gsc_2; | |
34 | gsc3 = &gsc_3; | |
de0f42be DA |
35 | mshc0 = &dwmmc_0; |
36 | mshc1 = &dwmmc_1; | |
37 | mshc2 = &dwmmc_2; | |
38 | mshc3 = &dwmmc_3; | |
b9fa3e7b AK |
39 | i2c0 = &i2c_0; |
40 | i2c1 = &i2c_1; | |
41 | i2c2 = &i2c_2; | |
42 | i2c3 = &i2c_3; | |
43 | i2c4 = &i2c_4; | |
44 | i2c5 = &i2c_5; | |
45 | i2c6 = &i2c_6; | |
46 | i2c7 = &i2c_7; | |
47 | i2c8 = &i2c_8; | |
f8bfe2b0 TA |
48 | pinctrl0 = &pinctrl_0; |
49 | pinctrl1 = &pinctrl_1; | |
50 | pinctrl2 = &pinctrl_2; | |
51 | pinctrl3 = &pinctrl_3; | |
79989ba3 TA |
52 | }; |
53 | ||
096ee6ad TA |
54 | chipid@10000000 { |
55 | compatible = "samsung,exynos4210-chipid"; | |
56 | reg = <0x10000000 0x100>; | |
79989ba3 TA |
57 | }; |
58 | ||
6f9e95e6 PK |
59 | pd_gsc: gsc-power-domain@0x10044000 { |
60 | compatible = "samsung,exynos4210-pd"; | |
61 | reg = <0x10044000 0x20>; | |
62 | }; | |
63 | ||
64 | pd_mfc: mfc-power-domain@0x10044040 { | |
65 | compatible = "samsung,exynos4210-pd"; | |
66 | reg = <0x10044040 0x20>; | |
67 | }; | |
68 | ||
d8bafc87 TA |
69 | clock: clock-controller@0x10010000 { |
70 | compatible = "samsung,exynos5250-clock"; | |
71 | reg = <0x10010000 0x30000>; | |
72 | #clock-cells = <1>; | |
73 | }; | |
74 | ||
009f7c9f | 75 | gic:interrupt-controller@10481000 { |
849ff89b | 76 | compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; |
b074abb7 KK |
77 | #interrupt-cells = <3>; |
78 | interrupt-controller; | |
849ff89b AG |
79 | reg = <0x10481000 0x1000>, |
80 | <0x10482000 0x1000>, | |
81 | <0x10484000 0x2000>, | |
82 | <0x10486000 0x2000>; | |
83 | interrupts = <1 9 0xf04>; | |
b074abb7 KK |
84 | }; |
85 | ||
2b7da988 AG |
86 | timer { |
87 | compatible = "arm,armv7-timer"; | |
88 | interrupts = <1 13 0xf08>, | |
89 | <1 14 0xf08>, | |
90 | <1 11 0xf08>, | |
91 | <1 10 0xf08>; | |
b074abb7 KK |
92 | }; |
93 | ||
fe84cdf6 TA |
94 | combiner:interrupt-controller@10440000 { |
95 | compatible = "samsung,exynos4210-combiner"; | |
96 | #interrupt-cells = <2>; | |
97 | interrupt-controller; | |
98 | samsung,combiner-nr = <32>; | |
99 | reg = <0x10440000 0x1000>; | |
100 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, | |
101 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, | |
102 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, | |
103 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, | |
104 | <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, | |
105 | <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, | |
106 | <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, | |
107 | <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; | |
108 | }; | |
109 | ||
bbd9700a TA |
110 | mct@101C0000 { |
111 | compatible = "samsung,exynos4210-mct"; | |
112 | reg = <0x101C0000 0x800>; | |
113 | interrupt-controller; | |
114 | #interrups-cells = <2>; | |
115 | interrupt-parent = <&mct_map>; | |
116 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, | |
117 | <4 0>, <5 0>; | |
2de6847c TA |
118 | clocks = <&clock 1>, <&clock 335>; |
119 | clock-names = "fin_pll", "mct"; | |
bbd9700a TA |
120 | |
121 | mct_map: mct-map { | |
122 | #interrupt-cells = <2>; | |
123 | #address-cells = <0>; | |
124 | #size-cells = <0>; | |
125 | interrupt-map = <0x0 0 &combiner 23 3>, | |
126 | <0x1 0 &combiner 23 4>, | |
127 | <0x2 0 &combiner 25 2>, | |
128 | <0x3 0 &combiner 25 3>, | |
129 | <0x4 0 &gic 0 120 0>, | |
130 | <0x5 0 &gic 0 121 0>; | |
131 | }; | |
132 | }; | |
133 | ||
4f801e59 CP |
134 | pmu { |
135 | compatible = "arm,cortex-a15-pmu"; | |
136 | interrupt-parent = <&combiner>; | |
137 | interrupts = <1 2>, <22 4>; | |
138 | }; | |
139 | ||
f8bfe2b0 TA |
140 | pinctrl_0: pinctrl@11400000 { |
141 | compatible = "samsung,exynos5250-pinctrl"; | |
142 | reg = <0x11400000 0x1000>; | |
143 | interrupts = <0 46 0>; | |
144 | ||
145 | wakup_eint: wakeup-interrupt-controller { | |
146 | compatible = "samsung,exynos4210-wakeup-eint"; | |
147 | interrupt-parent = <&gic>; | |
148 | interrupts = <0 32 0>; | |
149 | }; | |
150 | }; | |
151 | ||
152 | pinctrl_1: pinctrl@13400000 { | |
153 | compatible = "samsung,exynos5250-pinctrl"; | |
154 | reg = <0x13400000 0x1000>; | |
155 | interrupts = <0 45 0>; | |
156 | }; | |
157 | ||
158 | pinctrl_2: pinctrl@10d10000 { | |
159 | compatible = "samsung,exynos5250-pinctrl"; | |
160 | reg = <0x10d10000 0x1000>; | |
161 | interrupts = <0 50 0>; | |
162 | }; | |
163 | ||
164 | pinctrl_3: pinctrl@03680000 { | |
165 | compatible = "samsung,exynos5250-pinctrl"; | |
166 | reg = <0x0368000 0x1000>; | |
167 | interrupts = <0 47 0>; | |
168 | }; | |
169 | ||
b074abb7 KK |
170 | watchdog { |
171 | compatible = "samsung,s3c2410-wdt"; | |
172 | reg = <0x101D0000 0x100>; | |
173 | interrupts = <0 42 0>; | |
2de6847c TA |
174 | clocks = <&clock 336>; |
175 | clock-names = "watchdog"; | |
b074abb7 KK |
176 | }; |
177 | ||
2eae613b AK |
178 | codec@11000000 { |
179 | compatible = "samsung,mfc-v6"; | |
180 | reg = <0x11000000 0x10000>; | |
181 | interrupts = <0 96 0>; | |
6f9e95e6 | 182 | samsung,power-domain = <&pd_mfc>; |
2eae613b AK |
183 | }; |
184 | ||
b074abb7 KK |
185 | rtc { |
186 | compatible = "samsung,s3c6410-rtc"; | |
187 | reg = <0x101E0000 0x100>; | |
188 | interrupts = <0 43 0>, <0 44 0>; | |
2de6847c TA |
189 | clocks = <&clock 337>; |
190 | clock-names = "rtc"; | |
522ccdb6 | 191 | status = "disabled"; |
b074abb7 KK |
192 | }; |
193 | ||
ef405e04 ADK |
194 | tmu@10060000 { |
195 | compatible = "samsung,exynos5250-tmu"; | |
196 | reg = <0x10060000 0x100>; | |
197 | interrupts = <0 65 0>; | |
2de6847c TA |
198 | clocks = <&clock 338>; |
199 | clock-names = "tmu_apbif"; | |
ef405e04 ADK |
200 | }; |
201 | ||
b074abb7 KK |
202 | serial@12C00000 { |
203 | compatible = "samsung,exynos4210-uart"; | |
204 | reg = <0x12C00000 0x100>; | |
205 | interrupts = <0 51 0>; | |
2de6847c TA |
206 | clocks = <&clock 289>, <&clock 146>; |
207 | clock-names = "uart", "clk_uart_baud0"; | |
b074abb7 KK |
208 | }; |
209 | ||
210 | serial@12C10000 { | |
211 | compatible = "samsung,exynos4210-uart"; | |
212 | reg = <0x12C10000 0x100>; | |
213 | interrupts = <0 52 0>; | |
2de6847c TA |
214 | clocks = <&clock 290>, <&clock 147>; |
215 | clock-names = "uart", "clk_uart_baud0"; | |
b074abb7 KK |
216 | }; |
217 | ||
218 | serial@12C20000 { | |
219 | compatible = "samsung,exynos4210-uart"; | |
220 | reg = <0x12C20000 0x100>; | |
221 | interrupts = <0 53 0>; | |
2de6847c TA |
222 | clocks = <&clock 291>, <&clock 148>; |
223 | clock-names = "uart", "clk_uart_baud0"; | |
b074abb7 KK |
224 | }; |
225 | ||
226 | serial@12C30000 { | |
227 | compatible = "samsung,exynos4210-uart"; | |
228 | reg = <0x12C30000 0x100>; | |
229 | interrupts = <0 54 0>; | |
2de6847c TA |
230 | clocks = <&clock 292>, <&clock 149>; |
231 | clock-names = "uart", "clk_uart_baud0"; | |
b074abb7 KK |
232 | }; |
233 | ||
c47d244a VA |
234 | sata@122F0000 { |
235 | compatible = "samsung,exynos5-sata-ahci"; | |
236 | reg = <0x122F0000 0x1ff>; | |
237 | interrupts = <0 115 0>; | |
2de6847c TA |
238 | clocks = <&clock 277>, <&clock 143>; |
239 | clock-names = "sata", "sclk_sata"; | |
c47d244a VA |
240 | }; |
241 | ||
242 | sata-phy@12170000 { | |
243 | compatible = "samsung,exynos5-sata-phy"; | |
244 | reg = <0x12170000 0x1ff>; | |
245 | }; | |
246 | ||
b9fa3e7b | 247 | i2c_0: i2c@12C60000 { |
b074abb7 KK |
248 | compatible = "samsung,s3c2440-i2c"; |
249 | reg = <0x12C60000 0x100>; | |
250 | interrupts = <0 56 0>; | |
009f7c9f TA |
251 | #address-cells = <1>; |
252 | #size-cells = <0>; | |
2de6847c TA |
253 | clocks = <&clock 294>; |
254 | clock-names = "i2c"; | |
f8bfe2b0 TA |
255 | pinctrl-names = "default"; |
256 | pinctrl-0 = <&i2c0_bus>; | |
b074abb7 KK |
257 | }; |
258 | ||
b9fa3e7b | 259 | i2c_1: i2c@12C70000 { |
b074abb7 KK |
260 | compatible = "samsung,s3c2440-i2c"; |
261 | reg = <0x12C70000 0x100>; | |
262 | interrupts = <0 57 0>; | |
009f7c9f TA |
263 | #address-cells = <1>; |
264 | #size-cells = <0>; | |
2de6847c TA |
265 | clocks = <&clock 295>; |
266 | clock-names = "i2c"; | |
f8bfe2b0 TA |
267 | pinctrl-names = "default"; |
268 | pinctrl-0 = <&i2c1_bus>; | |
b074abb7 KK |
269 | }; |
270 | ||
b9fa3e7b | 271 | i2c_2: i2c@12C80000 { |
b074abb7 KK |
272 | compatible = "samsung,s3c2440-i2c"; |
273 | reg = <0x12C80000 0x100>; | |
274 | interrupts = <0 58 0>; | |
009f7c9f TA |
275 | #address-cells = <1>; |
276 | #size-cells = <0>; | |
2de6847c TA |
277 | clocks = <&clock 296>; |
278 | clock-names = "i2c"; | |
f8bfe2b0 TA |
279 | pinctrl-names = "default"; |
280 | pinctrl-0 = <&i2c2_bus>; | |
b074abb7 KK |
281 | }; |
282 | ||
b9fa3e7b | 283 | i2c_3: i2c@12C90000 { |
b074abb7 KK |
284 | compatible = "samsung,s3c2440-i2c"; |
285 | reg = <0x12C90000 0x100>; | |
286 | interrupts = <0 59 0>; | |
009f7c9f TA |
287 | #address-cells = <1>; |
288 | #size-cells = <0>; | |
2de6847c TA |
289 | clocks = <&clock 297>; |
290 | clock-names = "i2c"; | |
f8bfe2b0 TA |
291 | pinctrl-names = "default"; |
292 | pinctrl-0 = <&i2c3_bus>; | |
b074abb7 KK |
293 | }; |
294 | ||
b9fa3e7b | 295 | i2c_4: i2c@12CA0000 { |
b074abb7 KK |
296 | compatible = "samsung,s3c2440-i2c"; |
297 | reg = <0x12CA0000 0x100>; | |
298 | interrupts = <0 60 0>; | |
009f7c9f TA |
299 | #address-cells = <1>; |
300 | #size-cells = <0>; | |
2de6847c TA |
301 | clocks = <&clock 298>; |
302 | clock-names = "i2c"; | |
f8bfe2b0 TA |
303 | pinctrl-names = "default"; |
304 | pinctrl-0 = <&i2c4_bus>; | |
b074abb7 KK |
305 | }; |
306 | ||
b9fa3e7b | 307 | i2c_5: i2c@12CB0000 { |
b074abb7 KK |
308 | compatible = "samsung,s3c2440-i2c"; |
309 | reg = <0x12CB0000 0x100>; | |
310 | interrupts = <0 61 0>; | |
009f7c9f TA |
311 | #address-cells = <1>; |
312 | #size-cells = <0>; | |
2de6847c TA |
313 | clocks = <&clock 299>; |
314 | clock-names = "i2c"; | |
f8bfe2b0 TA |
315 | pinctrl-names = "default"; |
316 | pinctrl-0 = <&i2c5_bus>; | |
b074abb7 KK |
317 | }; |
318 | ||
b9fa3e7b | 319 | i2c_6: i2c@12CC0000 { |
b074abb7 KK |
320 | compatible = "samsung,s3c2440-i2c"; |
321 | reg = <0x12CC0000 0x100>; | |
322 | interrupts = <0 62 0>; | |
009f7c9f TA |
323 | #address-cells = <1>; |
324 | #size-cells = <0>; | |
2de6847c TA |
325 | clocks = <&clock 300>; |
326 | clock-names = "i2c"; | |
f8bfe2b0 TA |
327 | pinctrl-names = "default"; |
328 | pinctrl-0 = <&i2c6_bus>; | |
b074abb7 KK |
329 | }; |
330 | ||
b9fa3e7b | 331 | i2c_7: i2c@12CD0000 { |
b074abb7 KK |
332 | compatible = "samsung,s3c2440-i2c"; |
333 | reg = <0x12CD0000 0x100>; | |
334 | interrupts = <0 63 0>; | |
009f7c9f TA |
335 | #address-cells = <1>; |
336 | #size-cells = <0>; | |
2de6847c TA |
337 | clocks = <&clock 301>; |
338 | clock-names = "i2c"; | |
f8bfe2b0 TA |
339 | pinctrl-names = "default"; |
340 | pinctrl-0 = <&i2c7_bus>; | |
3e3e9ce4 RS |
341 | }; |
342 | ||
b9fa3e7b | 343 | i2c_8: i2c@12CE0000 { |
3e3e9ce4 RS |
344 | compatible = "samsung,s3c2440-hdmiphy-i2c"; |
345 | reg = <0x12CE0000 0x1000>; | |
346 | interrupts = <0 64 0>; | |
347 | #address-cells = <1>; | |
348 | #size-cells = <0>; | |
2de6847c TA |
349 | clocks = <&clock 302>; |
350 | clock-names = "i2c"; | |
24025f6f OJ |
351 | }; |
352 | ||
c47d244a VA |
353 | i2c@121D0000 { |
354 | compatible = "samsung,exynos5-sata-phy-i2c"; | |
355 | reg = <0x121D0000 0x100>; | |
356 | #address-cells = <1>; | |
357 | #size-cells = <0>; | |
2de6847c TA |
358 | clocks = <&clock 288>; |
359 | clock-names = "i2c"; | |
b074abb7 KK |
360 | }; |
361 | ||
79989ba3 TA |
362 | spi_0: spi@12d20000 { |
363 | compatible = "samsung,exynos4210-spi"; | |
364 | reg = <0x12d20000 0x100>; | |
365 | interrupts = <0 66 0>; | |
a4a8a9d3 PV |
366 | dmas = <&pdma0 5 |
367 | &pdma0 4>; | |
368 | dma-names = "tx", "rx"; | |
79989ba3 TA |
369 | #address-cells = <1>; |
370 | #size-cells = <0>; | |
2de6847c TA |
371 | clocks = <&clock 304>, <&clock 154>; |
372 | clock-names = "spi", "spi_busclk0"; | |
f8bfe2b0 TA |
373 | pinctrl-names = "default"; |
374 | pinctrl-0 = <&spi0_bus>; | |
79989ba3 TA |
375 | }; |
376 | ||
377 | spi_1: spi@12d30000 { | |
378 | compatible = "samsung,exynos4210-spi"; | |
379 | reg = <0x12d30000 0x100>; | |
380 | interrupts = <0 67 0>; | |
a4a8a9d3 PV |
381 | dmas = <&pdma1 5 |
382 | &pdma1 4>; | |
383 | dma-names = "tx", "rx"; | |
79989ba3 TA |
384 | #address-cells = <1>; |
385 | #size-cells = <0>; | |
2de6847c TA |
386 | clocks = <&clock 305>, <&clock 155>; |
387 | clock-names = "spi", "spi_busclk0"; | |
f8bfe2b0 TA |
388 | pinctrl-names = "default"; |
389 | pinctrl-0 = <&spi1_bus>; | |
79989ba3 TA |
390 | }; |
391 | ||
392 | spi_2: spi@12d40000 { | |
393 | compatible = "samsung,exynos4210-spi"; | |
394 | reg = <0x12d40000 0x100>; | |
395 | interrupts = <0 68 0>; | |
a4a8a9d3 PV |
396 | dmas = <&pdma0 7 |
397 | &pdma0 6>; | |
398 | dma-names = "tx", "rx"; | |
79989ba3 TA |
399 | #address-cells = <1>; |
400 | #size-cells = <0>; | |
2de6847c TA |
401 | clocks = <&clock 306>, <&clock 156>; |
402 | clock-names = "spi", "spi_busclk0"; | |
f8bfe2b0 TA |
403 | pinctrl-names = "default"; |
404 | pinctrl-0 = <&spi2_bus>; | |
79989ba3 TA |
405 | }; |
406 | ||
de0f42be | 407 | dwmmc_0: dwmmc0@12200000 { |
84bd48a0 TA |
408 | compatible = "samsung,exynos5250-dw-mshc"; |
409 | reg = <0x12200000 0x1000>; | |
410 | interrupts = <0 75 0>; | |
411 | #address-cells = <1>; | |
412 | #size-cells = <0>; | |
2de6847c TA |
413 | clocks = <&clock 280>, <&clock 139>; |
414 | clock-names = "biu", "ciu"; | |
84bd48a0 TA |
415 | }; |
416 | ||
de0f42be | 417 | dwmmc_1: dwmmc1@12210000 { |
84bd48a0 TA |
418 | compatible = "samsung,exynos5250-dw-mshc"; |
419 | reg = <0x12210000 0x1000>; | |
420 | interrupts = <0 76 0>; | |
421 | #address-cells = <1>; | |
422 | #size-cells = <0>; | |
2de6847c TA |
423 | clocks = <&clock 281>, <&clock 140>; |
424 | clock-names = "biu", "ciu"; | |
84bd48a0 TA |
425 | }; |
426 | ||
de0f42be | 427 | dwmmc_2: dwmmc2@12220000 { |
84bd48a0 TA |
428 | compatible = "samsung,exynos5250-dw-mshc"; |
429 | reg = <0x12220000 0x1000>; | |
430 | interrupts = <0 77 0>; | |
431 | #address-cells = <1>; | |
432 | #size-cells = <0>; | |
2de6847c TA |
433 | clocks = <&clock 282>, <&clock 141>; |
434 | clock-names = "biu", "ciu"; | |
84bd48a0 TA |
435 | }; |
436 | ||
de0f42be | 437 | dwmmc_3: dwmmc3@12230000 { |
84bd48a0 TA |
438 | compatible = "samsung,exynos5250-dw-mshc"; |
439 | reg = <0x12230000 0x1000>; | |
440 | interrupts = <0 78 0>; | |
441 | #address-cells = <1>; | |
442 | #size-cells = <0>; | |
2de6847c TA |
443 | clocks = <&clock 283>, <&clock 142>; |
444 | clock-names = "biu", "ciu"; | |
84bd48a0 TA |
445 | }; |
446 | ||
28a48058 | 447 | i2s0: i2s@03830000 { |
4c4c7463 PV |
448 | compatible = "samsung,i2s-v5"; |
449 | reg = <0x03830000 0x100>; | |
450 | dmas = <&pdma0 10 | |
451 | &pdma0 9 | |
452 | &pdma0 8>; | |
453 | dma-names = "tx", "rx", "tx-sec"; | |
454 | samsung,supports-6ch; | |
455 | samsung,supports-rstclr; | |
456 | samsung,supports-secdai; | |
457 | samsung,idma-addr = <0x03000000>; | |
f8bfe2b0 TA |
458 | pinctrl-names = "default"; |
459 | pinctrl-0 = <&i2s0_bus>; | |
4c4c7463 PV |
460 | }; |
461 | ||
28a48058 | 462 | i2s1: i2s@12D60000 { |
4c4c7463 PV |
463 | compatible = "samsung,i2s-v5"; |
464 | reg = <0x12D60000 0x100>; | |
465 | dmas = <&pdma1 12 | |
466 | &pdma1 11>; | |
467 | dma-names = "tx", "rx"; | |
f8bfe2b0 TA |
468 | pinctrl-names = "default"; |
469 | pinctrl-0 = <&i2s1_bus>; | |
4c4c7463 PV |
470 | }; |
471 | ||
28a48058 | 472 | i2s2: i2s@12D70000 { |
4c4c7463 PV |
473 | compatible = "samsung,i2s-v5"; |
474 | reg = <0x12D70000 0x100>; | |
475 | dmas = <&pdma0 12 | |
476 | &pdma0 11>; | |
477 | dma-names = "tx", "rx"; | |
f8bfe2b0 TA |
478 | pinctrl-names = "default"; |
479 | pinctrl-0 = <&i2s2_bus>; | |
4c4c7463 PV |
480 | }; |
481 | ||
13cbd1e3 VG |
482 | usb@12110000 { |
483 | compatible = "samsung,exynos4210-ehci"; | |
484 | reg = <0x12110000 0x100>; | |
485 | interrupts = <0 71 0>; | |
b3cd7d87 DA |
486 | |
487 | clocks = <&clock 285>; | |
488 | clock-names = "usbhost"; | |
13cbd1e3 VG |
489 | }; |
490 | ||
7d40d867 VG |
491 | usb@12120000 { |
492 | compatible = "samsung,exynos4210-ohci"; | |
493 | reg = <0x12120000 0x100>; | |
494 | interrupts = <0 71 0>; | |
b3cd7d87 DA |
495 | |
496 | clocks = <&clock 285>; | |
497 | clock-names = "usbhost"; | |
7d40d867 VG |
498 | }; |
499 | ||
7ec892ef VG |
500 | usbphy@12130000 { |
501 | compatible = "samsung,exynos5250-usb2phy"; | |
502 | reg = <0x12130000 0x100>; | |
503 | clocks = <&clock 1>, <&clock 285>; | |
504 | clock-names = "ext_xtal", "usbhost"; | |
505 | #address-cells = <1>; | |
506 | #size-cells = <1>; | |
507 | ranges; | |
508 | ||
509 | usbphy-sys { | |
510 | reg = <0x10040704 0x8>, | |
511 | <0x10050230 0x4>; | |
512 | }; | |
513 | }; | |
514 | ||
b074abb7 KK |
515 | amba { |
516 | #address-cells = <1>; | |
517 | #size-cells = <1>; | |
518 | compatible = "arm,amba-bus"; | |
519 | interrupt-parent = <&gic>; | |
520 | ranges; | |
521 | ||
522 | pdma0: pdma@121A0000 { | |
523 | compatible = "arm,pl330", "arm,primecell"; | |
524 | reg = <0x121A0000 0x1000>; | |
525 | interrupts = <0 34 0>; | |
2de6847c TA |
526 | clocks = <&clock 275>; |
527 | clock-names = "apb_pclk"; | |
42cf2098 PV |
528 | #dma-cells = <1>; |
529 | #dma-channels = <8>; | |
530 | #dma-requests = <32>; | |
b074abb7 KK |
531 | }; |
532 | ||
533 | pdma1: pdma@121B0000 { | |
534 | compatible = "arm,pl330", "arm,primecell"; | |
535 | reg = <0x121B0000 0x1000>; | |
536 | interrupts = <0 35 0>; | |
2de6847c TA |
537 | clocks = <&clock 276>; |
538 | clock-names = "apb_pclk"; | |
42cf2098 PV |
539 | #dma-cells = <1>; |
540 | #dma-channels = <8>; | |
541 | #dma-requests = <32>; | |
b074abb7 KK |
542 | }; |
543 | ||
009f7c9f | 544 | mdma0: mdma@10800000 { |
b074abb7 KK |
545 | compatible = "arm,pl330", "arm,primecell"; |
546 | reg = <0x10800000 0x1000>; | |
547 | interrupts = <0 33 0>; | |
2de6847c TA |
548 | clocks = <&clock 271>; |
549 | clock-names = "apb_pclk"; | |
42cf2098 PV |
550 | #dma-cells = <1>; |
551 | #dma-channels = <8>; | |
552 | #dma-requests = <1>; | |
b074abb7 KK |
553 | }; |
554 | ||
009f7c9f | 555 | mdma1: mdma@11C10000 { |
b074abb7 KK |
556 | compatible = "arm,pl330", "arm,primecell"; |
557 | reg = <0x11C10000 0x1000>; | |
558 | interrupts = <0 124 0>; | |
2de6847c TA |
559 | clocks = <&clock 271>; |
560 | clock-names = "apb_pclk"; | |
42cf2098 PV |
561 | #dma-cells = <1>; |
562 | #dma-channels = <8>; | |
563 | #dma-requests = <1>; | |
b074abb7 KK |
564 | }; |
565 | }; | |
566 | ||
1128658a SAB |
567 | gsc_0: gsc@0x13e00000 { |
568 | compatible = "samsung,exynos5-gsc"; | |
569 | reg = <0x13e00000 0x1000>; | |
570 | interrupts = <0 85 0>; | |
6f9e95e6 | 571 | samsung,power-domain = <&pd_gsc>; |
2de6847c TA |
572 | clocks = <&clock 256>; |
573 | clock-names = "gscl"; | |
1128658a SAB |
574 | }; |
575 | ||
576 | gsc_1: gsc@0x13e10000 { | |
577 | compatible = "samsung,exynos5-gsc"; | |
578 | reg = <0x13e10000 0x1000>; | |
579 | interrupts = <0 86 0>; | |
6f9e95e6 | 580 | samsung,power-domain = <&pd_gsc>; |
2de6847c TA |
581 | clocks = <&clock 257>; |
582 | clock-names = "gscl"; | |
1128658a SAB |
583 | }; |
584 | ||
585 | gsc_2: gsc@0x13e20000 { | |
586 | compatible = "samsung,exynos5-gsc"; | |
587 | reg = <0x13e20000 0x1000>; | |
588 | interrupts = <0 87 0>; | |
6f9e95e6 | 589 | samsung,power-domain = <&pd_gsc>; |
2de6847c TA |
590 | clocks = <&clock 258>; |
591 | clock-names = "gscl"; | |
1128658a SAB |
592 | }; |
593 | ||
594 | gsc_3: gsc@0x13e30000 { | |
595 | compatible = "samsung,exynos5-gsc"; | |
596 | reg = <0x13e30000 0x1000>; | |
597 | interrupts = <0 88 0>; | |
6f9e95e6 | 598 | samsung,power-domain = <&pd_gsc>; |
2de6847c TA |
599 | clocks = <&clock 259>; |
600 | clock-names = "gscl"; | |
1128658a | 601 | }; |
566cf8ee RS |
602 | |
603 | hdmi { | |
604 | compatible = "samsung,exynos5-hdmi"; | |
101250ce | 605 | reg = <0x14530000 0x70000>; |
566cf8ee | 606 | interrupts = <0 95 0>; |
2de6847c TA |
607 | clocks = <&clock 333>, <&clock 136>, <&clock 137>, |
608 | <&clock 333>, <&clock 333>; | |
609 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", | |
610 | "sclk_hdmiphy", "hdmiphy"; | |
566cf8ee | 611 | }; |
5af0d8a3 RS |
612 | |
613 | mixer { | |
614 | compatible = "samsung,exynos5-mixer"; | |
615 | reg = <0x14450000 0x10000>; | |
616 | interrupts = <0 94 0>; | |
617 | }; | |
ad4aebe1 JH |
618 | |
619 | dp-controller { | |
620 | compatible = "samsung,exynos5-dp"; | |
621 | reg = <0x145b0000 0x1000>; | |
622 | interrupts = <10 3>; | |
623 | interrupt-parent = <&combiner>; | |
624 | #address-cells = <1>; | |
625 | #size-cells = <0>; | |
626 | ||
627 | dptx-phy { | |
628 | reg = <0x10040720>; | |
629 | samsung,enable-mask = <1>; | |
630 | }; | |
631 | }; | |
a7389cb1 LKA |
632 | |
633 | fimd { | |
634 | compatible = "samsung,exynos5250-fimd"; | |
635 | interrupt-parent = <&combiner>; | |
636 | reg = <0x14400000 0x40000>; | |
637 | interrupt-names = "fifo", "vsync", "lcd_sys"; | |
638 | interrupts = <18 4>, <18 5>, <18 6>; | |
639 | clocks = <&clock 133>, <&clock 339>; | |
640 | clock-names = "sclk_fimd", "fimd"; | |
641 | }; | |
b074abb7 | 642 | }; |