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Merge tag 'for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux...
[deliverable/linux.git] / arch / arm / boot / dts / exynos5250.dtsi
CommitLineData
b074abb7
KK		 1/*
2 * SAMSUNG EXYNOS5250 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
fe273c3e 20#include <dt-bindings/clock/exynos5250.h>
e6c21cba 21#include "exynos5.dtsi"
3799279f 22#include "exynos5250-pinctrl.dtsi"
9843a223 23#include "exynos4-cpu-thermal.dtsi"
602408e3 24#include <dt-bindings/clock/exynos-audss-clk.h>
b074abb7
KK		 25
26/ {
8bdb31b4 27 compatible = "samsung,exynos5250", "samsung,exynos5";
b074abb7 28
79989ba3
TA		 29 aliases {
30 spi0 = &spi_0;
31 spi1 = &spi_1;
32 spi2 = &spi_2;
1128658a
SAB		 33 gsc0 = &gsc_0;
34 gsc1 = &gsc_1;
35 gsc2 = &gsc_2;
36 gsc3 = &gsc_3;
c8149df0
YK		 37 mshc0 = &mmc_0;
38 mshc1 = &mmc_1;
39 mshc2 = &mmc_2;
40 mshc3 = &mmc_3;
b9fa3e7b
AK		 41 i2c0 = &i2c_0;
42 i2c1 = &i2c_1;
43 i2c2 = &i2c_2;
44 i2c3 = &i2c_3;
45 i2c4 = &i2c_4;
46 i2c5 = &i2c_5;
47 i2c6 = &i2c_6;
48 i2c7 = &i2c_7;
49 i2c8 = &i2c_8;
ba0d7ed3 50 i2c9 = &i2c_9;
f8bfe2b0
TA		 51 pinctrl0 = &pinctrl_0;
52 pinctrl1 = &pinctrl_1;
53 pinctrl2 = &pinctrl_2;
54 pinctrl3 = &pinctrl_3;
79989ba3
TA		 55 };
56
1897d2f3
CK		 57 cpus {
58 #address-cells = <1>;
59 #size-cells = <0>;
60
bf4a0bed 61 cpu0: cpu@0 {
1897d2f3
CK		 62 device_type = "cpu";
63 compatible = "arm,cortex-a15";
64 reg = <0>;
0da80563 65 clock-frequency = <1700000000>;
bf4a0bed
LM		 66 cooling-min-level = <15>;
67 cooling-max-level = <9>;
68 #cooling-cells = <2>; /* min followed by max */
1897d2f3
CK		 69 };
70 cpu@1 {
71 device_type = "cpu";
72 compatible = "arm,cortex-a15";
73 reg = <1>;
0da80563 74 clock-frequency = <1700000000>;
1897d2f3 75 };
79989ba3
TA		 76 };
77
b3205dea
SK		 78 sysram@02020000 {
79 compatible = "mmio-sram";
80 reg = <0x02020000 0x30000>;
81 #address-cells = <1>;
82 #size-cells = <1>;
83 ranges = <0 0x02020000 0x30000>;
84
85 smp-sysram@0 {
86 compatible = "samsung,exynos4210-sysram";
87 reg = <0x0 0x1000>;
88 };
89
90 smp-sysram@2f000 {
91 compatible = "samsung,exynos4210-sysram-ns";
92 reg = <0x2f000 0x1000>;
93 };
94 };
95
c31f566d 96 pd_gsc: gsc-power-domain@10044000 {
6f9e95e6
PK		 97 compatible = "samsung,exynos4210-pd";
98 reg = <0x10044000 0x20>;
0da65870 99 #power-domain-cells = <0>;
6f9e95e6
PK		 100 };
101
c31f566d 102 pd_mfc: mfc-power-domain@10044040 {
6f9e95e6
PK		 103 compatible = "samsung,exynos4210-pd";
104 reg = <0x10044040 0x20>;
0da65870 105 #power-domain-cells = <0>;
6f9e95e6
PK		 106 };
107
2d2c9a8d
AH		 108 pd_disp1: disp1-power-domain@100440A0 {
109 compatible = "samsung,exynos4210-pd";
110 reg = <0x100440A0 0x20>;
111 #power-domain-cells = <0>;
112 };
113
c31f566d 114 clock: clock-controller@10010000 {
d8bafc87
TA		 115 compatible = "samsung,exynos5250-clock";
116 reg = <0x10010000 0x30000>;
117 #clock-cells = <1>;
118 };
119
bba23d95
PV		 120 clock_audss: audss-clock-controller@3810000 {
121 compatible = "samsung,exynos5250-audss-clock";
122 reg = <0x03810000 0x0C>;
123 #clock-cells = <1>;
fe273c3e
AH		 124 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
125 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
c08ceea3 126 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
bba23d95
PV		 127 };
128
2b7da988
AG		 129 timer {
130 compatible = "arm,armv7-timer";
131 interrupts = <1 13 0xf08>,
132 <1 14 0xf08>,
133 <1 11 0xf08>,
134 <1 10 0xf08>;
4d594dd3
YK		 135 /* Unfortunately we need this since some versions of U-Boot
136 * on Exynos don't set the CNTFRQ register, so we need the
137 * value from DT.
138 */
139 clock-frequency = <24000000>;
b074abb7
KK		 140 };
141
bbd9700a
TA		 142 mct@101C0000 {
143 compatible = "samsung,exynos4210-mct";
144 reg = <0x101C0000 0x800>;
145 interrupt-controller;
146 #interrups-cells = <2>;
147 interrupt-parent = <&mct_map>;
148 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
149 <4 0>, <5 0>;
fe273c3e 150 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
2de6847c 151 clock-names = "fin_pll", "mct";
bbd9700a
TA		 152
153 mct_map: mct-map {
154 #interrupt-cells = <2>;
155 #address-cells = <0>;
156 #size-cells = <0>;
157 interrupt-map = <0x0 0 &combiner 23 3>,
158 <0x1 0 &combiner 23 4>,
159 <0x2 0 &combiner 25 2>,
160 <0x3 0 &combiner 25 3>,
161 <0x4 0 &gic 0 120 0>,
162 <0x5 0 &gic 0 121 0>;
163 };
164 };
165
4f801e59
CP		 166 pmu {
167 compatible = "arm,cortex-a15-pmu";
168 interrupt-parent = <&combiner>;
169 interrupts = <1 2>, <22 4>;
170 };
171
f8bfe2b0
TA		 172 pinctrl_0: pinctrl@11400000 {
173 compatible = "samsung,exynos5250-pinctrl";
174 reg = <0x11400000 0x1000>;
175 interrupts = <0 46 0>;
176
177 wakup_eint: wakeup-interrupt-controller {
178 compatible = "samsung,exynos4210-wakeup-eint";
179 interrupt-parent = <&gic>;
180 interrupts = <0 32 0>;
181 };
182 };
183
184 pinctrl_1: pinctrl@13400000 {
185 compatible = "samsung,exynos5250-pinctrl";
186 reg = <0x13400000 0x1000>;
187 interrupts = <0 45 0>;
188 };
189
190 pinctrl_2: pinctrl@10d10000 {
191 compatible = "samsung,exynos5250-pinctrl";
192 reg = <0x10d10000 0x1000>;
193 interrupts = <0 50 0>;
194 };
195
0abb6aea 196 pinctrl_3: pinctrl@03860000 {
f8bfe2b0 197 compatible = "samsung,exynos5250-pinctrl";
0abb6aea 198 reg = <0x03860000 0x1000>;
f8bfe2b0
TA		 199 interrupts = <0 47 0>;
200 };
201
c680036a
LKA		 202 pmu_system_controller: system-controller@10040000 {
203 compatible = "samsung,exynos5250-pmu", "syscon";
204 reg = <0x10040000 0x5000>;
d19bb397
TF		 205 clock-names = "clkout16";
206 clocks = <&clock CLK_FIN_PLL>;
207 #clock-cells = <1>;
c680036a
LKA		 208 };
209
dfbbdbf4
VG		 210 sysreg_system_controller: syscon@10050000 {
211 compatible = "samsung,exynos5-sysreg", "syscon";
212 reg = <0x10050000 0x5000>;
213 };
214
1d287620
LKA		 215 watchdog@101D0000 {
216 compatible = "samsung,exynos5250-wdt";
217 reg = <0x101D0000 0x100>;
218 interrupts = <0 42 0>;
fe273c3e 219 clocks = <&clock CLK_WDT>;
2de6847c 220 clock-names = "watchdog";
1d287620 221 samsung,syscon-phandle = <&pmu_system_controller>;
b074abb7
KK		 222 };
223
21aa5217
SK		 224 g2d@10850000 {
225 compatible = "samsung,exynos5250-g2d";
226 reg = <0x10850000 0x1000>;
227 interrupts = <0 91 0>;
fe273c3e 228 clocks = <&clock CLK_G2D>;
21aa5217
SK		 229 clock-names = "fimg2d";
230 };
231
19fd45bf 232 mfc: codec@11000000 {
2eae613b
AK		 233 compatible = "samsung,mfc-v6";
234 reg = <0x11000000 0x10000>;
235 interrupts = <0 96 0>;
0da65870 236 power-domains = <&pd_mfc>;
fe273c3e 237 clocks = <&clock CLK_MFC>;
8b6bea33 238 clock-names = "mfc";
2eae613b
AK		 239 };
240
19fd45bf 241 rtc: rtc@101E0000 {
fe273c3e 242 clocks = <&clock CLK_RTC>;
2de6847c 243 clock-names = "rtc";
65cedf0e 244 status = "disabled";
b074abb7
KK		 245 };
246
9843a223 247 tmu: tmu@10060000 {
ef405e04
ADK		 248 compatible = "samsung,exynos5250-tmu";
249 reg = <0x10060000 0x100>;
250 interrupts = <0 65 0>;
fe273c3e 251 clocks = <&clock CLK_TMU>;
2de6847c 252 clock-names = "tmu_apbif";
9843a223 253 #include "exynos4412-tmu-sensor-conf.dtsi"
ef405e04
ADK		 254 };
255
bf4a0bed
LM		 256 thermal-zones {
257 cpu_thermal: cpu-thermal {
9843a223
LM		 258 polling-delay-passive = <0>;
259 polling-delay = <0>;
260 thermal-sensors = <&tmu 0>;
261
bf4a0bed
LM		 262 cooling-maps {
263 map0 {
264 /* Corresponds to 800MHz at freq_table */
265 cooling-device = <&cpu0 9 9>;
266 };
267 map1 {
268 /* Corresponds to 200MHz at freq_table */
269 cooling-device = <&cpu0 15 15>;
270 };
271 };
272 };
273 };
274
b074abb7 275 serial@12C00000 {
fe273c3e 276 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
2de6847c 277 clock-names = "uart", "clk_uart_baud0";
b074abb7
KK		 278 };
279
280 serial@12C10000 {
fe273c3e 281 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
2de6847c 282 clock-names = "uart", "clk_uart_baud0";
b074abb7
KK		 283 };
284
285 serial@12C20000 {
fe273c3e 286 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
2de6847c 287 clock-names = "uart", "clk_uart_baud0";
b074abb7
KK		 288 };
289
290 serial@12C30000 {
fe273c3e 291 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
2de6847c 292 clock-names = "uart", "clk_uart_baud0";
b074abb7
KK		 293 };
294
19fd45bf 295 sata: sata@122F0000 {
ba0d7ed3
YK		 296 compatible = "snps,dwc-ahci";
297 samsung,sata-freq = <66>;
c47d244a
VA		 298 reg = <0x122F0000 0x1ff>;
299 interrupts = <0 115 0>;
fe273c3e 300 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
2de6847c 301 clock-names = "sata", "sclk_sata";
ba0d7ed3
YK		 302 phys = <&sata_phy>;
303 phy-names = "sata-phy";
304 status = "disabled";
c47d244a
VA		 305 };
306
ba0d7ed3
YK		 307 sata_phy: sata-phy@12170000 {
308 compatible = "samsung,exynos5250-sata-phy";
c47d244a 309 reg = <0x12170000 0x1ff>;
e06e1067 310 clocks = <&clock CLK_SATA_PHYCTRL>;
ba0d7ed3
YK		 311 clock-names = "sata_phyctrl";
312 #phy-cells = <0>;
313 samsung,syscon-phandle = <&pmu_system_controller>;
314 status = "disabled";
c47d244a
VA		 315 };
316
b9fa3e7b 317 i2c_0: i2c@12C60000 {
b074abb7
KK		 318 compatible = "samsung,s3c2440-i2c";
319 reg = <0x12C60000 0x100>;
320 interrupts = <0 56 0>;
009f7c9f
TA		 321 #address-cells = <1>;
322 #size-cells = <0>;
fe273c3e 323 clocks = <&clock CLK_I2C0>;
2de6847c 324 clock-names = "i2c";
f8bfe2b0
TA		 325 pinctrl-names = "default";
326 pinctrl-0 = <&i2c0_bus>;
1888eb75 327 samsung,sysreg-phandle = <&sysreg_system_controller>;
6ad8ebff 328 status = "disabled";
b074abb7
KK		 329 };
330
b9fa3e7b 331 i2c_1: i2c@12C70000 {
b074abb7
KK		 332 compatible = "samsung,s3c2440-i2c";
333 reg = <0x12C70000 0x100>;
334 interrupts = <0 57 0>;
009f7c9f
TA		 335 #address-cells = <1>;
336 #size-cells = <0>;
fe273c3e 337 clocks = <&clock CLK_I2C1>;
2de6847c 338 clock-names = "i2c";
f8bfe2b0
TA		 339 pinctrl-names = "default";
340 pinctrl-0 = <&i2c1_bus>;
1888eb75 341 samsung,sysreg-phandle = <&sysreg_system_controller>;
6ad8ebff 342 status = "disabled";
b074abb7
KK		 343 };
344
b9fa3e7b 345 i2c_2: i2c@12C80000 {
b074abb7
KK		 346 compatible = "samsung,s3c2440-i2c";
347 reg = <0x12C80000 0x100>;
348 interrupts = <0 58 0>;
009f7c9f
TA		 349 #address-cells = <1>;
350 #size-cells = <0>;
fe273c3e 351 clocks = <&clock CLK_I2C2>;
2de6847c 352 clock-names = "i2c";
f8bfe2b0
TA		 353 pinctrl-names = "default";
354 pinctrl-0 = <&i2c2_bus>;
1888eb75 355 samsung,sysreg-phandle = <&sysreg_system_controller>;
6ad8ebff 356 status = "disabled";
b074abb7
KK		 357 };
358
b9fa3e7b 359 i2c_3: i2c@12C90000 {
b074abb7
KK		 360 compatible = "samsung,s3c2440-i2c";
361 reg = <0x12C90000 0x100>;
362 interrupts = <0 59 0>;
009f7c9f
TA		 363 #address-cells = <1>;
364 #size-cells = <0>;
fe273c3e 365 clocks = <&clock CLK_I2C3>;
2de6847c 366 clock-names = "i2c";
f8bfe2b0
TA		 367 pinctrl-names = "default";
368 pinctrl-0 = <&i2c3_bus>;
1888eb75 369 samsung,sysreg-phandle = <&sysreg_system_controller>;
6ad8ebff 370 status = "disabled";
b074abb7
KK		 371 };
372
b9fa3e7b 373 i2c_4: i2c@12CA0000 {
b074abb7
KK		 374 compatible = "samsung,s3c2440-i2c";
375 reg = <0x12CA0000 0x100>;
376 interrupts = <0 60 0>;
009f7c9f
TA		 377 #address-cells = <1>;
378 #size-cells = <0>;
fe273c3e 379 clocks = <&clock CLK_I2C4>;
2de6847c 380 clock-names = "i2c";
f8bfe2b0
TA		 381 pinctrl-names = "default";
382 pinctrl-0 = <&i2c4_bus>;
6ad8ebff 383 status = "disabled";
b074abb7
KK		 384 };
385
b9fa3e7b 386 i2c_5: i2c@12CB0000 {
b074abb7
KK		 387 compatible = "samsung,s3c2440-i2c";
388 reg = <0x12CB0000 0x100>;
389 interrupts = <0 61 0>;
009f7c9f
TA		 390 #address-cells = <1>;
391 #size-cells = <0>;
fe273c3e 392 clocks = <&clock CLK_I2C5>;
2de6847c 393 clock-names = "i2c";
f8bfe2b0
TA		 394 pinctrl-names = "default";
395 pinctrl-0 = <&i2c5_bus>;
6ad8ebff 396 status = "disabled";
b074abb7
KK		 397 };
398
b9fa3e7b 399 i2c_6: i2c@12CC0000 {
b074abb7
KK		 400 compatible = "samsung,s3c2440-i2c";
401 reg = <0x12CC0000 0x100>;
402 interrupts = <0 62 0>;
009f7c9f
TA		 403 #address-cells = <1>;
404 #size-cells = <0>;
fe273c3e 405 clocks = <&clock CLK_I2C6>;
2de6847c 406 clock-names = "i2c";
f8bfe2b0
TA		 407 pinctrl-names = "default";
408 pinctrl-0 = <&i2c6_bus>;
6ad8ebff 409 status = "disabled";
b074abb7
KK		 410 };
411
b9fa3e7b 412 i2c_7: i2c@12CD0000 {
b074abb7
KK		 413 compatible = "samsung,s3c2440-i2c";
414 reg = <0x12CD0000 0x100>;
415 interrupts = <0 63 0>;
009f7c9f
TA		 416 #address-cells = <1>;
417 #size-cells = <0>;
fe273c3e 418 clocks = <&clock CLK_I2C7>;
2de6847c 419 clock-names = "i2c";
f8bfe2b0
TA		 420 pinctrl-names = "default";
421 pinctrl-0 = <&i2c7_bus>;
6ad8ebff 422 status = "disabled";
3e3e9ce4
RS		 423 };
424
b9fa3e7b 425 i2c_8: i2c@12CE0000 {
3e3e9ce4
RS		 426 compatible = "samsung,s3c2440-hdmiphy-i2c";
427 reg = <0x12CE0000 0x1000>;
428 interrupts = <0 64 0>;
429 #address-cells = <1>;
430 #size-cells = <0>;
fe273c3e 431 clocks = <&clock CLK_I2C_HDMI>;
2de6847c 432 clock-names = "i2c";
6ad8ebff 433 status = "disabled";
24025f6f
OJ		 434 };
435
ba0d7ed3 436 i2c_9: i2c@121D0000 {
c47d244a
VA		 437 compatible = "samsung,exynos5-sata-phy-i2c";
438 reg = <0x121D0000 0x100>;
439 #address-cells = <1>;
440 #size-cells = <0>;
fe273c3e 441 clocks = <&clock CLK_SATA_PHYI2C>;
2de6847c 442 clock-names = "i2c";
6ad8ebff 443 status = "disabled";
b074abb7
KK		 444 };
445
79989ba3
TA		 446 spi_0: spi@12d20000 {
447 compatible = "samsung,exynos4210-spi";
fae93f7c 448 status = "disabled";
79989ba3
TA		 449 reg = <0x12d20000 0x100>;
450 interrupts = <0 66 0>;
a4a8a9d3
PV		 451 dmas = <&pdma0 5
452 &pdma0 4>;
453 dma-names = "tx", "rx";
79989ba3
TA		 454 #address-cells = <1>;
455 #size-cells = <0>;
fe273c3e 456 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
2de6847c 457 clock-names = "spi", "spi_busclk0";
f8bfe2b0
TA		 458 pinctrl-names = "default";
459 pinctrl-0 = <&spi0_bus>;
79989ba3
TA		 460 };
461
462 spi_1: spi@12d30000 {
463 compatible = "samsung,exynos4210-spi";
fae93f7c 464 status = "disabled";
79989ba3
TA		 465 reg = <0x12d30000 0x100>;
466 interrupts = <0 67 0>;
a4a8a9d3
PV		 467 dmas = <&pdma1 5
468 &pdma1 4>;
469 dma-names = "tx", "rx";
79989ba3
TA		 470 #address-cells = <1>;
471 #size-cells = <0>;
fe273c3e 472 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
2de6847c 473 clock-names = "spi", "spi_busclk0";
f8bfe2b0
TA		 474 pinctrl-names = "default";
475 pinctrl-0 = <&spi1_bus>;
79989ba3
TA		 476 };
477
478 spi_2: spi@12d40000 {
479 compatible = "samsung,exynos4210-spi";
fae93f7c 480 status = "disabled";
79989ba3
TA		 481 reg = <0x12d40000 0x100>;
482 interrupts = <0 68 0>;
a4a8a9d3
PV		 483 dmas = <&pdma0 7
484 &pdma0 6>;
485 dma-names = "tx", "rx";
79989ba3
TA		 486 #address-cells = <1>;
487 #size-cells = <0>;
fe273c3e 488 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
2de6847c 489 clock-names = "spi", "spi_busclk0";
f8bfe2b0
TA		 490 pinctrl-names = "default";
491 pinctrl-0 = <&spi2_bus>;
79989ba3
TA		 492 };
493
c8149df0 494 mmc_0: mmc@12200000 {
906fd84e
YK		 495 compatible = "samsung,exynos5250-dw-mshc";
496 interrupts = <0 75 0>;
497 #address-cells = <1>;
498 #size-cells = <0>;
84bd48a0 499 reg = <0x12200000 0x1000>;
fe273c3e 500 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
2de6847c 501 clock-names = "biu", "ciu";
46285a90 502 fifo-depth = <0x80>;
e908d5c5 503 status = "disabled";
84bd48a0
TA		 504 };
505
c8149df0 506 mmc_1: mmc@12210000 {
906fd84e
YK		 507 compatible = "samsung,exynos5250-dw-mshc";
508 interrupts = <0 76 0>;
509 #address-cells = <1>;
510 #size-cells = <0>;
84bd48a0 511 reg = <0x12210000 0x1000>;
fe273c3e 512 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
2de6847c 513 clock-names = "biu", "ciu";
46285a90 514 fifo-depth = <0x80>;
e908d5c5 515 status = "disabled";
84bd48a0
TA		 516 };
517
c8149df0 518 mmc_2: mmc@12220000 {
906fd84e
YK		 519 compatible = "samsung,exynos5250-dw-mshc";
520 interrupts = <0 77 0>;
521 #address-cells = <1>;
522 #size-cells = <0>;
84bd48a0 523 reg = <0x12220000 0x1000>;
fe273c3e 524 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
2de6847c 525 clock-names = "biu", "ciu";
46285a90 526 fifo-depth = <0x80>;
e908d5c5 527 status = "disabled";
84bd48a0
TA		 528 };
529
c8149df0 530 mmc_3: mmc@12230000 {
84bd48a0
TA		 531 compatible = "samsung,exynos5250-dw-mshc";
532 reg = <0x12230000 0x1000>;
533 interrupts = <0 78 0>;
534 #address-cells = <1>;
535 #size-cells = <0>;
fe273c3e 536 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
2de6847c 537 clock-names = "biu", "ciu";
46285a90 538 fifo-depth = <0x80>;
e908d5c5 539 status = "disabled";
84bd48a0
TA		 540 };
541
28a48058 542 i2s0: i2s@03830000 {
64183656 543 compatible = "samsung,s5pv210-i2s";
328aee4b 544 status = "disabled";
a0b5f81e 545 reg = <0x03830000 0x100>;
4c4c7463
PV		 546 dmas = <&pdma0 10
547 &pdma0 9
548 &pdma0 8>;
549 dma-names = "tx", "rx", "tx-sec";
916ec47e
PV		 550 clocks = <&clock_audss EXYNOS_I2S_BUS>,
551 <&clock_audss EXYNOS_I2S_BUS>,
552 <&clock_audss EXYNOS_SCLK_I2S>;
553 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
a0b5f81e 554 samsung,idma-addr = <0x03000000>;
f8bfe2b0
TA		 555 pinctrl-names = "default";
556 pinctrl-0 = <&i2s0_bus>;
4c4c7463
PV		 557 };
558
28a48058 559 i2s1: i2s@12D60000 {
64183656 560 compatible = "samsung,s3c6410-i2s";
328aee4b 561 status = "disabled";
a0b5f81e
MB		 562 reg = <0x12D60000 0x100>;
563 dmas = <&pdma1 12
564 &pdma1 11>;
565 dma-names = "tx", "rx";
fe273c3e 566 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
916ec47e 567 clock-names = "iis", "i2s_opclk0";
f8bfe2b0
TA		 568 pinctrl-names = "default";
569 pinctrl-0 = <&i2s1_bus>;
4c4c7463
PV		 570 };
571
28a48058 572 i2s2: i2s@12D70000 {
64183656 573 compatible = "samsung,s3c6410-i2s";
328aee4b 574 status = "disabled";
a0b5f81e
MB		 575 reg = <0x12D70000 0x100>;
576 dmas = <&pdma0 12
577 &pdma0 11>;
578 dma-names = "tx", "rx";
fe273c3e 579 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
916ec47e 580 clock-names = "iis", "i2s_opclk0";
f8bfe2b0
TA		 581 pinctrl-names = "default";
582 pinctrl-0 = <&i2s2_bus>;
4c4c7463
PV		 583 };
584
0b3dc97e
VG		 585 usb@12000000 {
586 compatible = "samsung,exynos5250-dwusb3";
fe273c3e 587 clocks = <&clock CLK_USB3>;
0b3dc97e
VG		 588 clock-names = "usbdrd30";
589 #address-cells = <1>;
590 #size-cells = <1>;
591 ranges;
592
0526f276 593 usbdrd_dwc3: dwc3 {
0b3dc97e
VG		 594 compatible = "synopsys,dwc3";
595 reg = <0x12000000 0x10000>;
596 interrupts = <0 72 0>;
7a4cf0fd
VG		 597 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
598 phy-names = "usb2-phy", "usb3-phy";
896db3b3
VG		 599 };
600 };
601
517083f4
VG		 602 usbdrd_phy: phy@12100000 {
603 compatible = "samsung,exynos5250-usbdrd-phy";
604 reg = <0x12100000 0x100>;
605 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
606 clock-names = "phy", "ref";
607 samsung,pmu-syscon = <&pmu_system_controller>;
608 #phy-cells = <1>;
609 };
610
19fd45bf 611 ehci: usb@12110000 {
13cbd1e3
VG		 612 compatible = "samsung,exynos4210-ehci";
613 reg = <0x12110000 0x100>;
614 interrupts = <0 71 0>;
b3cd7d87 615
fe273c3e 616 clocks = <&clock CLK_USB2>;
b3cd7d87 617 clock-names = "usbhost";
dba2f058
KD		 618 #address-cells = <1>;
619 #size-cells = <0>;
620 port@0 {
621 reg = <0>;
622 phys = <&usb2_phy_gen 1>;
623 };
13cbd1e3
VG		 624 };
625
19fd45bf 626 ohci: usb@12120000 {
7d40d867
VG		 627 compatible = "samsung,exynos4210-ohci";
628 reg = <0x12120000 0x100>;
629 interrupts = <0 71 0>;
b3cd7d87 630
fe273c3e 631 clocks = <&clock CLK_USB2>;
b3cd7d87 632 clock-names = "usbhost";
dba2f058
KD		 633 #address-cells = <1>;
634 #size-cells = <0>;
635 port@0 {
636 reg = <0>;
637 phys = <&usb2_phy_gen 1>;
638 };
7d40d867
VG		 639 };
640
dba2f058
KD		 641 usb2_phy_gen: phy@12130000 {
642 compatible = "samsung,exynos5250-usb2-phy";
643 reg = <0x12130000 0x100>;
644 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
645 clock-names = "phy", "ref";
646 #phy-cells = <1>;
647 samsung,sysreg-phandle = <&sysreg_system_controller>;
648 samsung,pmureg-phandle = <&pmu_system_controller>;
649 };
650
022cf308
LKA		 651 pwm: pwm@12dd0000 {
652 compatible = "samsung,exynos4210-pwm";
653 reg = <0x12dd0000 0x100>;
654 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
655 #pwm-cells = <3>;
fe273c3e 656 clocks = <&clock CLK_PWM>;
022cf308
LKA		 657 clock-names = "timers";
658 };
659
b074abb7
KK		 660 amba {
661 #address-cells = <1>;
662 #size-cells = <1>;
663 compatible = "arm,amba-bus";
664 interrupt-parent = <&gic>;
665 ranges;
666
667 pdma0: pdma@121A0000 {
668 compatible = "arm,pl330", "arm,primecell";
669 reg = <0x121A0000 0x1000>;
670 interrupts = <0 34 0>;
fe273c3e 671 clocks = <&clock CLK_PDMA0>;
2de6847c 672 clock-names = "apb_pclk";
42cf2098
PV		 673 #dma-cells = <1>;
674 #dma-channels = <8>;
675 #dma-requests = <32>;
b074abb7
KK		 676 };
677
678 pdma1: pdma@121B0000 {
679 compatible = "arm,pl330", "arm,primecell";
680 reg = <0x121B0000 0x1000>;
681 interrupts = <0 35 0>;
fe273c3e 682 clocks = <&clock CLK_PDMA1>;
2de6847c 683 clock-names = "apb_pclk";
42cf2098
PV		 684 #dma-cells = <1>;
685 #dma-channels = <8>;
686 #dma-requests = <32>;
b074abb7
KK		 687 };
688
009f7c9f 689 mdma0: mdma@10800000 {
b074abb7
KK		 690 compatible = "arm,pl330", "arm,primecell";
691 reg = <0x10800000 0x1000>;
692 interrupts = <0 33 0>;
fe273c3e 693 clocks = <&clock CLK_MDMA0>;
2de6847c 694 clock-names = "apb_pclk";
42cf2098
PV		 695 #dma-cells = <1>;
696 #dma-channels = <8>;
697 #dma-requests = <1>;
b074abb7
KK		 698 };
699
009f7c9f 700 mdma1: mdma@11C10000 {
b074abb7
KK		 701 compatible = "arm,pl330", "arm,primecell";
702 reg = <0x11C10000 0x1000>;
703 interrupts = <0 124 0>;
fe273c3e 704 clocks = <&clock CLK_MDMA1>;
2de6847c 705 clock-names = "apb_pclk";
42cf2098
PV		 706 #dma-cells = <1>;
707 #dma-channels = <8>;
708 #dma-requests = <1>;
b074abb7
KK		 709 };
710 };
711
c31f566d 712 gsc_0: gsc@13e00000 {
1128658a
SAB		 713 compatible = "samsung,exynos5-gsc";
714 reg = <0x13e00000 0x1000>;
715 interrupts = <0 85 0>;
0da65870 716 power-domains = <&pd_gsc>;
fe273c3e 717 clocks = <&clock CLK_GSCL0>;
2de6847c 718 clock-names = "gscl";
1128658a
SAB		 719 };
720
c31f566d 721 gsc_1: gsc@13e10000 {
1128658a
SAB		 722 compatible = "samsung,exynos5-gsc";
723 reg = <0x13e10000 0x1000>;
724 interrupts = <0 86 0>;
0da65870 725 power-domains = <&pd_gsc>;
fe273c3e 726 clocks = <&clock CLK_GSCL1>;
2de6847c 727 clock-names = "gscl";
1128658a
SAB		 728 };
729
c31f566d 730 gsc_2: gsc@13e20000 {
1128658a
SAB		 731 compatible = "samsung,exynos5-gsc";
732 reg = <0x13e20000 0x1000>;
733 interrupts = <0 87 0>;
0da65870 734 power-domains = <&pd_gsc>;
fe273c3e 735 clocks = <&clock CLK_GSCL2>;
2de6847c 736 clock-names = "gscl";
1128658a
SAB		 737 };
738
c31f566d 739 gsc_3: gsc@13e30000 {
1128658a
SAB		 740 compatible = "samsung,exynos5-gsc";
741 reg = <0x13e30000 0x1000>;
742 interrupts = <0 88 0>;
0da65870 743 power-domains = <&pd_gsc>;
fe273c3e 744 clocks = <&clock CLK_GSCL3>;
2de6847c 745 clock-names = "gscl";
1128658a 746 };
566cf8ee 747
19fd45bf 748 hdmi: hdmi {
0d1fc829 749 compatible = "samsung,exynos4212-hdmi";
101250ce 750 reg = <0x14530000 0x70000>;
2d2c9a8d 751 power-domains = <&pd_disp1>;
566cf8ee 752 interrupts = <0 95 0>;
fe273c3e
AH		 753 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
754 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
755 <&clock CLK_MOUT_HDMI>;
2de6847c 756 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
27c16d19 757 "sclk_hdmiphy", "mout_hdmi";
e54d90ec 758 samsung,syscon-phandle = <&pmu_system_controller>;
566cf8ee 759 };
5af0d8a3
RS		 760
761 mixer {
0d1fc829 762 compatible = "samsung,exynos5250-mixer";
5af0d8a3 763 reg = <0x14450000 0x10000>;
2d2c9a8d 764 power-domains = <&pd_disp1>;
5af0d8a3 765 interrupts = <0 94 0>;
c950ea68
MS		 766 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
767 <&clock CLK_SCLK_HDMI>;
768 clock-names = "mixer", "hdmi", "sclk_hdmi";
5af0d8a3 769 };
ad4aebe1 770
77899d53
VS		 771 dp_phy: video-phy@10040720 {
772 compatible = "samsung,exynos5250-dp-video-phy";
e93e5454 773 samsung,pmu-syscon = <&pmu_system_controller>;
77899d53
VS		 774 #phy-cells = <0>;
775 };
776
19fd45bf 777 dp: dp-controller@145B0000 {
2d2c9a8d 778 power-domains = <&pd_disp1>;
fe273c3e 779 clocks = <&clock CLK_DP>;
0f72a9ec 780 clock-names = "dp";
77899d53
VS		 781 phys = <&dp_phy>;
782 phy-names = "dp";
ad4aebe1 783 };
a7389cb1 784
19fd45bf 785 fimd: fimd@14400000 {
2d2c9a8d 786 power-domains = <&pd_disp1>;
fe273c3e 787 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
a7389cb1
LKA		 788 clock-names = "sclk_fimd", "fimd";
789 };
f408f9db
NKC		 790
791 adc: adc@12D10000 {
792 compatible = "samsung,exynos-adc-v1";
db9bf4d6 793 reg = <0x12D10000 0x100>;
f408f9db 794 interrupts = <0 106 0>;
fe273c3e 795 clocks = <&clock CLK_ADC>;
f408f9db
NKC		 796 clock-names = "adc";
797 #io-channel-cells = <1>;
798 io-channel-ranges;
db9bf4d6 799 samsung,syscon-phandle = <&pmu_system_controller>;
f408f9db
NKC		 800 status = "disabled";
801 };
183af252
NKC		 802
803 sss@10830000 {
804 compatible = "samsung,exynos4210-secss";
805 reg = <0x10830000 0x10000>;
806 interrupts = <0 112 0>;
e06e1067 807 clocks = <&clock CLK_SSS>;
183af252
NKC		 808 clock-names = "secss";
809 };
b074abb7 810};
Linux kernel - Deliverables
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