projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| b074abb7 KK |
1 | /* |
| 2 | * SAMSUNG EXYNOS5250 SoC device tree source | |
| 3 | * | |
| 4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
| 5 | * http://www.samsung.com | |
| 6 | * | |
| 7 | * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. | |
| 8 | * EXYNOS5250 based board files can include this file and provide | |
| 9 | * values for board specfic bindings. | |
| 10 | * | |
| 11 | * Note: This file does not include device nodes for all the controllers in | |
| 12 | * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, | |
| 13 | * additional nodes can be added to this file. | |
| 14 | * | |
| 15 | * This program is free software; you can redistribute it and/or modify | |
| 16 | * it under the terms of the GNU General Public License version 2 as | |
| 17 | * published by the Free Software Foundation. | |
| 18 | */ | |
| 19 | ||
| fe273c3e | 20 | #include <dt-bindings/clock/exynos5250.h> |
| e6c21cba | 21 | #include "exynos5.dtsi" |
| 9843a223 | 22 | #include "exynos4-cpu-thermal.dtsi" |
| 602408e3 | 23 | #include <dt-bindings/clock/exynos-audss-clk.h> |
| b074abb7 KK |
24 | |
| 25 | / { | |
| 8bdb31b4 | 26 | compatible = "samsung,exynos5250", "samsung,exynos5"; |
| b074abb7 | 27 | |
| 79989ba3 TA |
28 | aliases { |
| 29 | spi0 = &spi_0; | |
| 30 | spi1 = &spi_1; | |
| 31 | spi2 = &spi_2; | |
| 1128658a SAB |
32 | gsc0 = &gsc_0; |
| 33 | gsc1 = &gsc_1; | |
| 34 | gsc2 = &gsc_2; | |
| 35 | gsc3 = &gsc_3; | |
| c8149df0 YK |
36 | mshc0 = &mmc_0; |
| 37 | mshc1 = &mmc_1; | |
| 38 | mshc2 = &mmc_2; | |
| 39 | mshc3 = &mmc_3; | |
| b9fa3e7b AK |
40 | i2c0 = &i2c_0; |
| 41 | i2c1 = &i2c_1; | |
| 42 | i2c2 = &i2c_2; | |
| 43 | i2c3 = &i2c_3; | |
| 44 | i2c4 = &i2c_4; | |
| 45 | i2c5 = &i2c_5; | |
| 46 | i2c6 = &i2c_6; | |
| 47 | i2c7 = &i2c_7; | |
| 48 | i2c8 = &i2c_8; | |
| ba0d7ed3 | 49 | i2c9 = &i2c_9; |
| f8bfe2b0 TA |
50 | pinctrl0 = &pinctrl_0; |
| 51 | pinctrl1 = &pinctrl_1; | |
| 52 | pinctrl2 = &pinctrl_2; | |
| 53 | pinctrl3 = &pinctrl_3; | |
| 79989ba3 TA |
54 | }; |
| 55 | ||
| 1897d2f3 CK |
56 | cpus { |
| 57 | #address-cells = <1>; | |
| 58 | #size-cells = <0>; | |
| 59 | ||
| bf4a0bed | 60 | cpu0: cpu@0 { |
| 1897d2f3 CK |
61 | device_type = "cpu"; |
| 62 | compatible = "arm,cortex-a15"; | |
| 63 | reg = <0>; | |
| 0da80563 | 64 | clock-frequency = <1700000000>; |
| 846c5300 TA |
65 | clocks = <&clock CLK_ARM_CLK>; |
| 66 | clock-names = "cpu"; | |
| 67 | clock-latency = <140000>; | |
| 68 | ||
| 69 | operating-points = < | |
| 70 | 1700000 1300000 | |
| 71 | 1600000 1250000 | |
| 72 | 1500000 1225000 | |
| 73 | 1400000 1200000 | |
| 74 | 1300000 1150000 | |
| 75 | 1200000 1125000 | |
| 76 | 1100000 1100000 | |
| 77 | 1000000 1075000 | |
| 78 | 900000 1050000 | |
| 79 | 800000 1025000 | |
| 80 | 700000 1012500 | |
| 81 | 600000 1000000 | |
| 82 | 500000 975000 | |
| 83 | 400000 950000 | |
| 84 | 300000 937500 | |
| 85 | 200000 925000 | |
| 86 | >; | |
| bf4a0bed LM |
87 | cooling-min-level = <15>; |
| 88 | cooling-max-level = <9>; | |
| 89 | #cooling-cells = <2>; /* min followed by max */ | |
| 1897d2f3 CK |
90 | }; |
| 91 | cpu@1 { | |
| 92 | device_type = "cpu"; | |
| 93 | compatible = "arm,cortex-a15"; | |
| 94 | reg = <1>; | |
| 0da80563 | 95 | clock-frequency = <1700000000>; |
| 1897d2f3 | 96 | }; |
| 79989ba3 TA |
97 | }; |
| 98 | ||
| b3205dea SK |
99 | sysram@02020000 { |
| 100 | compatible = "mmio-sram"; | |
| 101 | reg = <0x02020000 0x30000>; | |
| 102 | #address-cells = <1>; | |
| 103 | #size-cells = <1>; | |
| 104 | ranges = <0 0x02020000 0x30000>; | |
| 105 | ||
| 106 | smp-sysram@0 { | |
| 107 | compatible = "samsung,exynos4210-sysram"; | |
| 108 | reg = <0x0 0x1000>; | |
| 109 | }; | |
| 110 | ||
| 111 | smp-sysram@2f000 { | |
| 112 | compatible = "samsung,exynos4210-sysram-ns"; | |
| 113 | reg = <0x2f000 0x1000>; | |
| 114 | }; | |
| 115 | }; | |
| 116 | ||
| c31f566d | 117 | pd_gsc: gsc-power-domain@10044000 { |
| 6f9e95e6 PK |
118 | compatible = "samsung,exynos4210-pd"; |
| 119 | reg = <0x10044000 0x20>; | |
| 0da65870 | 120 | #power-domain-cells = <0>; |
| 6f9e95e6 PK |
121 | }; |
| 122 | ||
| c31f566d | 123 | pd_mfc: mfc-power-domain@10044040 { |
| 6f9e95e6 PK |
124 | compatible = "samsung,exynos4210-pd"; |
| 125 | reg = <0x10044040 0x20>; | |
| 0da65870 | 126 | #power-domain-cells = <0>; |
| 6f9e95e6 PK |
127 | }; |
| 128 | ||
| 2d2c9a8d AH |
129 | pd_disp1: disp1-power-domain@100440A0 { |
| 130 | compatible = "samsung,exynos4210-pd"; | |
| 131 | reg = <0x100440A0 0x20>; | |
| 132 | #power-domain-cells = <0>; | |
| 69636a85 TV |
133 | clocks = <&clock CLK_FIN_PLL>, |
| 134 | <&clock CLK_MOUT_ACLK200_DISP1_SUB>, | |
| 135 | <&clock CLK_MOUT_ACLK300_DISP1_SUB>; | |
| 136 | clock-names = "oscclk", "clk0", "clk1"; | |
| 2d2c9a8d AH |
137 | }; |
| 138 | ||
| c31f566d | 139 | clock: clock-controller@10010000 { |
| d8bafc87 TA |
140 | compatible = "samsung,exynos5250-clock"; |
| 141 | reg = <0x10010000 0x30000>; | |
| 142 | #clock-cells = <1>; | |
| 143 | }; | |
| 144 | ||
| bba23d95 PV |
145 | clock_audss: audss-clock-controller@3810000 { |
| 146 | compatible = "samsung,exynos5250-audss-clock"; | |
| 147 | reg = <0x03810000 0x0C>; | |
| 148 | #clock-cells = <1>; | |
| fe273c3e AH |
149 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, |
| 150 | <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; | |
| c08ceea3 | 151 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; |
| bba23d95 PV |
152 | }; |
| 153 | ||
| 2b7da988 AG |
154 | timer { |
| 155 | compatible = "arm,armv7-timer"; | |
| 156 | interrupts = <1 13 0xf08>, | |
| 157 | <1 14 0xf08>, | |
| 158 | <1 11 0xf08>, | |
| 159 | <1 10 0xf08>; | |
| 4d594dd3 YK |
160 | /* Unfortunately we need this since some versions of U-Boot |
| 161 | * on Exynos don't set the CNTFRQ register, so we need the | |
| 162 | * value from DT. | |
| 163 | */ | |
| 164 | clock-frequency = <24000000>; | |
| b074abb7 KK |
165 | }; |
| 166 | ||
| bbd9700a TA |
167 | mct@101C0000 { |
| 168 | compatible = "samsung,exynos4210-mct"; | |
| 169 | reg = <0x101C0000 0x800>; | |
| 170 | interrupt-controller; | |
| f27b9075 | 171 | #interrupt-cells = <2>; |
| bbd9700a TA |
172 | interrupt-parent = <&mct_map>; |
| 173 | interrupts = <0 0>, <1 0>, <2 0>, <3 0>, | |
| 174 | <4 0>, <5 0>; | |
| fe273c3e | 175 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
| 2de6847c | 176 | clock-names = "fin_pll", "mct"; |
| bbd9700a TA |
177 | |
| 178 | mct_map: mct-map { | |
| 179 | #interrupt-cells = <2>; | |
| 180 | #address-cells = <0>; | |
| 181 | #size-cells = <0>; | |
| 182 | interrupt-map = <0x0 0 &combiner 23 3>, | |
| 183 | <0x1 0 &combiner 23 4>, | |
| 184 | <0x2 0 &combiner 25 2>, | |
| 185 | <0x3 0 &combiner 25 3>, | |
| 186 | <0x4 0 &gic 0 120 0>, | |
| 187 | <0x5 0 &gic 0 121 0>; | |
| 188 | }; | |
| 189 | }; | |
| 190 | ||
| 4f801e59 CP |
191 | pmu { |
| 192 | compatible = "arm,cortex-a15-pmu"; | |
| 193 | interrupt-parent = <&combiner>; | |
| 194 | interrupts = <1 2>, <22 4>; | |
| 195 | }; | |
| 196 | ||
| f8bfe2b0 TA |
197 | pinctrl_0: pinctrl@11400000 { |
| 198 | compatible = "samsung,exynos5250-pinctrl"; | |
| 199 | reg = <0x11400000 0x1000>; | |
| 200 | interrupts = <0 46 0>; | |
| 201 | ||
| 202 | wakup_eint: wakeup-interrupt-controller { | |
| 203 | compatible = "samsung,exynos4210-wakeup-eint"; | |
| 204 | interrupt-parent = <&gic>; | |
| 205 | interrupts = <0 32 0>; | |
| 206 | }; | |
| 207 | }; | |
| 208 | ||
| 209 | pinctrl_1: pinctrl@13400000 { | |
| 210 | compatible = "samsung,exynos5250-pinctrl"; | |
| 211 | reg = <0x13400000 0x1000>; | |
| 212 | interrupts = <0 45 0>; | |
| 213 | }; | |
| 214 | ||
| 215 | pinctrl_2: pinctrl@10d10000 { | |
| 216 | compatible = "samsung,exynos5250-pinctrl"; | |
| 217 | reg = <0x10d10000 0x1000>; | |
| 218 | interrupts = <0 50 0>; | |
| 219 | }; | |
| 220 | ||
| 0abb6aea | 221 | pinctrl_3: pinctrl@03860000 { |
| f8bfe2b0 | 222 | compatible = "samsung,exynos5250-pinctrl"; |
| 0abb6aea | 223 | reg = <0x03860000 0x1000>; |
| f8bfe2b0 TA |
224 | interrupts = <0 47 0>; |
| 225 | }; | |
| 226 | ||
| c680036a LKA |
227 | pmu_system_controller: system-controller@10040000 { |
| 228 | compatible = "samsung,exynos5250-pmu", "syscon"; | |
| 229 | reg = <0x10040000 0x5000>; | |
| d19bb397 TF |
230 | clock-names = "clkout16"; |
| 231 | clocks = <&clock CLK_FIN_PLL>; | |
| 232 | #clock-cells = <1>; | |
| 8b283c02 MZ |
233 | interrupt-controller; |
| 234 | #interrupt-cells = <3>; | |
| 235 | interrupt-parent = <&gic>; | |
| c680036a LKA |
236 | }; |
| 237 | ||
| dfbbdbf4 VG |
238 | sysreg_system_controller: syscon@10050000 { |
| 239 | compatible = "samsung,exynos5-sysreg", "syscon"; | |
| 240 | reg = <0x10050000 0x5000>; | |
| 241 | }; | |
| 242 | ||
| 1d287620 LKA |
243 | watchdog@101D0000 { |
| 244 | compatible = "samsung,exynos5250-wdt"; | |
| 245 | reg = <0x101D0000 0x100>; | |
| 246 | interrupts = <0 42 0>; | |
| fe273c3e | 247 | clocks = <&clock CLK_WDT>; |
| 2de6847c | 248 | clock-names = "watchdog"; |
| 1d287620 | 249 | samsung,syscon-phandle = <&pmu_system_controller>; |
| b074abb7 KK |
250 | }; |
| 251 | ||
| 21aa5217 SK |
252 | g2d@10850000 { |
| 253 | compatible = "samsung,exynos5250-g2d"; | |
| 254 | reg = <0x10850000 0x1000>; | |
| 255 | interrupts = <0 91 0>; | |
| fe273c3e | 256 | clocks = <&clock CLK_G2D>; |
| 21aa5217 | 257 | clock-names = "fimg2d"; |
| 6cbfdd73 | 258 | iommus = <&sysmmu_g2d>; |
| 21aa5217 SK |
259 | }; |
| 260 | ||
| 19fd45bf | 261 | mfc: codec@11000000 { |
| 2eae613b AK |
262 | compatible = "samsung,mfc-v6"; |
| 263 | reg = <0x11000000 0x10000>; | |
| 264 | interrupts = <0 96 0>; | |
| 0da65870 | 265 | power-domains = <&pd_mfc>; |
| fe273c3e | 266 | clocks = <&clock CLK_MFC>; |
| 8b6bea33 | 267 | clock-names = "mfc"; |
| 6cbfdd73 MS |
268 | iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; |
| 269 | iommu-names = "left", "right"; | |
| 2eae613b AK |
270 | }; |
| 271 | ||
| d35e20d9 MS |
272 | rotator: rotator@11C00000 { |
| 273 | compatible = "samsung,exynos5250-rotator"; | |
| 274 | reg = <0x11C00000 0x64>; | |
| 275 | interrupts = <0 84 0>; | |
| 276 | clocks = <&clock CLK_ROTATOR>; | |
| 277 | clock-names = "rotator"; | |
| 278 | iommus = <&sysmmu_rotator>; | |
| 279 | }; | |
| 280 | ||
| 9843a223 | 281 | tmu: tmu@10060000 { |
| ef405e04 ADK |
282 | compatible = "samsung,exynos5250-tmu"; |
| 283 | reg = <0x10060000 0x100>; | |
| 284 | interrupts = <0 65 0>; | |
| fe273c3e | 285 | clocks = <&clock CLK_TMU>; |
| 2de6847c | 286 | clock-names = "tmu_apbif"; |
| 9843a223 | 287 | #include "exynos4412-tmu-sensor-conf.dtsi" |
| ef405e04 ADK |
288 | }; |
| 289 | ||
| bf4a0bed LM |
290 | thermal-zones { |
| 291 | cpu_thermal: cpu-thermal { | |
| 9843a223 LM |
292 | polling-delay-passive = <0>; |
| 293 | polling-delay = <0>; | |
| 294 | thermal-sensors = <&tmu 0>; | |
| 295 | ||
| bf4a0bed LM |
296 | cooling-maps { |
| 297 | map0 { | |
| 298 | /* Corresponds to 800MHz at freq_table */ | |
| 299 | cooling-device = <&cpu0 9 9>; | |
| 300 | }; | |
| 301 | map1 { | |
| 302 | /* Corresponds to 200MHz at freq_table */ | |
| 303 | cooling-device = <&cpu0 15 15>; | |
| 304 | }; | |
| 305 | }; | |
| 306 | }; | |
| 307 | }; | |
| 308 | ||
| 19fd45bf | 309 | sata: sata@122F0000 { |
| ba0d7ed3 YK |
310 | compatible = "snps,dwc-ahci"; |
| 311 | samsung,sata-freq = <66>; | |
| c47d244a VA |
312 | reg = <0x122F0000 0x1ff>; |
| 313 | interrupts = <0 115 0>; | |
| fe273c3e | 314 | clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; |
| 2de6847c | 315 | clock-names = "sata", "sclk_sata"; |
| ba0d7ed3 YK |
316 | phys = <&sata_phy>; |
| 317 | phy-names = "sata-phy"; | |
| 318 | status = "disabled"; | |
| c47d244a VA |
319 | }; |
| 320 | ||
| ba0d7ed3 YK |
321 | sata_phy: sata-phy@12170000 { |
| 322 | compatible = "samsung,exynos5250-sata-phy"; | |
| c47d244a | 323 | reg = <0x12170000 0x1ff>; |
| e06e1067 | 324 | clocks = <&clock CLK_SATA_PHYCTRL>; |
| ba0d7ed3 YK |
325 | clock-names = "sata_phyctrl"; |
| 326 | #phy-cells = <0>; | |
| 327 | samsung,syscon-phandle = <&pmu_system_controller>; | |
| 328 | status = "disabled"; | |
| c47d244a VA |
329 | }; |
| 330 | ||
| b9fa3e7b | 331 | i2c_0: i2c@12C60000 { |
| b074abb7 KK |
332 | compatible = "samsung,s3c2440-i2c"; |
| 333 | reg = <0x12C60000 0x100>; | |
| 334 | interrupts = <0 56 0>; | |
| 009f7c9f TA |
335 | #address-cells = <1>; |
| 336 | #size-cells = <0>; | |
| fe273c3e | 337 | clocks = <&clock CLK_I2C0>; |
| 2de6847c | 338 | clock-names = "i2c"; |
| f8bfe2b0 TA |
339 | pinctrl-names = "default"; |
| 340 | pinctrl-0 = <&i2c0_bus>; | |
| 1888eb75 | 341 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
| 6ad8ebff | 342 | status = "disabled"; |
| b074abb7 KK |
343 | }; |
| 344 | ||
| b9fa3e7b | 345 | i2c_1: i2c@12C70000 { |
| b074abb7 KK |
346 | compatible = "samsung,s3c2440-i2c"; |
| 347 | reg = <0x12C70000 0x100>; | |
| 348 | interrupts = <0 57 0>; | |
| 009f7c9f TA |
349 | #address-cells = <1>; |
| 350 | #size-cells = <0>; | |
| fe273c3e | 351 | clocks = <&clock CLK_I2C1>; |
| 2de6847c | 352 | clock-names = "i2c"; |
| f8bfe2b0 TA |
353 | pinctrl-names = "default"; |
| 354 | pinctrl-0 = <&i2c1_bus>; | |
| 1888eb75 | 355 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
| 6ad8ebff | 356 | status = "disabled"; |
| b074abb7 KK |
357 | }; |
| 358 | ||
| b9fa3e7b | 359 | i2c_2: i2c@12C80000 { |
| b074abb7 KK |
360 | compatible = "samsung,s3c2440-i2c"; |
| 361 | reg = <0x12C80000 0x100>; | |
| 362 | interrupts = <0 58 0>; | |
| 009f7c9f TA |
363 | #address-cells = <1>; |
| 364 | #size-cells = <0>; | |
| fe273c3e | 365 | clocks = <&clock CLK_I2C2>; |
| 2de6847c | 366 | clock-names = "i2c"; |
| f8bfe2b0 TA |
367 | pinctrl-names = "default"; |
| 368 | pinctrl-0 = <&i2c2_bus>; | |
| 1888eb75 | 369 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
| 6ad8ebff | 370 | status = "disabled"; |
| b074abb7 KK |
371 | }; |
| 372 | ||
| b9fa3e7b | 373 | i2c_3: i2c@12C90000 { |
| b074abb7 KK |
374 | compatible = "samsung,s3c2440-i2c"; |
| 375 | reg = <0x12C90000 0x100>; | |
| 376 | interrupts = <0 59 0>; | |
| 009f7c9f TA |
377 | #address-cells = <1>; |
| 378 | #size-cells = <0>; | |
| fe273c3e | 379 | clocks = <&clock CLK_I2C3>; |
| 2de6847c | 380 | clock-names = "i2c"; |
| f8bfe2b0 TA |
381 | pinctrl-names = "default"; |
| 382 | pinctrl-0 = <&i2c3_bus>; | |
| 1888eb75 | 383 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
| 6ad8ebff | 384 | status = "disabled"; |
| b074abb7 KK |
385 | }; |
| 386 | ||
| b9fa3e7b | 387 | i2c_4: i2c@12CA0000 { |
| b074abb7 KK |
388 | compatible = "samsung,s3c2440-i2c"; |
| 389 | reg = <0x12CA0000 0x100>; | |
| 390 | interrupts = <0 60 0>; | |
| 009f7c9f TA |
391 | #address-cells = <1>; |
| 392 | #size-cells = <0>; | |
| fe273c3e | 393 | clocks = <&clock CLK_I2C4>; |
| 2de6847c | 394 | clock-names = "i2c"; |
| f8bfe2b0 TA |
395 | pinctrl-names = "default"; |
| 396 | pinctrl-0 = <&i2c4_bus>; | |
| 6ad8ebff | 397 | status = "disabled"; |
| b074abb7 KK |
398 | }; |
| 399 | ||
| b9fa3e7b | 400 | i2c_5: i2c@12CB0000 { |
| b074abb7 KK |
401 | compatible = "samsung,s3c2440-i2c"; |
| 402 | reg = <0x12CB0000 0x100>; | |
| 403 | interrupts = <0 61 0>; | |
| 009f7c9f TA |
404 | #address-cells = <1>; |
| 405 | #size-cells = <0>; | |
| fe273c3e | 406 | clocks = <&clock CLK_I2C5>; |
| 2de6847c | 407 | clock-names = "i2c"; |
| f8bfe2b0 TA |
408 | pinctrl-names = "default"; |
| 409 | pinctrl-0 = <&i2c5_bus>; | |
| 6ad8ebff | 410 | status = "disabled"; |
| b074abb7 KK |
411 | }; |
| 412 | ||
| b9fa3e7b | 413 | i2c_6: i2c@12CC0000 { |
| b074abb7 KK |
414 | compatible = "samsung,s3c2440-i2c"; |
| 415 | reg = <0x12CC0000 0x100>; | |
| 416 | interrupts = <0 62 0>; | |
| 009f7c9f TA |
417 | #address-cells = <1>; |
| 418 | #size-cells = <0>; | |
| fe273c3e | 419 | clocks = <&clock CLK_I2C6>; |
| 2de6847c | 420 | clock-names = "i2c"; |
| f8bfe2b0 TA |
421 | pinctrl-names = "default"; |
| 422 | pinctrl-0 = <&i2c6_bus>; | |
| 6ad8ebff | 423 | status = "disabled"; |
| b074abb7 KK |
424 | }; |
| 425 | ||
| b9fa3e7b | 426 | i2c_7: i2c@12CD0000 { |
| b074abb7 KK |
427 | compatible = "samsung,s3c2440-i2c"; |
| 428 | reg = <0x12CD0000 0x100>; | |
| 429 | interrupts = <0 63 0>; | |
| 009f7c9f TA |
430 | #address-cells = <1>; |
| 431 | #size-cells = <0>; | |
| fe273c3e | 432 | clocks = <&clock CLK_I2C7>; |
| 2de6847c | 433 | clock-names = "i2c"; |
| f8bfe2b0 TA |
434 | pinctrl-names = "default"; |
| 435 | pinctrl-0 = <&i2c7_bus>; | |
| 6ad8ebff | 436 | status = "disabled"; |
| 3e3e9ce4 RS |
437 | }; |
| 438 | ||
| b9fa3e7b | 439 | i2c_8: i2c@12CE0000 { |
| 3e3e9ce4 RS |
440 | compatible = "samsung,s3c2440-hdmiphy-i2c"; |
| 441 | reg = <0x12CE0000 0x1000>; | |
| 442 | interrupts = <0 64 0>; | |
| 443 | #address-cells = <1>; | |
| 444 | #size-cells = <0>; | |
| fe273c3e | 445 | clocks = <&clock CLK_I2C_HDMI>; |
| 2de6847c | 446 | clock-names = "i2c"; |
| 6ad8ebff | 447 | status = "disabled"; |
| 24025f6f OJ |
448 | }; |
| 449 | ||
| ba0d7ed3 | 450 | i2c_9: i2c@121D0000 { |
| c47d244a VA |
451 | compatible = "samsung,exynos5-sata-phy-i2c"; |
| 452 | reg = <0x121D0000 0x100>; | |
| 453 | #address-cells = <1>; | |
| 454 | #size-cells = <0>; | |
| fe273c3e | 455 | clocks = <&clock CLK_SATA_PHYI2C>; |
| 2de6847c | 456 | clock-names = "i2c"; |
| 6ad8ebff | 457 | status = "disabled"; |
| b074abb7 KK |
458 | }; |
| 459 | ||
| 79989ba3 TA |
460 | spi_0: spi@12d20000 { |
| 461 | compatible = "samsung,exynos4210-spi"; | |
| fae93f7c | 462 | status = "disabled"; |
| 79989ba3 TA |
463 | reg = <0x12d20000 0x100>; |
| 464 | interrupts = <0 66 0>; | |
| a4a8a9d3 PV |
465 | dmas = <&pdma0 5 |
| 466 | &pdma0 4>; | |
| 467 | dma-names = "tx", "rx"; | |
| 79989ba3 TA |
468 | #address-cells = <1>; |
| 469 | #size-cells = <0>; | |
| fe273c3e | 470 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; |
| 2de6847c | 471 | clock-names = "spi", "spi_busclk0"; |
| f8bfe2b0 TA |
472 | pinctrl-names = "default"; |
| 473 | pinctrl-0 = <&spi0_bus>; | |
| 79989ba3 TA |
474 | }; |
| 475 | ||
| 476 | spi_1: spi@12d30000 { | |
| 477 | compatible = "samsung,exynos4210-spi"; | |
| fae93f7c | 478 | status = "disabled"; |
| 79989ba3 TA |
479 | reg = <0x12d30000 0x100>; |
| 480 | interrupts = <0 67 0>; | |
| a4a8a9d3 PV |
481 | dmas = <&pdma1 5 |
| 482 | &pdma1 4>; | |
| 483 | dma-names = "tx", "rx"; | |
| 79989ba3 TA |
484 | #address-cells = <1>; |
| 485 | #size-cells = <0>; | |
| fe273c3e | 486 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; |
| 2de6847c | 487 | clock-names = "spi", "spi_busclk0"; |
| f8bfe2b0 TA |
488 | pinctrl-names = "default"; |
| 489 | pinctrl-0 = <&spi1_bus>; | |
| 79989ba3 TA |
490 | }; |
| 491 | ||
| 492 | spi_2: spi@12d40000 { | |
| 493 | compatible = "samsung,exynos4210-spi"; | |
| fae93f7c | 494 | status = "disabled"; |
| 79989ba3 TA |
495 | reg = <0x12d40000 0x100>; |
| 496 | interrupts = <0 68 0>; | |
| a4a8a9d3 PV |
497 | dmas = <&pdma0 7 |
| 498 | &pdma0 6>; | |
| 499 | dma-names = "tx", "rx"; | |
| 79989ba3 TA |
500 | #address-cells = <1>; |
| 501 | #size-cells = <0>; | |
| fe273c3e | 502 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; |
| 2de6847c | 503 | clock-names = "spi", "spi_busclk0"; |
| f8bfe2b0 TA |
504 | pinctrl-names = "default"; |
| 505 | pinctrl-0 = <&spi2_bus>; | |
| 79989ba3 TA |
506 | }; |
| 507 | ||
| c8149df0 | 508 | mmc_0: mmc@12200000 { |
| 906fd84e YK |
509 | compatible = "samsung,exynos5250-dw-mshc"; |
| 510 | interrupts = <0 75 0>; | |
| 511 | #address-cells = <1>; | |
| 512 | #size-cells = <0>; | |
| 84bd48a0 | 513 | reg = <0x12200000 0x1000>; |
| fe273c3e | 514 | clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; |
| 2de6847c | 515 | clock-names = "biu", "ciu"; |
| 46285a90 | 516 | fifo-depth = <0x80>; |
| e908d5c5 | 517 | status = "disabled"; |
| 84bd48a0 TA |
518 | }; |
| 519 | ||
| c8149df0 | 520 | mmc_1: mmc@12210000 { |
| 906fd84e YK |
521 | compatible = "samsung,exynos5250-dw-mshc"; |
| 522 | interrupts = <0 76 0>; | |
| 523 | #address-cells = <1>; | |
| 524 | #size-cells = <0>; | |
| 84bd48a0 | 525 | reg = <0x12210000 0x1000>; |
| fe273c3e | 526 | clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; |
| 2de6847c | 527 | clock-names = "biu", "ciu"; |
| 46285a90 | 528 | fifo-depth = <0x80>; |
| e908d5c5 | 529 | status = "disabled"; |
| 84bd48a0 TA |
530 | }; |
| 531 | ||
| c8149df0 | 532 | mmc_2: mmc@12220000 { |
| 906fd84e YK |
533 | compatible = "samsung,exynos5250-dw-mshc"; |
| 534 | interrupts = <0 77 0>; | |
| 535 | #address-cells = <1>; | |
| 536 | #size-cells = <0>; | |
| 84bd48a0 | 537 | reg = <0x12220000 0x1000>; |
| fe273c3e | 538 | clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; |
| 2de6847c | 539 | clock-names = "biu", "ciu"; |
| 46285a90 | 540 | fifo-depth = <0x80>; |
| e908d5c5 | 541 | status = "disabled"; |
| 84bd48a0 TA |
542 | }; |
| 543 | ||
| c8149df0 | 544 | mmc_3: mmc@12230000 { |
| 84bd48a0 TA |
545 | compatible = "samsung,exynos5250-dw-mshc"; |
| 546 | reg = <0x12230000 0x1000>; | |
| 547 | interrupts = <0 78 0>; | |
| 548 | #address-cells = <1>; | |
| 549 | #size-cells = <0>; | |
| fe273c3e | 550 | clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; |
| 2de6847c | 551 | clock-names = "biu", "ciu"; |
| 46285a90 | 552 | fifo-depth = <0x80>; |
| e908d5c5 | 553 | status = "disabled"; |
| 84bd48a0 TA |
554 | }; |
| 555 | ||
| 28a48058 | 556 | i2s0: i2s@03830000 { |
| 64183656 | 557 | compatible = "samsung,s5pv210-i2s"; |
| 328aee4b | 558 | status = "disabled"; |
| a0b5f81e | 559 | reg = <0x03830000 0x100>; |
| 4c4c7463 PV |
560 | dmas = <&pdma0 10 |
| 561 | &pdma0 9 | |
| 562 | &pdma0 8>; | |
| 563 | dma-names = "tx", "rx", "tx-sec"; | |
| 916ec47e PV |
564 | clocks = <&clock_audss EXYNOS_I2S_BUS>, |
| 565 | <&clock_audss EXYNOS_I2S_BUS>, | |
| 566 | <&clock_audss EXYNOS_SCLK_I2S>; | |
| 567 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
| a0b5f81e | 568 | samsung,idma-addr = <0x03000000>; |
| f8bfe2b0 TA |
569 | pinctrl-names = "default"; |
| 570 | pinctrl-0 = <&i2s0_bus>; | |
| 4c4c7463 PV |
571 | }; |
| 572 | ||
| 28a48058 | 573 | i2s1: i2s@12D60000 { |
| 64183656 | 574 | compatible = "samsung,s3c6410-i2s"; |
| 328aee4b | 575 | status = "disabled"; |
| a0b5f81e MB |
576 | reg = <0x12D60000 0x100>; |
| 577 | dmas = <&pdma1 12 | |
| 578 | &pdma1 11>; | |
| 579 | dma-names = "tx", "rx"; | |
| fe273c3e | 580 | clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; |
| 916ec47e | 581 | clock-names = "iis", "i2s_opclk0"; |
| f8bfe2b0 TA |
582 | pinctrl-names = "default"; |
| 583 | pinctrl-0 = <&i2s1_bus>; | |
| 4c4c7463 PV |
584 | }; |
| 585 | ||
| 28a48058 | 586 | i2s2: i2s@12D70000 { |
| 64183656 | 587 | compatible = "samsung,s3c6410-i2s"; |
| 328aee4b | 588 | status = "disabled"; |
| a0b5f81e MB |
589 | reg = <0x12D70000 0x100>; |
| 590 | dmas = <&pdma0 12 | |
| 591 | &pdma0 11>; | |
| 592 | dma-names = "tx", "rx"; | |
| fe273c3e | 593 | clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; |
| 916ec47e | 594 | clock-names = "iis", "i2s_opclk0"; |
| f8bfe2b0 TA |
595 | pinctrl-names = "default"; |
| 596 | pinctrl-0 = <&i2s2_bus>; | |
| 4c4c7463 PV |
597 | }; |
| 598 | ||
| 0b3dc97e VG |
599 | usb@12000000 { |
| 600 | compatible = "samsung,exynos5250-dwusb3"; | |
| fe273c3e | 601 | clocks = <&clock CLK_USB3>; |
| 0b3dc97e VG |
602 | clock-names = "usbdrd30"; |
| 603 | #address-cells = <1>; | |
| 604 | #size-cells = <1>; | |
| 605 | ranges; | |
| 606 | ||
| 0526f276 | 607 | usbdrd_dwc3: dwc3 { |
| 0b3dc97e VG |
608 | compatible = "synopsys,dwc3"; |
| 609 | reg = <0x12000000 0x10000>; | |
| 610 | interrupts = <0 72 0>; | |
| 7a4cf0fd VG |
611 | phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; |
| 612 | phy-names = "usb2-phy", "usb3-phy"; | |
| 896db3b3 VG |
613 | }; |
| 614 | }; | |
| 615 | ||
| 517083f4 VG |
616 | usbdrd_phy: phy@12100000 { |
| 617 | compatible = "samsung,exynos5250-usbdrd-phy"; | |
| 618 | reg = <0x12100000 0x100>; | |
| 619 | clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; | |
| 620 | clock-names = "phy", "ref"; | |
| 621 | samsung,pmu-syscon = <&pmu_system_controller>; | |
| 622 | #phy-cells = <1>; | |
| 623 | }; | |
| 624 | ||
| 19fd45bf | 625 | ehci: usb@12110000 { |
| 13cbd1e3 VG |
626 | compatible = "samsung,exynos4210-ehci"; |
| 627 | reg = <0x12110000 0x100>; | |
| 628 | interrupts = <0 71 0>; | |
| b3cd7d87 | 629 | |
| fe273c3e | 630 | clocks = <&clock CLK_USB2>; |
| b3cd7d87 | 631 | clock-names = "usbhost"; |
| dba2f058 KD |
632 | #address-cells = <1>; |
| 633 | #size-cells = <0>; | |
| 634 | port@0 { | |
| 635 | reg = <0>; | |
| 636 | phys = <&usb2_phy_gen 1>; | |
| 637 | }; | |
| 13cbd1e3 VG |
638 | }; |
| 639 | ||
| 19fd45bf | 640 | ohci: usb@12120000 { |
| 7d40d867 VG |
641 | compatible = "samsung,exynos4210-ohci"; |
| 642 | reg = <0x12120000 0x100>; | |
| 643 | interrupts = <0 71 0>; | |
| b3cd7d87 | 644 | |
| fe273c3e | 645 | clocks = <&clock CLK_USB2>; |
| b3cd7d87 | 646 | clock-names = "usbhost"; |
| dba2f058 KD |
647 | #address-cells = <1>; |
| 648 | #size-cells = <0>; | |
| 649 | port@0 { | |
| 650 | reg = <0>; | |
| 651 | phys = <&usb2_phy_gen 1>; | |
| 652 | }; | |
| 7d40d867 VG |
653 | }; |
| 654 | ||
| dba2f058 KD |
655 | usb2_phy_gen: phy@12130000 { |
| 656 | compatible = "samsung,exynos5250-usb2-phy"; | |
| 657 | reg = <0x12130000 0x100>; | |
| 658 | clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; | |
| 659 | clock-names = "phy", "ref"; | |
| 660 | #phy-cells = <1>; | |
| 661 | samsung,sysreg-phandle = <&sysreg_system_controller>; | |
| 662 | samsung,pmureg-phandle = <&pmu_system_controller>; | |
| 663 | }; | |
| 664 | ||
| 022cf308 LKA |
665 | pwm: pwm@12dd0000 { |
| 666 | compatible = "samsung,exynos4210-pwm"; | |
| 667 | reg = <0x12dd0000 0x100>; | |
| 668 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; | |
| 669 | #pwm-cells = <3>; | |
| fe273c3e | 670 | clocks = <&clock CLK_PWM>; |
| 022cf308 LKA |
671 | clock-names = "timers"; |
| 672 | }; | |
| 673 | ||
| b074abb7 KK |
674 | amba { |
| 675 | #address-cells = <1>; | |
| 676 | #size-cells = <1>; | |
| 2ef7d5f3 | 677 | compatible = "simple-bus"; |
| b074abb7 KK |
678 | interrupt-parent = <&gic>; |
| 679 | ranges; | |
| 680 | ||
| 681 | pdma0: pdma@121A0000 { | |
| 682 | compatible = "arm,pl330", "arm,primecell"; | |
| 683 | reg = <0x121A0000 0x1000>; | |
| 684 | interrupts = <0 34 0>; | |
| fe273c3e | 685 | clocks = <&clock CLK_PDMA0>; |
| 2de6847c | 686 | clock-names = "apb_pclk"; |
| 42cf2098 PV |
687 | #dma-cells = <1>; |
| 688 | #dma-channels = <8>; | |
| 689 | #dma-requests = <32>; | |
| b074abb7 KK |
690 | }; |
| 691 | ||
| 692 | pdma1: pdma@121B0000 { | |
| 693 | compatible = "arm,pl330", "arm,primecell"; | |
| 694 | reg = <0x121B0000 0x1000>; | |
| 695 | interrupts = <0 35 0>; | |
| fe273c3e | 696 | clocks = <&clock CLK_PDMA1>; |
| 2de6847c | 697 | clock-names = "apb_pclk"; |
| 42cf2098 PV |
698 | #dma-cells = <1>; |
| 699 | #dma-channels = <8>; | |
| 700 | #dma-requests = <32>; | |
| b074abb7 KK |
701 | }; |
| 702 | ||
| 009f7c9f | 703 | mdma0: mdma@10800000 { |
| b074abb7 KK |
704 | compatible = "arm,pl330", "arm,primecell"; |
| 705 | reg = <0x10800000 0x1000>; | |
| 706 | interrupts = <0 33 0>; | |
| fe273c3e | 707 | clocks = <&clock CLK_MDMA0>; |
| 2de6847c | 708 | clock-names = "apb_pclk"; |
| 42cf2098 PV |
709 | #dma-cells = <1>; |
| 710 | #dma-channels = <8>; | |
| 711 | #dma-requests = <1>; | |
| b074abb7 KK |
712 | }; |
| 713 | ||
| 009f7c9f | 714 | mdma1: mdma@11C10000 { |
| b074abb7 KK |
715 | compatible = "arm,pl330", "arm,primecell"; |
| 716 | reg = <0x11C10000 0x1000>; | |
| 717 | interrupts = <0 124 0>; | |
| fe273c3e | 718 | clocks = <&clock CLK_MDMA1>; |
| 2de6847c | 719 | clock-names = "apb_pclk"; |
| 42cf2098 PV |
720 | #dma-cells = <1>; |
| 721 | #dma-channels = <8>; | |
| 722 | #dma-requests = <1>; | |
| b074abb7 KK |
723 | }; |
| 724 | }; | |
| 725 | ||
| c31f566d | 726 | gsc_0: gsc@13e00000 { |
| 1128658a SAB |
727 | compatible = "samsung,exynos5-gsc"; |
| 728 | reg = <0x13e00000 0x1000>; | |
| 729 | interrupts = <0 85 0>; | |
| 0da65870 | 730 | power-domains = <&pd_gsc>; |
| fe273c3e | 731 | clocks = <&clock CLK_GSCL0>; |
| 2de6847c | 732 | clock-names = "gscl"; |
| 6cbfdd73 | 733 | iommu = <&sysmmu_gsc0>; |
| 1128658a SAB |
734 | }; |
| 735 | ||
| c31f566d | 736 | gsc_1: gsc@13e10000 { |
| 1128658a SAB |
737 | compatible = "samsung,exynos5-gsc"; |
| 738 | reg = <0x13e10000 0x1000>; | |
| 739 | interrupts = <0 86 0>; | |
| 0da65870 | 740 | power-domains = <&pd_gsc>; |
| fe273c3e | 741 | clocks = <&clock CLK_GSCL1>; |
| 2de6847c | 742 | clock-names = "gscl"; |
| 6cbfdd73 | 743 | iommu = <&sysmmu_gsc1>; |
| 1128658a SAB |
744 | }; |
| 745 | ||
| c31f566d | 746 | gsc_2: gsc@13e20000 { |
| 1128658a SAB |
747 | compatible = "samsung,exynos5-gsc"; |
| 748 | reg = <0x13e20000 0x1000>; | |
| 749 | interrupts = <0 87 0>; | |
| 0da65870 | 750 | power-domains = <&pd_gsc>; |
| fe273c3e | 751 | clocks = <&clock CLK_GSCL2>; |
| 2de6847c | 752 | clock-names = "gscl"; |
| 6cbfdd73 | 753 | iommu = <&sysmmu_gsc2>; |
| 1128658a SAB |
754 | }; |
| 755 | ||
| c31f566d | 756 | gsc_3: gsc@13e30000 { |
| 1128658a SAB |
757 | compatible = "samsung,exynos5-gsc"; |
| 758 | reg = <0x13e30000 0x1000>; | |
| 759 | interrupts = <0 88 0>; | |
| 0da65870 | 760 | power-domains = <&pd_gsc>; |
| fe273c3e | 761 | clocks = <&clock CLK_GSCL3>; |
| 2de6847c | 762 | clock-names = "gscl"; |
| 6cbfdd73 | 763 | iommu = <&sysmmu_gsc3>; |
| 1128658a | 764 | }; |
| 566cf8ee | 765 | |
| 19fd45bf | 766 | hdmi: hdmi { |
| 0d1fc829 | 767 | compatible = "samsung,exynos4212-hdmi"; |
| 101250ce | 768 | reg = <0x14530000 0x70000>; |
| 2d2c9a8d | 769 | power-domains = <&pd_disp1>; |
| 566cf8ee | 770 | interrupts = <0 95 0>; |
| fe273c3e AH |
771 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, |
| 772 | <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, | |
| 773 | <&clock CLK_MOUT_HDMI>; | |
| 2de6847c | 774 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", |
| 27c16d19 | 775 | "sclk_hdmiphy", "mout_hdmi"; |
| e54d90ec | 776 | samsung,syscon-phandle = <&pmu_system_controller>; |
| 566cf8ee | 777 | }; |
| 5af0d8a3 RS |
778 | |
| 779 | mixer { | |
| 0d1fc829 | 780 | compatible = "samsung,exynos5250-mixer"; |
| 5af0d8a3 | 781 | reg = <0x14450000 0x10000>; |
| 2d2c9a8d | 782 | power-domains = <&pd_disp1>; |
| 5af0d8a3 | 783 | interrupts = <0 94 0>; |
| c950ea68 MS |
784 | clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, |
| 785 | <&clock CLK_SCLK_HDMI>; | |
| 786 | clock-names = "mixer", "hdmi", "sclk_hdmi"; | |
| 6cbfdd73 | 787 | iommus = <&sysmmu_tv>; |
| 5af0d8a3 | 788 | }; |
| ad4aebe1 | 789 | |
| 77899d53 VS |
790 | dp_phy: video-phy@10040720 { |
| 791 | compatible = "samsung,exynos5250-dp-video-phy"; | |
| e93e5454 | 792 | samsung,pmu-syscon = <&pmu_system_controller>; |
| 77899d53 VS |
793 | #phy-cells = <0>; |
| 794 | }; | |
| 795 | ||
| f408f9db NKC |
796 | adc: adc@12D10000 { |
| 797 | compatible = "samsung,exynos-adc-v1"; | |
| db9bf4d6 | 798 | reg = <0x12D10000 0x100>; |
| f408f9db | 799 | interrupts = <0 106 0>; |
| fe273c3e | 800 | clocks = <&clock CLK_ADC>; |
| f408f9db NKC |
801 | clock-names = "adc"; |
| 802 | #io-channel-cells = <1>; | |
| 803 | io-channel-ranges; | |
| db9bf4d6 | 804 | samsung,syscon-phandle = <&pmu_system_controller>; |
| f408f9db NKC |
805 | status = "disabled"; |
| 806 | }; | |
| 183af252 NKC |
807 | |
| 808 | sss@10830000 { | |
| 809 | compatible = "samsung,exynos4210-secss"; | |
| cb4f2d75 | 810 | reg = <0x10830000 0x300>; |
| 183af252 | 811 | interrupts = <0 112 0>; |
| e06e1067 | 812 | clocks = <&clock CLK_SSS>; |
| 183af252 NKC |
813 | clock-names = "secss"; |
| 814 | }; | |
| 6cbfdd73 MS |
815 | |
| 816 | sysmmu_g2d: sysmmu@10A60000 { | |
| 817 | compatible = "samsung,exynos-sysmmu"; | |
| 818 | reg = <0x10A60000 0x1000>; | |
| 819 | interrupt-parent = <&combiner>; | |
| 820 | interrupts = <24 5>; | |
| 821 | clock-names = "sysmmu", "master"; | |
| 822 | clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; | |
| 823 | #iommu-cells = <0>; | |
| 824 | }; | |
| 825 | ||
| 826 | sysmmu_mfc_r: sysmmu@11200000 { | |
| 827 | compatible = "samsung,exynos-sysmmu"; | |
| 828 | reg = <0x11200000 0x1000>; | |
| 829 | interrupt-parent = <&combiner>; | |
| 830 | interrupts = <6 2>; | |
| 831 | power-domains = <&pd_mfc>; | |
| 832 | clock-names = "sysmmu", "master"; | |
| 833 | clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; | |
| 834 | #iommu-cells = <0>; | |
| 835 | }; | |
| 836 | ||
| 837 | sysmmu_mfc_l: sysmmu@11210000 { | |
| 838 | compatible = "samsung,exynos-sysmmu"; | |
| 839 | reg = <0x11210000 0x1000>; | |
| 840 | interrupt-parent = <&combiner>; | |
| 841 | interrupts = <8 5>; | |
| 842 | power-domains = <&pd_mfc>; | |
| 843 | clock-names = "sysmmu", "master"; | |
| 844 | clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; | |
| 845 | #iommu-cells = <0>; | |
| 846 | }; | |
| 847 | ||
| 848 | sysmmu_rotator: sysmmu@11D40000 { | |
| 849 | compatible = "samsung,exynos-sysmmu"; | |
| 850 | reg = <0x11D40000 0x1000>; | |
| 851 | interrupt-parent = <&combiner>; | |
| 852 | interrupts = <4 0>; | |
| 853 | clock-names = "sysmmu", "master"; | |
| 854 | clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; | |
| 855 | #iommu-cells = <0>; | |
| 856 | }; | |
| 857 | ||
| 858 | sysmmu_jpeg: sysmmu@11F20000 { | |
| 859 | compatible = "samsung,exynos-sysmmu"; | |
| 860 | reg = <0x11F20000 0x1000>; | |
| 861 | interrupt-parent = <&combiner>; | |
| 862 | interrupts = <4 2>; | |
| 863 | power-domains = <&pd_gsc>; | |
| 864 | clock-names = "sysmmu", "master"; | |
| 865 | clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; | |
| 866 | #iommu-cells = <0>; | |
| 867 | }; | |
| 868 | ||
| 869 | sysmmu_fimc_isp: sysmmu@13260000 { | |
| 870 | compatible = "samsung,exynos-sysmmu"; | |
| 871 | reg = <0x13260000 0x1000>; | |
| 872 | interrupt-parent = <&combiner>; | |
| 873 | interrupts = <10 6>; | |
| 874 | clock-names = "sysmmu"; | |
| 875 | clocks = <&clock CLK_SMMU_FIMC_ISP>; | |
| 876 | #iommu-cells = <0>; | |
| 877 | }; | |
| 878 | ||
| 879 | sysmmu_fimc_drc: sysmmu@13270000 { | |
| 880 | compatible = "samsung,exynos-sysmmu"; | |
| 881 | reg = <0x13270000 0x1000>; | |
| 882 | interrupt-parent = <&combiner>; | |
| 883 | interrupts = <11 6>; | |
| 884 | clock-names = "sysmmu"; | |
| 885 | clocks = <&clock CLK_SMMU_FIMC_DRC>; | |
| 886 | #iommu-cells = <0>; | |
| 887 | }; | |
| 888 | ||
| 889 | sysmmu_fimc_fd: sysmmu@132A0000 { | |
| 890 | compatible = "samsung,exynos-sysmmu"; | |
| 891 | reg = <0x132A0000 0x1000>; | |
| 892 | interrupt-parent = <&combiner>; | |
| 893 | interrupts = <5 0>; | |
| 894 | clock-names = "sysmmu"; | |
| 895 | clocks = <&clock CLK_SMMU_FIMC_FD>; | |
| 896 | #iommu-cells = <0>; | |
| 897 | }; | |
| 898 | ||
| 899 | sysmmu_fimc_scc: sysmmu@13280000 { | |
| 900 | compatible = "samsung,exynos-sysmmu"; | |
| 901 | reg = <0x13280000 0x1000>; | |
| 902 | interrupt-parent = <&combiner>; | |
| 903 | interrupts = <5 2>; | |
| 904 | clock-names = "sysmmu"; | |
| 905 | clocks = <&clock CLK_SMMU_FIMC_SCC>; | |
| 906 | #iommu-cells = <0>; | |
| 907 | }; | |
| 908 | ||
| 909 | sysmmu_fimc_scp: sysmmu@13290000 { | |
| 910 | compatible = "samsung,exynos-sysmmu"; | |
| 911 | reg = <0x13290000 0x1000>; | |
| 912 | interrupt-parent = <&combiner>; | |
| 913 | interrupts = <3 6>; | |
| 914 | clock-names = "sysmmu"; | |
| 915 | clocks = <&clock CLK_SMMU_FIMC_SCP>; | |
| 916 | #iommu-cells = <0>; | |
| 917 | }; | |
| 918 | ||
| 919 | sysmmu_fimc_mcuctl: sysmmu@132B0000 { | |
| 920 | compatible = "samsung,exynos-sysmmu"; | |
| 921 | reg = <0x132B0000 0x1000>; | |
| 922 | interrupt-parent = <&combiner>; | |
| 923 | interrupts = <5 4>; | |
| 924 | clock-names = "sysmmu"; | |
| 925 | clocks = <&clock CLK_SMMU_FIMC_MCU>; | |
| 926 | #iommu-cells = <0>; | |
| 927 | }; | |
| 928 | ||
| 929 | sysmmu_fimc_odc: sysmmu@132C0000 { | |
| 930 | compatible = "samsung,exynos-sysmmu"; | |
| 931 | reg = <0x132C0000 0x1000>; | |
| 932 | interrupt-parent = <&combiner>; | |
| 933 | interrupts = <11 0>; | |
| 934 | clock-names = "sysmmu"; | |
| 935 | clocks = <&clock CLK_SMMU_FIMC_ODC>; | |
| 936 | #iommu-cells = <0>; | |
| 937 | }; | |
| 938 | ||
| 939 | sysmmu_fimc_dis0: sysmmu@132D0000 { | |
| 940 | compatible = "samsung,exynos-sysmmu"; | |
| 941 | reg = <0x132D0000 0x1000>; | |
| 942 | interrupt-parent = <&combiner>; | |
| 943 | interrupts = <10 4>; | |
| 944 | clock-names = "sysmmu"; | |
| 945 | clocks = <&clock CLK_SMMU_FIMC_DIS0>; | |
| 946 | #iommu-cells = <0>; | |
| 947 | }; | |
| 948 | ||
| 949 | sysmmu_fimc_dis1: sysmmu@132E0000{ | |
| 950 | compatible = "samsung,exynos-sysmmu"; | |
| 951 | reg = <0x132E0000 0x1000>; | |
| 952 | interrupt-parent = <&combiner>; | |
| 953 | interrupts = <9 4>; | |
| 954 | clock-names = "sysmmu"; | |
| 955 | clocks = <&clock CLK_SMMU_FIMC_DIS1>; | |
| 956 | #iommu-cells = <0>; | |
| 957 | }; | |
| 958 | ||
| 959 | sysmmu_fimc_3dnr: sysmmu@132F0000 { | |
| 960 | compatible = "samsung,exynos-sysmmu"; | |
| 961 | reg = <0x132F0000 0x1000>; | |
| 962 | interrupt-parent = <&combiner>; | |
| 963 | interrupts = <5 6>; | |
| 964 | clock-names = "sysmmu"; | |
| 965 | clocks = <&clock CLK_SMMU_FIMC_3DNR>; | |
| 966 | #iommu-cells = <0>; | |
| 967 | }; | |
| 968 | ||
| 969 | sysmmu_fimc_lite0: sysmmu@13C40000 { | |
| 970 | compatible = "samsung,exynos-sysmmu"; | |
| 971 | reg = <0x13C40000 0x1000>; | |
| 972 | interrupt-parent = <&combiner>; | |
| 973 | interrupts = <3 4>; | |
| 974 | power-domains = <&pd_gsc>; | |
| 975 | clock-names = "sysmmu", "master"; | |
| 976 | clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; | |
| 977 | #iommu-cells = <0>; | |
| 978 | }; | |
| 979 | ||
| 980 | sysmmu_fimc_lite1: sysmmu@13C50000 { | |
| 981 | compatible = "samsung,exynos-sysmmu"; | |
| 982 | reg = <0x13C50000 0x1000>; | |
| 983 | interrupt-parent = <&combiner>; | |
| 984 | interrupts = <24 1>; | |
| 985 | power-domains = <&pd_gsc>; | |
| 986 | clock-names = "sysmmu", "master"; | |
| 987 | clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; | |
| 988 | #iommu-cells = <0>; | |
| 989 | }; | |
| 990 | ||
| 991 | sysmmu_gsc0: sysmmu@13E80000 { | |
| 992 | compatible = "samsung,exynos-sysmmu"; | |
| 993 | reg = <0x13E80000 0x1000>; | |
| 994 | interrupt-parent = <&combiner>; | |
| 995 | interrupts = <2 0>; | |
| 996 | power-domains = <&pd_gsc>; | |
| 997 | clock-names = "sysmmu", "master"; | |
| 998 | clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; | |
| 999 | #iommu-cells = <0>; | |
| 1000 | }; | |
| 1001 | ||
| 1002 | sysmmu_gsc1: sysmmu@13E90000 { | |
| 1003 | compatible = "samsung,exynos-sysmmu"; | |
| 1004 | reg = <0x13E90000 0x1000>; | |
| 1005 | interrupt-parent = <&combiner>; | |
| 1006 | interrupts = <2 2>; | |
| 1007 | power-domains = <&pd_gsc>; | |
| 1008 | clock-names = "sysmmu", "master"; | |
| 1009 | clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; | |
| 1010 | #iommu-cells = <0>; | |
| 1011 | }; | |
| 1012 | ||
| 1013 | sysmmu_gsc2: sysmmu@13EA0000 { | |
| 1014 | compatible = "samsung,exynos-sysmmu"; | |
| 1015 | reg = <0x13EA0000 0x1000>; | |
| 1016 | interrupt-parent = <&combiner>; | |
| 1017 | interrupts = <2 4>; | |
| 1018 | power-domains = <&pd_gsc>; | |
| 1019 | clock-names = "sysmmu", "master"; | |
| 1020 | clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; | |
| 1021 | #iommu-cells = <0>; | |
| 1022 | }; | |
| 1023 | ||
| 1024 | sysmmu_gsc3: sysmmu@13EB0000 { | |
| 1025 | compatible = "samsung,exynos-sysmmu"; | |
| 1026 | reg = <0x13EB0000 0x1000>; | |
| 1027 | interrupt-parent = <&combiner>; | |
| 1028 | interrupts = <2 6>; | |
| 1029 | power-domains = <&pd_gsc>; | |
| 1030 | clock-names = "sysmmu", "master"; | |
| 1031 | clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; | |
| 1032 | #iommu-cells = <0>; | |
| 1033 | }; | |
| 1034 | ||
| 1035 | sysmmu_fimd1: sysmmu@14640000 { | |
| 1036 | compatible = "samsung,exynos-sysmmu"; | |
| 1037 | reg = <0x14640000 0x1000>; | |
| 1038 | interrupt-parent = <&combiner>; | |
| 1039 | interrupts = <3 2>; | |
| 1040 | power-domains = <&pd_disp1>; | |
| 1041 | clock-names = "sysmmu", "master"; | |
| 1042 | clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; | |
| 1043 | #iommu-cells = <0>; | |
| 1044 | }; | |
| 1045 | ||
| 1046 | sysmmu_tv: sysmmu@14650000 { | |
| 1047 | compatible = "samsung,exynos-sysmmu"; | |
| 1048 | reg = <0x14650000 0x1000>; | |
| 1049 | interrupt-parent = <&combiner>; | |
| 1050 | interrupts = <7 4>; | |
| 1051 | power-domains = <&pd_disp1>; | |
| 1052 | clock-names = "sysmmu", "master"; | |
| 1053 | clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; | |
| 1054 | #iommu-cells = <0>; | |
| 1055 | }; | |
| b074abb7 | 1056 | }; |
| e9a2f409 KK |
1057 | |
| 1058 | &dp { | |
| 1059 | power-domains = <&pd_disp1>; | |
| 1060 | clocks = <&clock CLK_DP>; | |
| 1061 | clock-names = "dp"; | |
| 1062 | phys = <&dp_phy>; | |
| 1063 | phy-names = "dp"; | |
| 1064 | }; | |
| 1065 | ||
| 1066 | &fimd { | |
| 1067 | power-domains = <&pd_disp1>; | |
| 1068 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; | |
| 1069 | clock-names = "sclk_fimd", "fimd"; | |
| 6cbfdd73 | 1070 | iommus = <&sysmmu_fimd1>; |
| e9a2f409 KK |
1071 | }; |
| 1072 | ||
| 1073 | &rtc { | |
| 1074 | clocks = <&clock CLK_RTC>; | |
| 1075 | clock-names = "rtc"; | |
| 1076 | interrupt-parent = <&pmu_system_controller>; | |
| 1077 | status = "disabled"; | |
| 1078 | }; | |
| 1079 | ||
| 1080 | &serial_0 { | |
| 1081 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; | |
| 1082 | clock-names = "uart", "clk_uart_baud0"; | |
| 1083 | }; | |
| 1084 | ||
| 1085 | &serial_1 { | |
| 1086 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; | |
| 1087 | clock-names = "uart", "clk_uart_baud0"; | |
| 1088 | }; | |
| 1089 | ||
| 1090 | &serial_2 { | |
| 1091 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; | |
| 1092 | clock-names = "uart", "clk_uart_baud0"; | |
| 1093 | }; | |
| 1094 | ||
| 1095 | &serial_3 { | |
| 1096 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; | |
| 1097 | clock-names = "uart", "clk_uart_baud0"; | |
| 1098 | }; | |
| dc561797 JMC |
1099 | |
| 1100 | #include "exynos5250-pinctrl.dtsi" |