projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 34dcedfb CK |
1 | /* |
| 2 | * SAMSUNG EXYNOS5420 SoC device tree source | |
| 3 | * | |
| 4 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
| 5 | * http://www.samsung.com | |
| 6 | * | |
| 7 | * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. | |
| 8 | * EXYNOS5420 based board files can include this file and provide | |
| 9 | * values for board specfic bindings. | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or modify | |
| 12 | * it under the terms of the GNU General Public License version 2 as | |
| 13 | * published by the Free Software Foundation. | |
| 14 | */ | |
| 15 | ||
| 16 | #include "exynos5.dtsi" | |
| d81c6cbe | 17 | /include/ "exynos5420-pinctrl.dtsi" |
| 34dcedfb CK |
18 | / { |
| 19 | compatible = "samsung,exynos5420"; | |
| 20 | ||
| d81c6cbe LKA |
21 | aliases { |
| 22 | pinctrl0 = &pinctrl_0; | |
| 23 | pinctrl1 = &pinctrl_1; | |
| 24 | pinctrl2 = &pinctrl_2; | |
| 25 | pinctrl3 = &pinctrl_3; | |
| 26 | pinctrl4 = &pinctrl_4; | |
| 27 | }; | |
| 28 | ||
| 34dcedfb CK |
29 | cpus { |
| 30 | #address-cells = <1>; | |
| 31 | #size-cells = <0>; | |
| 32 | ||
| 33 | cpu0: cpu@0 { | |
| 34 | device_type = "cpu"; | |
| 35 | compatible = "arm,cortex-a15"; | |
| 36 | reg = <0x0>; | |
| 37 | clock-frequency = <1800000000>; | |
| 38 | }; | |
| 39 | ||
| 40 | cpu1: cpu@1 { | |
| 41 | device_type = "cpu"; | |
| 42 | compatible = "arm,cortex-a15"; | |
| 43 | reg = <0x1>; | |
| 44 | clock-frequency = <1800000000>; | |
| 45 | }; | |
| 46 | ||
| 47 | cpu2: cpu@2 { | |
| 48 | device_type = "cpu"; | |
| 49 | compatible = "arm,cortex-a15"; | |
| 50 | reg = <0x2>; | |
| 51 | clock-frequency = <1800000000>; | |
| 52 | }; | |
| 53 | ||
| 54 | cpu3: cpu@3 { | |
| 55 | device_type = "cpu"; | |
| 56 | compatible = "arm,cortex-a15"; | |
| 57 | reg = <0x3>; | |
| 58 | clock-frequency = <1800000000>; | |
| 59 | }; | |
| 60 | }; | |
| 61 | ||
| 62 | clock: clock-controller@0x10010000 { | |
| 63 | compatible = "samsung,exynos5420-clock"; | |
| 64 | reg = <0x10010000 0x30000>; | |
| 65 | #clock-cells = <1>; | |
| 66 | }; | |
| 67 | ||
| 68 | mct@101C0000 { | |
| 69 | compatible = "samsung,exynos4210-mct"; | |
| 70 | reg = <0x101C0000 0x800>; | |
| 71 | interrupt-controller; | |
| 72 | #interrups-cells = <1>; | |
| 73 | interrupt-parent = <&mct_map>; | |
| 74 | interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>; | |
| 75 | clocks = <&clock 1>, <&clock 315>; | |
| 76 | clock-names = "fin_pll", "mct"; | |
| 77 | ||
| 78 | mct_map: mct-map { | |
| 79 | #interrupt-cells = <1>; | |
| 80 | #address-cells = <0>; | |
| 81 | #size-cells = <0>; | |
| 82 | interrupt-map = <0 &combiner 23 3>, | |
| 83 | <1 &combiner 23 4>, | |
| 84 | <2 &combiner 25 2>, | |
| 85 | <3 &combiner 25 3>, | |
| 86 | <4 &gic 0 120 0>, | |
| 87 | <5 &gic 0 121 0>, | |
| 88 | <6 &gic 0 122 0>, | |
| 89 | <7 &gic 0 123 0>; | |
| 90 | }; | |
| 91 | }; | |
| 92 | ||
| d81c6cbe LKA |
93 | pinctrl_0: pinctrl@13400000 { |
| 94 | compatible = "samsung,exynos5420-pinctrl"; | |
| 95 | reg = <0x13400000 0x1000>; | |
| 96 | interrupts = <0 45 0>; | |
| 97 | ||
| 98 | wakeup-interrupt-controller { | |
| 99 | compatible = "samsung,exynos4210-wakeup-eint"; | |
| 100 | interrupt-parent = <&gic>; | |
| 101 | interrupts = <0 32 0>; | |
| 102 | }; | |
| 103 | }; | |
| 104 | ||
| 105 | pinctrl_1: pinctrl@13410000 { | |
| 106 | compatible = "samsung,exynos5420-pinctrl"; | |
| 107 | reg = <0x13410000 0x1000>; | |
| 108 | interrupts = <0 78 0>; | |
| 109 | }; | |
| 110 | ||
| 111 | pinctrl_2: pinctrl@14000000 { | |
| 112 | compatible = "samsung,exynos5420-pinctrl"; | |
| 113 | reg = <0x14000000 0x1000>; | |
| 114 | interrupts = <0 46 0>; | |
| 115 | }; | |
| 116 | ||
| 117 | pinctrl_3: pinctrl@14010000 { | |
| 118 | compatible = "samsung,exynos5420-pinctrl"; | |
| 119 | reg = <0x14010000 0x1000>; | |
| 120 | interrupts = <0 50 0>; | |
| 121 | }; | |
| 122 | ||
| 123 | pinctrl_4: pinctrl@03860000 { | |
| 124 | compatible = "samsung,exynos5420-pinctrl"; | |
| 125 | reg = <0x03860000 0x1000>; | |
| 126 | interrupts = <0 47 0>; | |
| 127 | }; | |
| 128 | ||
| 34dcedfb CK |
129 | serial@12C00000 { |
| 130 | clocks = <&clock 257>, <&clock 128>; | |
| 131 | clock-names = "uart", "clk_uart_baud0"; | |
| 132 | }; | |
| 133 | ||
| 134 | serial@12C10000 { | |
| 135 | clocks = <&clock 258>, <&clock 129>; | |
| 136 | clock-names = "uart", "clk_uart_baud0"; | |
| 137 | }; | |
| 138 | ||
| 139 | serial@12C20000 { | |
| 140 | clocks = <&clock 259>, <&clock 130>; | |
| 141 | clock-names = "uart", "clk_uart_baud0"; | |
| 142 | }; | |
| 143 | ||
| 144 | serial@12C30000 { | |
| 145 | clocks = <&clock 260>, <&clock 131>; | |
| 146 | clock-names = "uart", "clk_uart_baud0"; | |
| 147 | }; | |
| 148 | }; |