[deliverable/linux.git] / arch / arm / boot / dts / exynos5420.dtsi

/*
 * SAMSUNG EXYNOS5420 SoC device tree source
 *
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
 * EXYNOS5420 based board files can include this file and provide
 * values for board specfic bindings.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <dt-bindings/clock/exynos5420.h>
#include "exynos5.dtsi"
#include "exynos5420-pinctrl.dtsi"

#include <dt-bindings/clock/exynos-audss-clk.h>

/ {
	compatible = "samsung,exynos5420", "samsung,exynos5";

	aliases {
		mshc0 = &mmc_0;
		mshc1 = &mmc_1;
		mshc2 = &mmc_2;
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		pinctrl2 = &pinctrl_2;
		pinctrl3 = &pinctrl_3;
		pinctrl4 = &pinctrl_4;
		i2c0 = &i2c_0;
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		i2c4 = &hsi2c_4;
		i2c5 = &hsi2c_5;
		i2c6 = &hsi2c_6;
		i2c7 = &hsi2c_7;
		i2c8 = &hsi2c_8;
		i2c9 = &hsi2c_9;
		i2c10 = &hsi2c_10;
		gsc0 = &gsc_0;
		gsc1 = &gsc_1;
		spi0 = &spi_0;
		spi1 = &spi_1;
		spi2 = &spi_2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x0>;
			clock-frequency = <1800000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x1>;
			clock-frequency = <1800000000>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x2>;
			clock-frequency = <1800000000>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x3>;
			clock-frequency = <1800000000>;
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x100>;
			clock-frequency = <1000000000>;
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x101>;
			clock-frequency = <1000000000>;
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x102>;
			clock-frequency = <1000000000>;
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x103>;
			clock-frequency = <1000000000>;
		};
	};

	sysram@02020000 {
		compatible = "mmio-sram";
		reg = <0x02020000 0x54000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x02020000 0x54000>;

		smp-sysram@0 {
			compatible = "samsung,exynos4210-sysram";
			reg = <0x0 0x1000>;
		};

		smp-sysram@53000 {
			compatible = "samsung,exynos4210-sysram-ns";
			reg = <0x53000 0x1000>;
		};
	};

	clock: clock-controller@10010000 {
		compatible = "samsung,exynos5420-clock";
		reg = <0x10010000 0x30000>;
		#clock-cells = <1>;
	};

	clock_audss: audss-clock-controller@3810000 {
		compatible = "samsung,exynos5420-audss-clock";
		reg = <0x03810000 0x0C>;
		#clock-cells = <1>;
		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
			 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
		clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
	};

	mfc: codec@11000000 {
		compatible = "samsung,mfc-v7";
		reg = <0x11000000 0x10000>;
		interrupts = <0 96 0>;
		clocks = <&clock CLK_MFC>;
		clock-names = "mfc";
	};

	mmc_0: mmc@12200000 {
		compatible = "samsung,exynos5420-dw-mshc-smu";
		interrupts = <0 75 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x12200000 0x2000>;
		clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
		clock-names = "biu", "ciu";
		fifo-depth = <0x40>;
		status = "disabled";
	};

	mmc_1: mmc@12210000 {
		compatible = "samsung,exynos5420-dw-mshc-smu";
		interrupts = <0 76 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x12210000 0x2000>;
		clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
		clock-names = "biu", "ciu";
		fifo-depth = <0x40>;
		status = "disabled";
	};

	mmc_2: mmc@12220000 {
		compatible = "samsung,exynos5420-dw-mshc";
		interrupts = <0 77 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x12220000 0x1000>;
		clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
		clock-names = "biu", "ciu";
		fifo-depth = <0x40>;
		status = "disabled";
	};

	mct: mct@101C0000 {
		compatible = "samsung,exynos4210-mct";
		reg = <0x101C0000 0x800>;
		interrupt-controller;
		#interrups-cells = <1>;
		interrupt-parent = <&mct_map>;
		interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
				<8>, <9>, <10>, <11>;
		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
		clock-names = "fin_pll", "mct";

		mct_map: mct-map {
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = <0 &combiner 23 3>,
					<1 &combiner 23 4>,
					<2 &combiner 25 2>,
					<3 &combiner 25 3>,
					<4 &gic 0 120 0>,
					<5 &gic 0 121 0>,
					<6 &gic 0 122 0>,
					<7 &gic 0 123 0>,
					<8 &gic 0 128 0>,
					<9 &gic 0 129 0>,
					<10 &gic 0 130 0>,
					<11 &gic 0 131 0>;
		};
	};

	gsc_pd: power-domain@10044000 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10044000 0x20>;
	};

	isp_pd: power-domain@10044020 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10044020 0x20>;
	};

	mfc_pd: power-domain@10044060 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10044060 0x20>;
	};

	disp_pd: power-domain@100440C0 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x100440C0 0x20>;
	};

	mau_pd: power-domain@100440E0 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x100440E0 0x20>;
	};

	g2d_pd: power-domain@10044100 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10044100 0x20>;
	};

	msc_pd: power-domain@10044120 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10044120 0x20>;
	};

	pinctrl_0: pinctrl@13400000 {
		compatible = "samsung,exynos5420-pinctrl";
		reg = <0x13400000 0x1000>;
		interrupts = <0 45 0>;

		wakeup-interrupt-controller {
			compatible = "samsung,exynos4210-wakeup-eint";
			interrupt-parent = <&gic>;
			interrupts = <0 32 0>;
		};
	};

	pinctrl_1: pinctrl@13410000 {
		compatible = "samsung,exynos5420-pinctrl";
		reg = <0x13410000 0x1000>;
		interrupts = <0 78 0>;
	};

	pinctrl_2: pinctrl@14000000 {
		compatible = "samsung,exynos5420-pinctrl";
		reg = <0x14000000 0x1000>;
		interrupts = <0 46 0>;
	};

	pinctrl_3: pinctrl@14010000 {
		compatible = "samsung,exynos5420-pinctrl";
		reg = <0x14010000 0x1000>;
		interrupts = <0 50 0>;
	};

	pinctrl_4: pinctrl@03860000 {
		compatible = "samsung,exynos5420-pinctrl";
		reg = <0x03860000 0x1000>;
		interrupts = <0 47 0>;
	};

	rtc: rtc@101E0000 {
		clocks = <&clock CLK_RTC>;
		clock-names = "rtc";
		status = "disabled";
	};

	amba {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "arm,amba-bus";
		interrupt-parent = <&gic>;
		ranges;

		adma: adma@03880000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x03880000 0x1000>;
			interrupts = <0 110 0>;
			clocks = <&clock_audss EXYNOS_ADMA>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
			#dma-channels = <6>;
			#dma-requests = <16>;
		};

		pdma0: pdma@121A0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x121A0000 0x1000>;
			interrupts = <0 34 0>;
			clocks = <&clock CLK_PDMA0>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <32>;
		};

		pdma1: pdma@121B0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x121B0000 0x1000>;
			interrupts = <0 35 0>;
			clocks = <&clock CLK_PDMA1>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <32>;
		};

		mdma0: mdma@10800000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x10800000 0x1000>;
			interrupts = <0 33 0>;
			clocks = <&clock CLK_MDMA0>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <1>;
		};

		mdma1: mdma@11C10000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x11C10000 0x1000>;
			interrupts = <0 124 0>;
			clocks = <&clock CLK_MDMA1>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <1>;
		};
	};

	i2s0: i2s@03830000 {
		compatible = "samsung,exynos5420-i2s";
		reg = <0x03830000 0x100>;
		dmas = <&adma 0
			&adma 2
			&adma 1>;
		dma-names = "tx", "rx", "tx-sec";
		clocks = <&clock_audss EXYNOS_I2S_BUS>,
			<&clock_audss EXYNOS_I2S_BUS>,
			<&clock_audss EXYNOS_SCLK_I2S>;
		clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
		samsung,idma-addr = <0x03000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s0_bus>;
		status = "disabled";
	};

	i2s1: i2s@12D60000 {
		compatible = "samsung,exynos5420-i2s";
		reg = <0x12D60000 0x100>;
		dmas = <&pdma1 12
			&pdma1 11>;
		dma-names = "tx", "rx";
		clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
		clock-names = "iis", "i2s_opclk0";
		pinctrl-names = "default";
		pinctrl-0 = <&i2s1_bus>;
		status = "disabled";
	};

	i2s2: i2s@12D70000 {
		compatible = "samsung,exynos5420-i2s";
		reg = <0x12D70000 0x100>;
		dmas = <&pdma0 12
			&pdma0 11>;
		dma-names = "tx", "rx";
		clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
		clock-names = "iis", "i2s_opclk0";
		pinctrl-names = "default";
		pinctrl-0 = <&i2s2_bus>;
		status = "disabled";
	};

	spi_0: spi@12d20000 {
		compatible = "samsung,exynos4210-spi";
		reg = <0x12d20000 0x100>;
		interrupts = <0 66 0>;
		dmas = <&pdma0 5
			&pdma0 4>;
		dma-names = "tx", "rx";
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi0_bus>;
		clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
		clock-names = "spi", "spi_busclk0";
		status = "disabled";
	};

	spi_1: spi@12d30000 {
		compatible = "samsung,exynos4210-spi";
		reg = <0x12d30000 0x100>;
		interrupts = <0 67 0>;
		dmas = <&pdma1 5
			&pdma1 4>;
		dma-names = "tx", "rx";
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi1_bus>;
		clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
		clock-names = "spi", "spi_busclk0";
		status = "disabled";
	};

	spi_2: spi@12d40000 {
		compatible = "samsung,exynos4210-spi";
		reg = <0x12d40000 0x100>;
		interrupts = <0 68 0>;
		dmas = <&pdma0 7
			&pdma0 6>;
		dma-names = "tx", "rx";
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi2_bus>;
		clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
		clock-names = "spi", "spi_busclk0";
		status = "disabled";
	};

	uart_0: serial@12C00000 {
		clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
		clock-names = "uart", "clk_uart_baud0";
	};

	uart_1: serial@12C10000 {
		clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
		clock-names = "uart", "clk_uart_baud0";
	};

	uart_2: serial@12C20000 {
		clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
		clock-names = "uart", "clk_uart_baud0";
	};

	uart_3: serial@12C30000 {
		clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
		clock-names = "uart", "clk_uart_baud0";
	};

	pwm: pwm@12dd0000 {
		compatible = "samsung,exynos4210-pwm";
		reg = <0x12dd0000 0x100>;
		samsung,pwm-outputs = <0>, <1>, <2>, <3>;
		#pwm-cells = <3>;
		clocks = <&clock CLK_PWM>;
		clock-names = "timers";
	};

	dp_phy: video-phy@10040728 {
		compatible = "samsung,exynos5250-dp-video-phy";
		reg = <0x10040728 4>;
		#phy-cells = <0>;
	};

	dp: dp-controller@145B0000 {
		clocks = <&clock CLK_DP1>;
		clock-names = "dp";
		phys = <&dp_phy>;
		phy-names = "dp";
	};

	fimd: fimd@14400000 {
		samsung,power-domain = <&disp_pd>;
		clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
		clock-names = "sclk_fimd", "fimd";
	};

	adc: adc@12D10000 {
		compatible = "samsung,exynos-adc-v2";
		reg = <0x12D10000 0x100>, <0x10040720 0x4>;
		interrupts = <0 106 0>;
		clocks = <&clock CLK_TSADC>;
		clock-names = "adc";
		#io-channel-cells = <1>;
		io-channel-ranges;
		status = "disabled";
	};

	i2c_0: i2c@12C60000 {
		compatible = "samsung,s3c2440-i2c";
		reg = <0x12C60000 0x100>;
		interrupts = <0 56 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_I2C0>;
		clock-names = "i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_bus>;
		status = "disabled";
	};

	i2c_1: i2c@12C70000 {
		compatible = "samsung,s3c2440-i2c";
		reg = <0x12C70000 0x100>;
		interrupts = <0 57 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_I2C1>;
		clock-names = "i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c1_bus>;
		status = "disabled";
	};

	i2c_2: i2c@12C80000 {
		compatible = "samsung,s3c2440-i2c";
		reg = <0x12C80000 0x100>;
		interrupts = <0 58 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_I2C2>;
		clock-names = "i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c2_bus>;
		status = "disabled";
	};

	i2c_3: i2c@12C90000 {
		compatible = "samsung,s3c2440-i2c";
		reg = <0x12C90000 0x100>;
		interrupts = <0 59 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_I2C3>;
		clock-names = "i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c3_bus>;
		status = "disabled";
	};

	hsi2c_4: i2c@12CA0000 {
		compatible = "samsung,exynos5-hsi2c";
		reg = <0x12CA0000 0x1000>;
		interrupts = <0 60 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c4_hs_bus>;
		clocks = <&clock CLK_I2C4>;
		clock-names = "hsi2c";
		status = "disabled";
	};

	hsi2c_5: i2c@12CB0000 {
		compatible = "samsung,exynos5-hsi2c";
		reg = <0x12CB0000 0x1000>;
		interrupts = <0 61 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c5_hs_bus>;
		clocks = <&clock CLK_I2C5>;
		clock-names = "hsi2c";
		status = "disabled";
	};

	hsi2c_6: i2c@12CC0000 {
		compatible = "samsung,exynos5-hsi2c";
		reg = <0x12CC0000 0x1000>;
		interrupts = <0 62 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c6_hs_bus>;
		clocks = <&clock CLK_I2C6>;
		clock-names = "hsi2c";
		status = "disabled";
	};

	hsi2c_7: i2c@12CD0000 {
		compatible = "samsung,exynos5-hsi2c";
		reg = <0x12CD0000 0x1000>;
		interrupts = <0 63 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c7_hs_bus>;
		clocks = <&clock CLK_I2C7>;
		clock-names = "hsi2c";
		status = "disabled";
	};

	hsi2c_8: i2c@12E00000 {
		compatible = "samsung,exynos5-hsi2c";
		reg = <0x12E00000 0x1000>;
		interrupts = <0 87 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c8_hs_bus>;
		clocks = <&clock CLK_I2C8>;
		clock-names = "hsi2c";
		status = "disabled";
	};

	hsi2c_9: i2c@12E10000 {
		compatible = "samsung,exynos5-hsi2c";
		reg = <0x12E10000 0x1000>;
		interrupts = <0 88 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c9_hs_bus>;
		clocks = <&clock CLK_I2C9>;
		clock-names = "hsi2c";
		status = "disabled";
	};

	hsi2c_10: i2c@12E20000 {
		compatible = "samsung,exynos5-hsi2c";
		reg = <0x12E20000 0x1000>;
		interrupts = <0 203 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c10_hs_bus>;
		clocks = <&clock CLK_I2C10>;
		clock-names = "hsi2c";
		status = "disabled";
	};

	hdmi: hdmi@14530000 {
		compatible = "samsung,exynos4212-hdmi";
		reg = <0x14530000 0x70000>;
		interrupts = <0 95 0>;
		clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
			 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
			 <&clock CLK_MOUT_HDMI>;
		clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
			"sclk_hdmiphy", "mout_hdmi";
		status = "disabled";
	};

	mixer: mixer@14450000 {
		compatible = "samsung,exynos5420-mixer";
		reg = <0x14450000 0x10000>;
		interrupts = <0 94 0>;
		clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
		clock-names = "mixer", "sclk_hdmi";
	};

	gsc_0: video-scaler@13e00000 {
		compatible = "samsung,exynos5-gsc";
		reg = <0x13e00000 0x1000>;
		interrupts = <0 85 0>;
		clocks = <&clock CLK_GSCL0>;
		clock-names = "gscl";
		samsung,power-domain = <&gsc_pd>;
	};

	gsc_1: video-scaler@13e10000 {
		compatible = "samsung,exynos5-gsc";
		reg = <0x13e10000 0x1000>;
		interrupts = <0 86 0>;
		clocks = <&clock CLK_GSCL1>;
		clock-names = "gscl";
		samsung,power-domain = <&gsc_pd>;
	};

	pmu_system_controller: system-controller@10040000 {
		compatible = "samsung,exynos5420-pmu", "syscon";
		reg = <0x10040000 0x5000>;
	};

	tmu_cpu0: tmu@10060000 {
		compatible = "samsung,exynos5420-tmu";
		reg = <0x10060000 0x100>;
		interrupts = <0 65 0>;
		clocks = <&clock CLK_TMU>;
		clock-names = "tmu_apbif";
	};

	tmu_cpu1: tmu@10064000 {
		compatible = "samsung,exynos5420-tmu";
		reg = <0x10064000 0x100>;
		interrupts = <0 183 0>;
		clocks = <&clock CLK_TMU>;
		clock-names = "tmu_apbif";
	};

	tmu_cpu2: tmu@10068000 {
		compatible = "samsung,exynos5420-tmu-ext-triminfo";
		reg = <0x10068000 0x100>, <0x1006c000 0x4>;
		interrupts = <0 184 0>;
		clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
	};

	tmu_cpu3: tmu@1006c000 {
		compatible = "samsung,exynos5420-tmu-ext-triminfo";
		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
		interrupts = <0 185 0>;
		clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
	};

	tmu_gpu: tmu@100a0000 {
		compatible = "samsung,exynos5420-tmu-ext-triminfo";
		reg = <0x100a0000 0x100>, <0x10068000 0x4>;
		interrupts = <0 215 0>;
		clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
	};

        watchdog: watchdog@101D0000 {
		compatible = "samsung,exynos5420-wdt";
		reg = <0x101D0000 0x100>;
		interrupts = <0 42 0>;
		clocks = <&clock CLK_WDT>;
		clock-names = "watchdog";
		samsung,syscon-phandle = <&pmu_system_controller>;
        };

	sss: sss@10830000 {
		compatible = "samsung,exynos4210-secss";
		reg = <0x10830000 0x10000>;
		interrupts = <0 112 0>;
		clocks = <&clock 471>;
		clock-names = "secss";
		samsung,power-domain = <&g2d_pd>;
	};
};
Commit	Line	Data
34dcedfb CK	1	/*
	2	* SAMSUNG EXYNOS5420 SoC device tree source
	3	*
	4	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
	8	* EXYNOS5420 based board files can include this file and provide
	9	* values for board specfic bindings.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
1dd4e599	16	#include <dt-bindings/clock/exynos5420.h>
34dcedfb	17	#include "exynos5.dtsi"
0bd03f6f	18	#include "exynos5420-pinctrl.dtsi"
35e82775	19
602408e3	20	#include <dt-bindings/clock/exynos-audss-clk.h>
35e82775	21
34dcedfb	22	/ {
8bdb31b4	23	compatible = "samsung,exynos5420", "samsung,exynos5";
34dcedfb	24
d81c6cbe	25	aliases {
0e2c5915 YK	26	mshc0 = &mmc_0;
	27	mshc1 = &mmc_1;
	28	mshc2 = &mmc_2;
d81c6cbe LKA	29	pinctrl0 = &pinctrl_0;
	30	pinctrl1 = &pinctrl_1;
	31	pinctrl2 = &pinctrl_2;
	32	pinctrl3 = &pinctrl_3;
	33	pinctrl4 = &pinctrl_4;
f49e347b AB	34	i2c0 = &i2c_0;
	35	i2c1 = &i2c_1;
	36	i2c2 = &i2c_2;
	37	i2c3 = &i2c_3;
1a9110d6 SK	38	i2c4 = &hsi2c_4;
	39	i2c5 = &hsi2c_5;
	40	i2c6 = &hsi2c_6;
	41	i2c7 = &hsi2c_7;
	42	i2c8 = &hsi2c_8;
	43	i2c9 = &hsi2c_9;
	44	i2c10 = &hsi2c_10;
01eb4636 LKA	45	gsc0 = &gsc_0;
01eb4636 LKA	46	gsc1 = &gsc_1;
e84a2d91 LKA	47	spi0 = &spi_0;
	48	spi1 = &spi_1;
	49	spi2 = &spi_2;
d81c6cbe LKA	50	};
d81c6cbe LKA	51
34dcedfb CK	52	cpus {
	53	#address-cells = <1>;
	54	#size-cells = <0>;
	55
	56	cpu0: cpu@0 {
	57	device_type = "cpu";
	58	compatible = "arm,cortex-a15";
	59	reg = <0x0>;
	60	clock-frequency = <1800000000>;
	61	};
	62
	63	cpu1: cpu@1 {
	64	device_type = "cpu";
	65	compatible = "arm,cortex-a15";
	66	reg = <0x1>;
	67	clock-frequency = <1800000000>;
	68	};
	69
	70	cpu2: cpu@2 {
	71	device_type = "cpu";
	72	compatible = "arm,cortex-a15";
	73	reg = <0x2>;
	74	clock-frequency = <1800000000>;
	75	};
	76
	77	cpu3: cpu@3 {
	78	device_type = "cpu";
	79	compatible = "arm,cortex-a15";
	80	reg = <0x3>;
	81	clock-frequency = <1800000000>;
	82	};
1c0e0854 CK	83
	84	cpu4: cpu@100 {
	85	device_type = "cpu";
	86	compatible = "arm,cortex-a7";
	87	reg = <0x100>;
	88	clock-frequency = <1000000000>;
	89	};
	90
	91	cpu5: cpu@101 {
	92	device_type = "cpu";
	93	compatible = "arm,cortex-a7";
	94	reg = <0x101>;
	95	clock-frequency = <1000000000>;
	96	};
	97
	98	cpu6: cpu@102 {
	99	device_type = "cpu";
	100	compatible = "arm,cortex-a7";
	101	reg = <0x102>;
	102	clock-frequency = <1000000000>;
	103	};
	104
	105	cpu7: cpu@103 {
	106	device_type = "cpu";
	107	compatible = "arm,cortex-a7";
	108	reg = <0x103>;
	109	clock-frequency = <1000000000>;
	110	};
34dcedfb CK	111	};
34dcedfb CK	112
b3205dea SK	113	sysram@02020000 {
	114	compatible = "mmio-sram";
	115	reg = <0x02020000 0x54000>;
	116	#address-cells = <1>;
	117	#size-cells = <1>;
	118	ranges = <0 0x02020000 0x54000>;
	119
	120	smp-sysram@0 {
	121	compatible = "samsung,exynos4210-sysram";
	122	reg = <0x0 0x1000>;
	123	};
	124
	125	smp-sysram@53000 {
	126	compatible = "samsung,exynos4210-sysram-ns";
	127	reg = <0x53000 0x1000>;
	128	};
	129	};
	130
92040bd6	131	clock: clock-controller@10010000 {
34dcedfb CK	132	compatible = "samsung,exynos5420-clock";
	133	reg = <0x10010000 0x30000>;
	134	#clock-cells = <1>;
	135	};
	136
35e82775 AB	137	clock_audss: audss-clock-controller@3810000 {
	138	compatible = "samsung,exynos5420-audss-clock";
	139	reg = <0x03810000 0x0C>;
	140	#clock-cells = <1>;
1dd4e599 AH	141	clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
1dd4e599 AH	142	<&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
59d711e9	143	clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
35e82775 AB	144	};
35e82775 AB	145
8e371a91	146	mfc: codec@11000000 {
f09d062f AK	147	compatible = "samsung,mfc-v7";
	148	reg = <0x11000000 0x10000>;
	149	interrupts = <0 96 0>;
1dd4e599	150	clocks = <&clock CLK_MFC>;
f09d062f AK	151	clock-names = "mfc";
	152	};
	153
0e2c5915 YK	154	mmc_0: mmc@12200000 {
	155	compatible = "samsung,exynos5420-dw-mshc-smu";
	156	interrupts = <0 75 0>;
	157	#address-cells = <1>;
	158	#size-cells = <0>;
	159	reg = <0x12200000 0x2000>;
1dd4e599	160	clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
0e2c5915 YK	161	clock-names = "biu", "ciu";
	162	fifo-depth = <0x40>;
	163	status = "disabled";
	164	};
	165
	166	mmc_1: mmc@12210000 {
	167	compatible = "samsung,exynos5420-dw-mshc-smu";
	168	interrupts = <0 76 0>;
	169	#address-cells = <1>;
	170	#size-cells = <0>;
	171	reg = <0x12210000 0x2000>;
1dd4e599	172	clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
0e2c5915 YK	173	clock-names = "biu", "ciu";
	174	fifo-depth = <0x40>;
	175	status = "disabled";
	176	};
	177
	178	mmc_2: mmc@12220000 {
	179	compatible = "samsung,exynos5420-dw-mshc";
	180	interrupts = <0 77 0>;
	181	#address-cells = <1>;
	182	#size-cells = <0>;
	183	reg = <0x12220000 0x1000>;
1dd4e599	184	clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
0e2c5915 YK	185	clock-names = "biu", "ciu";
	186	fifo-depth = <0x40>;
	187	status = "disabled";
	188	};
	189
8e371a91	190	mct: mct@101C0000 {
34dcedfb CK	191	compatible = "samsung,exynos4210-mct";
	192	reg = <0x101C0000 0x800>;
	193	interrupt-controller;
	194	#interrups-cells = <1>;
	195	interrupt-parent = <&mct_map>;
6c16dedf CK	196	interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
6c16dedf CK	197	<8>, <9>, <10>, <11>;
1dd4e599	198	clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
34dcedfb CK	199	clock-names = "fin_pll", "mct";
	200
	201	mct_map: mct-map {
	202	#interrupt-cells = <1>;
	203	#address-cells = <0>;
	204	#size-cells = <0>;
	205	interrupt-map = <0 &combiner 23 3>,
	206	<1 &combiner 23 4>,
	207	<2 &combiner 25 2>,
	208	<3 &combiner 25 3>,
	209	<4 &gic 0 120 0>,
	210	<5 &gic 0 121 0>,
	211	<6 &gic 0 122 0>,
6c16dedf CK	212	<7 &gic 0 123 0>,
	213	<8 &gic 0 128 0>,
	214	<9 &gic 0 129 0>,
	215	<10 &gic 0 130 0>,
	216	<11 &gic 0 131 0>;
34dcedfb CK	217	};
	218	};
	219
dcfca2cc YSB	220	gsc_pd: power-domain@10044000 {
	221	compatible = "samsung,exynos4210-pd";
	222	reg = <0x10044000 0x20>;
	223	};
	224
	225	isp_pd: power-domain@10044020 {
	226	compatible = "samsung,exynos4210-pd";
	227	reg = <0x10044020 0x20>;
	228	};
	229
	230	mfc_pd: power-domain@10044060 {
	231	compatible = "samsung,exynos4210-pd";
	232	reg = <0x10044060 0x20>;
	233	};
	234
	235	disp_pd: power-domain@100440C0 {
	236	compatible = "samsung,exynos4210-pd";
	237	reg = <0x100440C0 0x20>;
	238	};
	239
	240	mau_pd: power-domain@100440E0 {
	241	compatible = "samsung,exynos4210-pd";
	242	reg = <0x100440E0 0x20>;
	243	};
	244
	245	g2d_pd: power-domain@10044100 {
	246	compatible = "samsung,exynos4210-pd";
	247	reg = <0x10044100 0x20>;
	248	};
	249
	250	msc_pd: power-domain@10044120 {
	251	compatible = "samsung,exynos4210-pd";
	252	reg = <0x10044120 0x20>;
	253	};
	254
d81c6cbe LKA	255	pinctrl_0: pinctrl@13400000 {
	256	compatible = "samsung,exynos5420-pinctrl";
	257	reg = <0x13400000 0x1000>;
	258	interrupts = <0 45 0>;
	259
	260	wakeup-interrupt-controller {
	261	compatible = "samsung,exynos4210-wakeup-eint";
	262	interrupt-parent = <&gic>;
	263	interrupts = <0 32 0>;
	264	};
	265	};
	266
	267	pinctrl_1: pinctrl@13410000 {
	268	compatible = "samsung,exynos5420-pinctrl";
	269	reg = <0x13410000 0x1000>;
	270	interrupts = <0 78 0>;
	271	};
	272
	273	pinctrl_2: pinctrl@14000000 {
	274	compatible = "samsung,exynos5420-pinctrl";
	275	reg = <0x14000000 0x1000>;
	276	interrupts = <0 46 0>;
	277	};
	278
	279	pinctrl_3: pinctrl@14010000 {
	280	compatible = "samsung,exynos5420-pinctrl";
	281	reg = <0x14010000 0x1000>;
	282	interrupts = <0 50 0>;
	283	};
	284
	285	pinctrl_4: pinctrl@03860000 {
	286	compatible = "samsung,exynos5420-pinctrl";
	287	reg = <0x03860000 0x1000>;
	288	interrupts = <0 47 0>;
	289	};
	290
8e371a91	291	rtc: rtc@101E0000 {
1dd4e599	292	clocks = <&clock CLK_RTC>;
a81951d9	293	clock-names = "rtc";
451c402b	294	status = "disabled";
a81951d9 VS	295	};
a81951d9 VS	296
e3188533 PV	297	amba {
	298	#address-cells = <1>;
	299	#size-cells = <1>;
	300	compatible = "arm,amba-bus";
	301	interrupt-parent = <&gic>;
	302	ranges;
	303
6dd2f1c4 SK	304	adma: adma@03880000 {
	305	compatible = "arm,pl330", "arm,primecell";
	306	reg = <0x03880000 0x1000>;
	307	interrupts = <0 110 0>;
	308	clocks = <&clock_audss EXYNOS_ADMA>;
	309	clock-names = "apb_pclk";
	310	#dma-cells = <1>;
	311	#dma-channels = <6>;
	312	#dma-requests = <16>;
	313	};
	314
e3188533 PV	315	pdma0: pdma@121A0000 {
	316	compatible = "arm,pl330", "arm,primecell";
	317	reg = <0x121A0000 0x1000>;
	318	interrupts = <0 34 0>;
1dd4e599	319	clocks = <&clock CLK_PDMA0>;
e3188533 PV	320	clock-names = "apb_pclk";
	321	#dma-cells = <1>;
	322	#dma-channels = <8>;
	323	#dma-requests = <32>;
	324	};
	325
	326	pdma1: pdma@121B0000 {
	327	compatible = "arm,pl330", "arm,primecell";
	328	reg = <0x121B0000 0x1000>;
	329	interrupts = <0 35 0>;
1dd4e599	330	clocks = <&clock CLK_PDMA1>;
e3188533 PV	331	clock-names = "apb_pclk";
	332	#dma-cells = <1>;
	333	#dma-channels = <8>;
	334	#dma-requests = <32>;
	335	};
	336
	337	mdma0: mdma@10800000 {
	338	compatible = "arm,pl330", "arm,primecell";
	339	reg = <0x10800000 0x1000>;
	340	interrupts = <0 33 0>;
1dd4e599	341	clocks = <&clock CLK_MDMA0>;
e3188533 PV	342	clock-names = "apb_pclk";
	343	#dma-cells = <1>;
	344	#dma-channels = <8>;
	345	#dma-requests = <1>;
	346	};
	347
	348	mdma1: mdma@11C10000 {
	349	compatible = "arm,pl330", "arm,primecell";
	350	reg = <0x11C10000 0x1000>;
	351	interrupts = <0 124 0>;
1dd4e599	352	clocks = <&clock CLK_MDMA1>;
e3188533 PV	353	clock-names = "apb_pclk";
	354	#dma-cells = <1>;
	355	#dma-channels = <8>;
	356	#dma-requests = <1>;
	357	};
	358	};
	359
98bcb547 SK	360	i2s0: i2s@03830000 {
	361	compatible = "samsung,exynos5420-i2s";
	362	reg = <0x03830000 0x100>;
	363	dmas = <&adma 0
	364	&adma 2
	365	&adma 1>;
	366	dma-names = "tx", "rx", "tx-sec";
	367	clocks = <&clock_audss EXYNOS_I2S_BUS>,
	368	<&clock_audss EXYNOS_I2S_BUS>,
	369	<&clock_audss EXYNOS_SCLK_I2S>;
	370	clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
	371	samsung,idma-addr = <0x03000000>;
	372	pinctrl-names = "default";
	373	pinctrl-0 = <&i2s0_bus>;
	374	status = "disabled";
	375	};
	376
	377	i2s1: i2s@12D60000 {
	378	compatible = "samsung,exynos5420-i2s";
	379	reg = <0x12D60000 0x100>;
	380	dmas = <&pdma1 12
	381	&pdma1 11>;
	382	dma-names = "tx", "rx";
1dd4e599	383	clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
98bcb547 SK	384	clock-names = "iis", "i2s_opclk0";
	385	pinctrl-names = "default";
	386	pinctrl-0 = <&i2s1_bus>;
	387	status = "disabled";
	388	};
	389
	390	i2s2: i2s@12D70000 {
	391	compatible = "samsung,exynos5420-i2s";
	392	reg = <0x12D70000 0x100>;
	393	dmas = <&pdma0 12
	394	&pdma0 11>;
	395	dma-names = "tx", "rx";
1dd4e599	396	clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
98bcb547 SK	397	clock-names = "iis", "i2s_opclk0";
	398	pinctrl-names = "default";
	399	pinctrl-0 = <&i2s2_bus>;
	400	status = "disabled";
	401	};
	402
e84a2d91 LKA	403	spi_0: spi@12d20000 {
	404	compatible = "samsung,exynos4210-spi";
	405	reg = <0x12d20000 0x100>;
	406	interrupts = <0 66 0>;
	407	dmas = <&pdma0 5
	408	&pdma0 4>;
	409	dma-names = "tx", "rx";
	410	#address-cells = <1>;
	411	#size-cells = <0>;
	412	pinctrl-names = "default";
	413	pinctrl-0 = <&spi0_bus>;
1dd4e599	414	clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
e84a2d91 LKA	415	clock-names = "spi", "spi_busclk0";
	416	status = "disabled";
	417	};
	418
	419	spi_1: spi@12d30000 {
	420	compatible = "samsung,exynos4210-spi";
	421	reg = <0x12d30000 0x100>;
	422	interrupts = <0 67 0>;
	423	dmas = <&pdma1 5
	424	&pdma1 4>;
	425	dma-names = "tx", "rx";
	426	#address-cells = <1>;
	427	#size-cells = <0>;
	428	pinctrl-names = "default";
	429	pinctrl-0 = <&spi1_bus>;
1dd4e599	430	clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
e84a2d91 LKA	431	clock-names = "spi", "spi_busclk0";
	432	status = "disabled";
	433	};
	434
	435	spi_2: spi@12d40000 {
	436	compatible = "samsung,exynos4210-spi";
	437	reg = <0x12d40000 0x100>;
	438	interrupts = <0 68 0>;
	439	dmas = <&pdma0 7
	440	&pdma0 6>;
	441	dma-names = "tx", "rx";
	442	#address-cells = <1>;
	443	#size-cells = <0>;
	444	pinctrl-names = "default";
	445	pinctrl-0 = <&spi2_bus>;
1dd4e599	446	clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
e84a2d91 LKA	447	clock-names = "spi", "spi_busclk0";
	448	status = "disabled";
	449	};
	450
8e371a91	451	uart_0: serial@12C00000 {
1dd4e599	452	clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
34dcedfb CK	453	clock-names = "uart", "clk_uart_baud0";
	454	};
	455
8e371a91	456	uart_1: serial@12C10000 {
1dd4e599	457	clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
34dcedfb CK	458	clock-names = "uart", "clk_uart_baud0";
	459	};
	460
8e371a91	461	uart_2: serial@12C20000 {
1dd4e599	462	clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
34dcedfb CK	463	clock-names = "uart", "clk_uart_baud0";
	464	};
	465
8e371a91	466	uart_3: serial@12C30000 {
1dd4e599	467	clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
34dcedfb CK	468	clock-names = "uart", "clk_uart_baud0";
34dcedfb CK	469	};
ee3381d4	470
022cf308 LKA	471	pwm: pwm@12dd0000 {
	472	compatible = "samsung,exynos4210-pwm";
	473	reg = <0x12dd0000 0x100>;
	474	samsung,pwm-outputs = <0>, <1>, <2>, <3>;
	475	#pwm-cells = <3>;
1dd4e599	476	clocks = <&clock CLK_PWM>;
022cf308 LKA	477	clock-names = "timers";
	478	};
	479
1339d33a VS	480	dp_phy: video-phy@10040728 {
	481	compatible = "samsung,exynos5250-dp-video-phy";
	482	reg = <0x10040728 4>;
	483	#phy-cells = <0>;
	484	};
	485
8e371a91	486	dp: dp-controller@145B0000 {
1dd4e599	487	clocks = <&clock CLK_DP1>;
1339d33a VS	488	clock-names = "dp";
	489	phys = <&dp_phy>;
	490	phy-names = "dp";
	491	};
	492
8e371a91	493	fimd: fimd@14400000 {
ee3381d4	494	samsung,power-domain = <&disp_pd>;
1dd4e599	495	clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
ee3381d4 VS	496	clock-names = "sclk_fimd", "fimd";
ee3381d4 VS	497	};
f408f9db NKC	498
	499	adc: adc@12D10000 {
	500	compatible = "samsung,exynos-adc-v2";
	501	reg = <0x12D10000 0x100>, <0x10040720 0x4>;
	502	interrupts = <0 106 0>;
1dd4e599	503	clocks = <&clock CLK_TSADC>;
f408f9db NKC	504	clock-names = "adc";
	505	#io-channel-cells = <1>;
	506	io-channel-ranges;
	507	status = "disabled";
	508	};
f49e347b AB	509
	510	i2c_0: i2c@12C60000 {
	511	compatible = "samsung,s3c2440-i2c";
	512	reg = <0x12C60000 0x100>;
	513	interrupts = <0 56 0>;
	514	#address-cells = <1>;
	515	#size-cells = <0>;
1dd4e599	516	clocks = <&clock CLK_I2C0>;
f49e347b AB	517	clock-names = "i2c";
	518	pinctrl-names = "default";
	519	pinctrl-0 = <&i2c0_bus>;
	520	status = "disabled";
	521	};
	522
	523	i2c_1: i2c@12C70000 {
	524	compatible = "samsung,s3c2440-i2c";
	525	reg = <0x12C70000 0x100>;
	526	interrupts = <0 57 0>;
	527	#address-cells = <1>;
	528	#size-cells = <0>;
1dd4e599	529	clocks = <&clock CLK_I2C1>;
f49e347b AB	530	clock-names = "i2c";
	531	pinctrl-names = "default";
	532	pinctrl-0 = <&i2c1_bus>;
	533	status = "disabled";
	534	};
	535
	536	i2c_2: i2c@12C80000 {
	537	compatible = "samsung,s3c2440-i2c";
	538	reg = <0x12C80000 0x100>;
	539	interrupts = <0 58 0>;
	540	#address-cells = <1>;
	541	#size-cells = <0>;
1dd4e599	542	clocks = <&clock CLK_I2C2>;
f49e347b AB	543	clock-names = "i2c";
	544	pinctrl-names = "default";
	545	pinctrl-0 = <&i2c2_bus>;
	546	status = "disabled";
	547	};
	548
	549	i2c_3: i2c@12C90000 {
	550	compatible = "samsung,s3c2440-i2c";
	551	reg = <0x12C90000 0x100>;
	552	interrupts = <0 59 0>;
	553	#address-cells = <1>;
	554	#size-cells = <0>;
1dd4e599	555	clocks = <&clock CLK_I2C3>;
f49e347b AB	556	clock-names = "i2c";
	557	pinctrl-names = "default";
	558	pinctrl-0 = <&i2c3_bus>;
	559	status = "disabled";
	560	};
b0e505ce	561
1a9110d6 SK	562	hsi2c_4: i2c@12CA0000 {
	563	compatible = "samsung,exynos5-hsi2c";
	564	reg = <0x12CA0000 0x1000>;
	565	interrupts = <0 60 0>;
	566	#address-cells = <1>;
	567	#size-cells = <0>;
	568	pinctrl-names = "default";
	569	pinctrl-0 = <&i2c4_hs_bus>;
1dd4e599	570	clocks = <&clock CLK_I2C4>;
1a9110d6 SK	571	clock-names = "hsi2c";
	572	status = "disabled";
	573	};
	574
	575	hsi2c_5: i2c@12CB0000 {
	576	compatible = "samsung,exynos5-hsi2c";
	577	reg = <0x12CB0000 0x1000>;
	578	interrupts = <0 61 0>;
	579	#address-cells = <1>;
	580	#size-cells = <0>;
	581	pinctrl-names = "default";
	582	pinctrl-0 = <&i2c5_hs_bus>;
1dd4e599	583	clocks = <&clock CLK_I2C5>;
1a9110d6 SK	584	clock-names = "hsi2c";
	585	status = "disabled";
	586	};
	587
	588	hsi2c_6: i2c@12CC0000 {
	589	compatible = "samsung,exynos5-hsi2c";
	590	reg = <0x12CC0000 0x1000>;
	591	interrupts = <0 62 0>;
	592	#address-cells = <1>;
	593	#size-cells = <0>;
	594	pinctrl-names = "default";
	595	pinctrl-0 = <&i2c6_hs_bus>;
1dd4e599	596	clocks = <&clock CLK_I2C6>;
1a9110d6 SK	597	clock-names = "hsi2c";
	598	status = "disabled";
	599	};
	600
	601	hsi2c_7: i2c@12CD0000 {
	602	compatible = "samsung,exynos5-hsi2c";
	603	reg = <0x12CD0000 0x1000>;
	604	interrupts = <0 63 0>;
	605	#address-cells = <1>;
	606	#size-cells = <0>;
	607	pinctrl-names = "default";
	608	pinctrl-0 = <&i2c7_hs_bus>;
1dd4e599	609	clocks = <&clock CLK_I2C7>;
1a9110d6 SK	610	clock-names = "hsi2c";
	611	status = "disabled";
	612	};
	613
	614	hsi2c_8: i2c@12E00000 {
	615	compatible = "samsung,exynos5-hsi2c";
	616	reg = <0x12E00000 0x1000>;
	617	interrupts = <0 87 0>;
	618	#address-cells = <1>;
	619	#size-cells = <0>;
	620	pinctrl-names = "default";
	621	pinctrl-0 = <&i2c8_hs_bus>;
1dd4e599	622	clocks = <&clock CLK_I2C8>;
1a9110d6 SK	623	clock-names = "hsi2c";
	624	status = "disabled";
	625	};
	626
	627	hsi2c_9: i2c@12E10000 {
	628	compatible = "samsung,exynos5-hsi2c";
	629	reg = <0x12E10000 0x1000>;
	630	interrupts = <0 88 0>;
	631	#address-cells = <1>;
	632	#size-cells = <0>;
	633	pinctrl-names = "default";
	634	pinctrl-0 = <&i2c9_hs_bus>;
1dd4e599	635	clocks = <&clock CLK_I2C9>;
1a9110d6 SK	636	clock-names = "hsi2c";
	637	status = "disabled";
	638	};
	639
	640	hsi2c_10: i2c@12E20000 {
	641	compatible = "samsung,exynos5-hsi2c";
	642	reg = <0x12E20000 0x1000>;
	643	interrupts = <0 203 0>;
	644	#address-cells = <1>;
	645	#size-cells = <0>;
	646	pinctrl-names = "default";
	647	pinctrl-0 = <&i2c10_hs_bus>;
1dd4e599	648	clocks = <&clock CLK_I2C10>;
1a9110d6 SK	649	clock-names = "hsi2c";
	650	status = "disabled";
	651	};
	652
8e371a91	653	hdmi: hdmi@14530000 {
b0e505ce RS	654	compatible = "samsung,exynos4212-hdmi";
	655	reg = <0x14530000 0x70000>;
	656	interrupts = <0 95 0>;
1dd4e599 AH	657	clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
	658	<&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
	659	<&clock CLK_MOUT_HDMI>;
b0e505ce RS	660	clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
	661	"sclk_hdmiphy", "mout_hdmi";
	662	status = "disabled";
	663	};
	664
8e371a91	665	mixer: mixer@14450000 {
b0e505ce RS	666	compatible = "samsung,exynos5420-mixer";
	667	reg = <0x14450000 0x10000>;
	668	interrupts = <0 94 0>;
1dd4e599	669	clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
b0e505ce RS	670	clock-names = "mixer", "sclk_hdmi";
b0e505ce RS	671	};
01eb4636 LKA	672
	673	gsc_0: video-scaler@13e00000 {
	674	compatible = "samsung,exynos5-gsc";
	675	reg = <0x13e00000 0x1000>;
	676	interrupts = <0 85 0>;
1dd4e599	677	clocks = <&clock CLK_GSCL0>;
01eb4636 LKA	678	clock-names = "gscl";
	679	samsung,power-domain = <&gsc_pd>;
	680	};
	681
	682	gsc_1: video-scaler@13e10000 {
	683	compatible = "samsung,exynos5-gsc";
	684	reg = <0x13e10000 0x1000>;
	685	interrupts = <0 86 0>;
1dd4e599	686	clocks = <&clock CLK_GSCL1>;
01eb4636 LKA	687	clock-names = "gscl";
	688	samsung,power-domain = <&gsc_pd>;
	689	};
655de648	690
c680036a LKA	691	pmu_system_controller: system-controller@10040000 {
	692	compatible = "samsung,exynos5420-pmu", "syscon";
	693	reg = <0x10040000 0x5000>;
	694	};
	695
655de648 NKC	696	tmu_cpu0: tmu@10060000 {
	697	compatible = "samsung,exynos5420-tmu";
	698	reg = <0x10060000 0x100>;
	699	interrupts = <0 65 0>;
1dd4e599	700	clocks = <&clock CLK_TMU>;
655de648 NKC	701	clock-names = "tmu_apbif";
	702	};
	703
	704	tmu_cpu1: tmu@10064000 {
	705	compatible = "samsung,exynos5420-tmu";
	706	reg = <0x10064000 0x100>;
	707	interrupts = <0 183 0>;
1dd4e599	708	clocks = <&clock CLK_TMU>;
655de648 NKC	709	clock-names = "tmu_apbif";
	710	};
	711
	712	tmu_cpu2: tmu@10068000 {
	713	compatible = "samsung,exynos5420-tmu-ext-triminfo";
	714	reg = <0x10068000 0x100>, <0x1006c000 0x4>;
	715	interrupts = <0 184 0>;
1dd4e599	716	clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
655de648 NKC	717	clock-names = "tmu_apbif", "tmu_triminfo_apbif";
	718	};
	719
	720	tmu_cpu3: tmu@1006c000 {
	721	compatible = "samsung,exynos5420-tmu-ext-triminfo";
	722	reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
	723	interrupts = <0 185 0>;
1dd4e599	724	clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
655de648 NKC	725	clock-names = "tmu_apbif", "tmu_triminfo_apbif";
	726	};
	727
	728	tmu_gpu: tmu@100a0000 {
	729	compatible = "samsung,exynos5420-tmu-ext-triminfo";
	730	reg = <0x100a0000 0x100>, <0x10068000 0x4>;
	731	interrupts = <0 215 0>;
1dd4e599	732	clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
655de648 NKC	733	clock-names = "tmu_apbif", "tmu_triminfo_apbif";
655de648 NKC	734	};
1d287620	735
8e371a91	736	watchdog: watchdog@101D0000 {
1d287620 LKA	737	compatible = "samsung,exynos5420-wdt";
	738	reg = <0x101D0000 0x100>;
	739	interrupts = <0 42 0>;
1dd4e599	740	clocks = <&clock CLK_WDT>;
1d287620 LKA	741	clock-names = "watchdog";
	742	samsung,syscon-phandle = <&pmu_system_controller>;
	743	};
183af252	744
8e371a91	745	sss: sss@10830000 {
183af252 NKC	746	compatible = "samsung,exynos4210-secss";
	747	reg = <0x10830000 0x10000>;
	748	interrupts = <0 112 0>;
	749	clocks = <&clock 471>;
	750	clock-names = "secss";
	751	samsung,power-domain = <&g2d_pd>;
	752	};
34dcedfb	753	};