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34dcedfb CK |
1 | /* |
2 | * SAMSUNG EXYNOS5420 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. | |
8 | * EXYNOS5420 based board files can include this file and provide | |
9 | * values for board specfic bindings. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
1dd4e599 | 16 | #include <dt-bindings/clock/exynos5420.h> |
34dcedfb | 17 | #include "exynos5.dtsi" |
35e82775 | 18 | |
602408e3 | 19 | #include <dt-bindings/clock/exynos-audss-clk.h> |
35e82775 | 20 | |
34dcedfb | 21 | / { |
8bdb31b4 | 22 | compatible = "samsung,exynos5420", "samsung,exynos5"; |
34dcedfb | 23 | |
d81c6cbe | 24 | aliases { |
0e2c5915 YK |
25 | mshc0 = &mmc_0; |
26 | mshc1 = &mmc_1; | |
27 | mshc2 = &mmc_2; | |
d81c6cbe LKA |
28 | pinctrl0 = &pinctrl_0; |
29 | pinctrl1 = &pinctrl_1; | |
30 | pinctrl2 = &pinctrl_2; | |
31 | pinctrl3 = &pinctrl_3; | |
32 | pinctrl4 = &pinctrl_4; | |
f49e347b AB |
33 | i2c0 = &i2c_0; |
34 | i2c1 = &i2c_1; | |
35 | i2c2 = &i2c_2; | |
36 | i2c3 = &i2c_3; | |
1a9110d6 SK |
37 | i2c4 = &hsi2c_4; |
38 | i2c5 = &hsi2c_5; | |
39 | i2c6 = &hsi2c_6; | |
40 | i2c7 = &hsi2c_7; | |
41 | i2c8 = &hsi2c_8; | |
42 | i2c9 = &hsi2c_9; | |
43 | i2c10 = &hsi2c_10; | |
01eb4636 LKA |
44 | gsc0 = &gsc_0; |
45 | gsc1 = &gsc_1; | |
e84a2d91 LKA |
46 | spi0 = &spi_0; |
47 | spi1 = &spi_1; | |
48 | spi2 = &spi_2; | |
3cb7d1cd VG |
49 | usbdrdphy0 = &usbdrd_phy0; |
50 | usbdrdphy1 = &usbdrd_phy1; | |
d81c6cbe LKA |
51 | }; |
52 | ||
34dcedfb CK |
53 | cpus { |
54 | #address-cells = <1>; | |
55 | #size-cells = <0>; | |
56 | ||
57 | cpu0: cpu@0 { | |
58 | device_type = "cpu"; | |
59 | compatible = "arm,cortex-a15"; | |
60 | reg = <0x0>; | |
61 | clock-frequency = <1800000000>; | |
5b56642b | 62 | cci-control-port = <&cci_control1>; |
34dcedfb CK |
63 | }; |
64 | ||
65 | cpu1: cpu@1 { | |
66 | device_type = "cpu"; | |
67 | compatible = "arm,cortex-a15"; | |
68 | reg = <0x1>; | |
69 | clock-frequency = <1800000000>; | |
5b56642b | 70 | cci-control-port = <&cci_control1>; |
34dcedfb CK |
71 | }; |
72 | ||
73 | cpu2: cpu@2 { | |
74 | device_type = "cpu"; | |
75 | compatible = "arm,cortex-a15"; | |
76 | reg = <0x2>; | |
77 | clock-frequency = <1800000000>; | |
5b56642b | 78 | cci-control-port = <&cci_control1>; |
34dcedfb CK |
79 | }; |
80 | ||
81 | cpu3: cpu@3 { | |
82 | device_type = "cpu"; | |
83 | compatible = "arm,cortex-a15"; | |
84 | reg = <0x3>; | |
85 | clock-frequency = <1800000000>; | |
5b56642b | 86 | cci-control-port = <&cci_control1>; |
34dcedfb | 87 | }; |
1c0e0854 CK |
88 | |
89 | cpu4: cpu@100 { | |
90 | device_type = "cpu"; | |
91 | compatible = "arm,cortex-a7"; | |
92 | reg = <0x100>; | |
93 | clock-frequency = <1000000000>; | |
5b56642b | 94 | cci-control-port = <&cci_control0>; |
1c0e0854 CK |
95 | }; |
96 | ||
97 | cpu5: cpu@101 { | |
98 | device_type = "cpu"; | |
99 | compatible = "arm,cortex-a7"; | |
100 | reg = <0x101>; | |
101 | clock-frequency = <1000000000>; | |
5b56642b | 102 | cci-control-port = <&cci_control0>; |
1c0e0854 CK |
103 | }; |
104 | ||
105 | cpu6: cpu@102 { | |
106 | device_type = "cpu"; | |
107 | compatible = "arm,cortex-a7"; | |
108 | reg = <0x102>; | |
109 | clock-frequency = <1000000000>; | |
5b56642b | 110 | cci-control-port = <&cci_control0>; |
1c0e0854 CK |
111 | }; |
112 | ||
113 | cpu7: cpu@103 { | |
114 | device_type = "cpu"; | |
115 | compatible = "arm,cortex-a7"; | |
116 | reg = <0x103>; | |
117 | clock-frequency = <1000000000>; | |
5b56642b AB |
118 | cci-control-port = <&cci_control0>; |
119 | }; | |
120 | }; | |
121 | ||
25217fef | 122 | cci: cci@10d20000 { |
5b56642b AB |
123 | compatible = "arm,cci-400"; |
124 | #address-cells = <1>; | |
125 | #size-cells = <1>; | |
126 | reg = <0x10d20000 0x1000>; | |
127 | ranges = <0x0 0x10d20000 0x6000>; | |
128 | ||
129 | cci_control0: slave-if@4000 { | |
130 | compatible = "arm,cci-400-ctrl-if"; | |
131 | interface-type = "ace"; | |
132 | reg = <0x4000 0x1000>; | |
133 | }; | |
134 | cci_control1: slave-if@5000 { | |
135 | compatible = "arm,cci-400-ctrl-if"; | |
136 | interface-type = "ace"; | |
137 | reg = <0x5000 0x1000>; | |
1c0e0854 | 138 | }; |
34dcedfb CK |
139 | }; |
140 | ||
b3205dea SK |
141 | sysram@02020000 { |
142 | compatible = "mmio-sram"; | |
143 | reg = <0x02020000 0x54000>; | |
144 | #address-cells = <1>; | |
145 | #size-cells = <1>; | |
146 | ranges = <0 0x02020000 0x54000>; | |
147 | ||
148 | smp-sysram@0 { | |
149 | compatible = "samsung,exynos4210-sysram"; | |
150 | reg = <0x0 0x1000>; | |
151 | }; | |
152 | ||
153 | smp-sysram@53000 { | |
154 | compatible = "samsung,exynos4210-sysram-ns"; | |
155 | reg = <0x53000 0x1000>; | |
1c0e0854 | 156 | }; |
34dcedfb CK |
157 | }; |
158 | ||
92040bd6 | 159 | clock: clock-controller@10010000 { |
34dcedfb CK |
160 | compatible = "samsung,exynos5420-clock"; |
161 | reg = <0x10010000 0x30000>; | |
162 | #clock-cells = <1>; | |
163 | }; | |
164 | ||
35e82775 AB |
165 | clock_audss: audss-clock-controller@3810000 { |
166 | compatible = "samsung,exynos5420-audss-clock"; | |
167 | reg = <0x03810000 0x0C>; | |
168 | #clock-cells = <1>; | |
be0b420a | 169 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, |
1dd4e599 | 170 | <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; |
59d711e9 | 171 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; |
35e82775 AB |
172 | }; |
173 | ||
8e371a91 | 174 | mfc: codec@11000000 { |
f09d062f AK |
175 | compatible = "samsung,mfc-v7"; |
176 | reg = <0x11000000 0x10000>; | |
177 | interrupts = <0 96 0>; | |
1dd4e599 | 178 | clocks = <&clock CLK_MFC>; |
f09d062f | 179 | clock-names = "mfc"; |
0da65870 | 180 | power-domains = <&mfc_pd>; |
b7004516 MS |
181 | iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; |
182 | iommu-names = "left", "right"; | |
f09d062f AK |
183 | }; |
184 | ||
0e2c5915 YK |
185 | mmc_0: mmc@12200000 { |
186 | compatible = "samsung,exynos5420-dw-mshc-smu"; | |
187 | interrupts = <0 75 0>; | |
188 | #address-cells = <1>; | |
189 | #size-cells = <0>; | |
190 | reg = <0x12200000 0x2000>; | |
1dd4e599 | 191 | clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; |
0e2c5915 YK |
192 | clock-names = "biu", "ciu"; |
193 | fifo-depth = <0x40>; | |
194 | status = "disabled"; | |
195 | }; | |
196 | ||
197 | mmc_1: mmc@12210000 { | |
198 | compatible = "samsung,exynos5420-dw-mshc-smu"; | |
199 | interrupts = <0 76 0>; | |
200 | #address-cells = <1>; | |
201 | #size-cells = <0>; | |
202 | reg = <0x12210000 0x2000>; | |
1dd4e599 | 203 | clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; |
0e2c5915 YK |
204 | clock-names = "biu", "ciu"; |
205 | fifo-depth = <0x40>; | |
206 | status = "disabled"; | |
207 | }; | |
208 | ||
209 | mmc_2: mmc@12220000 { | |
210 | compatible = "samsung,exynos5420-dw-mshc"; | |
211 | interrupts = <0 77 0>; | |
212 | #address-cells = <1>; | |
213 | #size-cells = <0>; | |
214 | reg = <0x12220000 0x1000>; | |
1dd4e599 | 215 | clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; |
0e2c5915 YK |
216 | clock-names = "biu", "ciu"; |
217 | fifo-depth = <0x40>; | |
218 | status = "disabled"; | |
219 | }; | |
220 | ||
8e371a91 | 221 | mct: mct@101C0000 { |
34dcedfb CK |
222 | compatible = "samsung,exynos4210-mct"; |
223 | reg = <0x101C0000 0x800>; | |
224 | interrupt-controller; | |
f27b9075 | 225 | #interrupt-cells = <1>; |
34dcedfb | 226 | interrupt-parent = <&mct_map>; |
6c16dedf CK |
227 | interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, |
228 | <8>, <9>, <10>, <11>; | |
1dd4e599 | 229 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
34dcedfb CK |
230 | clock-names = "fin_pll", "mct"; |
231 | ||
232 | mct_map: mct-map { | |
233 | #interrupt-cells = <1>; | |
234 | #address-cells = <0>; | |
235 | #size-cells = <0>; | |
236 | interrupt-map = <0 &combiner 23 3>, | |
237 | <1 &combiner 23 4>, | |
238 | <2 &combiner 25 2>, | |
239 | <3 &combiner 25 3>, | |
240 | <4 &gic 0 120 0>, | |
241 | <5 &gic 0 121 0>, | |
242 | <6 &gic 0 122 0>, | |
6c16dedf CK |
243 | <7 &gic 0 123 0>, |
244 | <8 &gic 0 128 0>, | |
245 | <9 &gic 0 129 0>, | |
246 | <10 &gic 0 130 0>, | |
247 | <11 &gic 0 131 0>; | |
34dcedfb CK |
248 | }; |
249 | }; | |
250 | ||
dcfca2cc YSB |
251 | gsc_pd: power-domain@10044000 { |
252 | compatible = "samsung,exynos4210-pd"; | |
253 | reg = <0x10044000 0x20>; | |
0da65870 | 254 | #power-domain-cells = <0>; |
fa87bd43 AH |
255 | clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; |
256 | clock-names = "asb0", "asb1"; | |
dcfca2cc YSB |
257 | }; |
258 | ||
259 | isp_pd: power-domain@10044020 { | |
260 | compatible = "samsung,exynos4210-pd"; | |
261 | reg = <0x10044020 0x20>; | |
0da65870 | 262 | #power-domain-cells = <0>; |
dcfca2cc YSB |
263 | }; |
264 | ||
265 | mfc_pd: power-domain@10044060 { | |
266 | compatible = "samsung,exynos4210-pd"; | |
267 | reg = <0x10044060 0x20>; | |
8d9321fb KK |
268 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>; |
269 | clock-names = "oscclk", "clk0"; | |
0da65870 | 270 | #power-domain-cells = <0>; |
dcfca2cc YSB |
271 | }; |
272 | ||
dcfca2cc YSB |
273 | msc_pd: power-domain@10044120 { |
274 | compatible = "samsung,exynos4210-pd"; | |
275 | reg = <0x10044120 0x20>; | |
0da65870 | 276 | #power-domain-cells = <0>; |
dcfca2cc YSB |
277 | }; |
278 | ||
ea08de16 JMC |
279 | disp_pd: power-domain@100440C0 { |
280 | compatible = "samsung,exynos4210-pd"; | |
281 | reg = <0x100440C0 0x20>; | |
282 | #power-domain-cells = <0>; | |
8d9321fb | 283 | clocks = <&clock CLK_FIN_PLL>, |
ea08de16 | 284 | <&clock CLK_MOUT_USER_ACLK200_DISP1>, |
ea08de16 | 285 | <&clock CLK_MOUT_USER_ACLK300_DISP1>, |
ffb8b1ee AH |
286 | <&clock CLK_MOUT_USER_ACLK400_DISP1>, |
287 | <&clock CLK_FIMD1>, <&clock CLK_MIXER>; | |
8d9321fb | 288 | clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; |
dcfca2cc YSB |
289 | }; |
290 | ||
d81c6cbe LKA |
291 | pinctrl_0: pinctrl@13400000 { |
292 | compatible = "samsung,exynos5420-pinctrl"; | |
293 | reg = <0x13400000 0x1000>; | |
294 | interrupts = <0 45 0>; | |
295 | ||
296 | wakeup-interrupt-controller { | |
297 | compatible = "samsung,exynos4210-wakeup-eint"; | |
298 | interrupt-parent = <&gic>; | |
299 | interrupts = <0 32 0>; | |
300 | }; | |
301 | }; | |
302 | ||
303 | pinctrl_1: pinctrl@13410000 { | |
304 | compatible = "samsung,exynos5420-pinctrl"; | |
305 | reg = <0x13410000 0x1000>; | |
306 | interrupts = <0 78 0>; | |
307 | }; | |
308 | ||
309 | pinctrl_2: pinctrl@14000000 { | |
310 | compatible = "samsung,exynos5420-pinctrl"; | |
311 | reg = <0x14000000 0x1000>; | |
312 | interrupts = <0 46 0>; | |
313 | }; | |
314 | ||
315 | pinctrl_3: pinctrl@14010000 { | |
316 | compatible = "samsung,exynos5420-pinctrl"; | |
317 | reg = <0x14010000 0x1000>; | |
318 | interrupts = <0 50 0>; | |
319 | }; | |
320 | ||
321 | pinctrl_4: pinctrl@03860000 { | |
322 | compatible = "samsung,exynos5420-pinctrl"; | |
323 | reg = <0x03860000 0x1000>; | |
324 | interrupts = <0 47 0>; | |
325 | }; | |
326 | ||
e3188533 PV |
327 | amba { |
328 | #address-cells = <1>; | |
329 | #size-cells = <1>; | |
330 | compatible = "arm,amba-bus"; | |
331 | interrupt-parent = <&gic>; | |
332 | ranges; | |
333 | ||
6dd2f1c4 SK |
334 | adma: adma@03880000 { |
335 | compatible = "arm,pl330", "arm,primecell"; | |
336 | reg = <0x03880000 0x1000>; | |
337 | interrupts = <0 110 0>; | |
338 | clocks = <&clock_audss EXYNOS_ADMA>; | |
339 | clock-names = "apb_pclk"; | |
340 | #dma-cells = <1>; | |
341 | #dma-channels = <6>; | |
342 | #dma-requests = <16>; | |
343 | }; | |
344 | ||
e3188533 PV |
345 | pdma0: pdma@121A0000 { |
346 | compatible = "arm,pl330", "arm,primecell"; | |
347 | reg = <0x121A0000 0x1000>; | |
348 | interrupts = <0 34 0>; | |
1dd4e599 | 349 | clocks = <&clock CLK_PDMA0>; |
e3188533 PV |
350 | clock-names = "apb_pclk"; |
351 | #dma-cells = <1>; | |
352 | #dma-channels = <8>; | |
353 | #dma-requests = <32>; | |
354 | }; | |
355 | ||
356 | pdma1: pdma@121B0000 { | |
357 | compatible = "arm,pl330", "arm,primecell"; | |
358 | reg = <0x121B0000 0x1000>; | |
359 | interrupts = <0 35 0>; | |
1dd4e599 | 360 | clocks = <&clock CLK_PDMA1>; |
e3188533 PV |
361 | clock-names = "apb_pclk"; |
362 | #dma-cells = <1>; | |
363 | #dma-channels = <8>; | |
364 | #dma-requests = <32>; | |
365 | }; | |
366 | ||
367 | mdma0: mdma@10800000 { | |
368 | compatible = "arm,pl330", "arm,primecell"; | |
369 | reg = <0x10800000 0x1000>; | |
370 | interrupts = <0 33 0>; | |
1dd4e599 | 371 | clocks = <&clock CLK_MDMA0>; |
e3188533 PV |
372 | clock-names = "apb_pclk"; |
373 | #dma-cells = <1>; | |
374 | #dma-channels = <8>; | |
375 | #dma-requests = <1>; | |
376 | }; | |
377 | ||
378 | mdma1: mdma@11C10000 { | |
379 | compatible = "arm,pl330", "arm,primecell"; | |
380 | reg = <0x11C10000 0x1000>; | |
381 | interrupts = <0 124 0>; | |
1dd4e599 | 382 | clocks = <&clock CLK_MDMA1>; |
e3188533 PV |
383 | clock-names = "apb_pclk"; |
384 | #dma-cells = <1>; | |
385 | #dma-channels = <8>; | |
386 | #dma-requests = <1>; | |
e6015c1f SJ |
387 | /* |
388 | * MDMA1 can support both secure and non-secure | |
389 | * AXI transactions. When this is enabled in the kernel | |
390 | * for boards that run in secure mode, we are getting | |
391 | * imprecise external aborts causing the kernel to oops. | |
392 | */ | |
393 | status = "disabled"; | |
e3188533 PV |
394 | }; |
395 | }; | |
396 | ||
98bcb547 SK |
397 | i2s0: i2s@03830000 { |
398 | compatible = "samsung,exynos5420-i2s"; | |
399 | reg = <0x03830000 0x100>; | |
400 | dmas = <&adma 0 | |
401 | &adma 2 | |
402 | &adma 1>; | |
403 | dma-names = "tx", "rx", "tx-sec"; | |
404 | clocks = <&clock_audss EXYNOS_I2S_BUS>, | |
405 | <&clock_audss EXYNOS_I2S_BUS>, | |
406 | <&clock_audss EXYNOS_SCLK_I2S>; | |
407 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | |
7a548b1f IS |
408 | #clock-cells = <1>; |
409 | clock-output-names = "i2s_cdclk0"; | |
410 | #sound-dai-cells = <1>; | |
98bcb547 SK |
411 | samsung,idma-addr = <0x03000000>; |
412 | pinctrl-names = "default"; | |
413 | pinctrl-0 = <&i2s0_bus>; | |
414 | status = "disabled"; | |
415 | }; | |
416 | ||
417 | i2s1: i2s@12D60000 { | |
418 | compatible = "samsung,exynos5420-i2s"; | |
419 | reg = <0x12D60000 0x100>; | |
420 | dmas = <&pdma1 12 | |
421 | &pdma1 11>; | |
422 | dma-names = "tx", "rx"; | |
1dd4e599 | 423 | clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; |
98bcb547 | 424 | clock-names = "iis", "i2s_opclk0"; |
7a548b1f IS |
425 | #clock-cells = <1>; |
426 | clock-output-names = "i2s_cdclk1"; | |
427 | #sound-dai-cells = <1>; | |
98bcb547 SK |
428 | pinctrl-names = "default"; |
429 | pinctrl-0 = <&i2s1_bus>; | |
430 | status = "disabled"; | |
431 | }; | |
432 | ||
433 | i2s2: i2s@12D70000 { | |
434 | compatible = "samsung,exynos5420-i2s"; | |
435 | reg = <0x12D70000 0x100>; | |
436 | dmas = <&pdma0 12 | |
437 | &pdma0 11>; | |
438 | dma-names = "tx", "rx"; | |
1dd4e599 | 439 | clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; |
98bcb547 | 440 | clock-names = "iis", "i2s_opclk0"; |
7a548b1f IS |
441 | #clock-cells = <1>; |
442 | clock-output-names = "i2s_cdclk2"; | |
443 | #sound-dai-cells = <1>; | |
98bcb547 SK |
444 | pinctrl-names = "default"; |
445 | pinctrl-0 = <&i2s2_bus>; | |
446 | status = "disabled"; | |
447 | }; | |
448 | ||
e84a2d91 LKA |
449 | spi_0: spi@12d20000 { |
450 | compatible = "samsung,exynos4210-spi"; | |
451 | reg = <0x12d20000 0x100>; | |
e3b6c271 | 452 | interrupts = <0 68 0>; |
e84a2d91 LKA |
453 | dmas = <&pdma0 5 |
454 | &pdma0 4>; | |
455 | dma-names = "tx", "rx"; | |
456 | #address-cells = <1>; | |
457 | #size-cells = <0>; | |
458 | pinctrl-names = "default"; | |
459 | pinctrl-0 = <&spi0_bus>; | |
1dd4e599 | 460 | clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; |
e84a2d91 LKA |
461 | clock-names = "spi", "spi_busclk0"; |
462 | status = "disabled"; | |
463 | }; | |
464 | ||
465 | spi_1: spi@12d30000 { | |
466 | compatible = "samsung,exynos4210-spi"; | |
467 | reg = <0x12d30000 0x100>; | |
e3b6c271 | 468 | interrupts = <0 69 0>; |
e84a2d91 LKA |
469 | dmas = <&pdma1 5 |
470 | &pdma1 4>; | |
471 | dma-names = "tx", "rx"; | |
472 | #address-cells = <1>; | |
473 | #size-cells = <0>; | |
474 | pinctrl-names = "default"; | |
475 | pinctrl-0 = <&spi1_bus>; | |
1dd4e599 | 476 | clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; |
e84a2d91 LKA |
477 | clock-names = "spi", "spi_busclk0"; |
478 | status = "disabled"; | |
479 | }; | |
480 | ||
481 | spi_2: spi@12d40000 { | |
482 | compatible = "samsung,exynos4210-spi"; | |
483 | reg = <0x12d40000 0x100>; | |
e3b6c271 | 484 | interrupts = <0 70 0>; |
e84a2d91 LKA |
485 | dmas = <&pdma0 7 |
486 | &pdma0 6>; | |
487 | dma-names = "tx", "rx"; | |
488 | #address-cells = <1>; | |
489 | #size-cells = <0>; | |
490 | pinctrl-names = "default"; | |
491 | pinctrl-0 = <&spi2_bus>; | |
1dd4e599 | 492 | clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; |
e84a2d91 LKA |
493 | clock-names = "spi", "spi_busclk0"; |
494 | status = "disabled"; | |
495 | }; | |
496 | ||
022cf308 LKA |
497 | pwm: pwm@12dd0000 { |
498 | compatible = "samsung,exynos4210-pwm"; | |
499 | reg = <0x12dd0000 0x100>; | |
500 | samsung,pwm-outputs = <0>, <1>, <2>, <3>; | |
501 | #pwm-cells = <3>; | |
1dd4e599 | 502 | clocks = <&clock CLK_PWM>; |
022cf308 LKA |
503 | clock-names = "timers"; |
504 | }; | |
505 | ||
1339d33a | 506 | dp_phy: video-phy@10040728 { |
e93e5454 VG |
507 | compatible = "samsung,exynos5420-dp-video-phy"; |
508 | samsung,pmu-syscon = <&pmu_system_controller>; | |
1339d33a VS |
509 | #phy-cells = <0>; |
510 | }; | |
511 | ||
dc9ec8cd YC |
512 | mipi_phy: video-phy@10040714 { |
513 | compatible = "samsung,s5pv210-mipi-video-phy"; | |
d1ed0d21 | 514 | syscon = <&pmu_system_controller>; |
dc9ec8cd YC |
515 | #phy-cells = <1>; |
516 | }; | |
517 | ||
5a8da524 YC |
518 | dsi@14500000 { |
519 | compatible = "samsung,exynos5410-mipi-dsi"; | |
520 | reg = <0x14500000 0x10000>; | |
521 | interrupts = <0 82 0>; | |
5a8da524 YC |
522 | phys = <&mipi_phy 1>; |
523 | phy-names = "dsim"; | |
524 | clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; | |
525 | clock-names = "bus_clk", "pll_clk"; | |
526 | #address-cells = <1>; | |
527 | #size-cells = <0>; | |
528 | status = "disabled"; | |
529 | }; | |
530 | ||
f408f9db NKC |
531 | adc: adc@12D10000 { |
532 | compatible = "samsung,exynos-adc-v2"; | |
db9bf4d6 | 533 | reg = <0x12D10000 0x100>; |
f408f9db | 534 | interrupts = <0 106 0>; |
1dd4e599 | 535 | clocks = <&clock CLK_TSADC>; |
f408f9db NKC |
536 | clock-names = "adc"; |
537 | #io-channel-cells = <1>; | |
538 | io-channel-ranges; | |
db9bf4d6 | 539 | samsung,syscon-phandle = <&pmu_system_controller>; |
f408f9db NKC |
540 | status = "disabled"; |
541 | }; | |
f49e347b AB |
542 | |
543 | i2c_0: i2c@12C60000 { | |
544 | compatible = "samsung,s3c2440-i2c"; | |
545 | reg = <0x12C60000 0x100>; | |
546 | interrupts = <0 56 0>; | |
547 | #address-cells = <1>; | |
548 | #size-cells = <0>; | |
1dd4e599 | 549 | clocks = <&clock CLK_I2C0>; |
f49e347b AB |
550 | clock-names = "i2c"; |
551 | pinctrl-names = "default"; | |
552 | pinctrl-0 = <&i2c0_bus>; | |
1888eb75 | 553 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
f49e347b AB |
554 | status = "disabled"; |
555 | }; | |
556 | ||
557 | i2c_1: i2c@12C70000 { | |
558 | compatible = "samsung,s3c2440-i2c"; | |
559 | reg = <0x12C70000 0x100>; | |
560 | interrupts = <0 57 0>; | |
561 | #address-cells = <1>; | |
562 | #size-cells = <0>; | |
1dd4e599 | 563 | clocks = <&clock CLK_I2C1>; |
f49e347b AB |
564 | clock-names = "i2c"; |
565 | pinctrl-names = "default"; | |
566 | pinctrl-0 = <&i2c1_bus>; | |
1888eb75 | 567 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
f49e347b AB |
568 | status = "disabled"; |
569 | }; | |
570 | ||
571 | i2c_2: i2c@12C80000 { | |
572 | compatible = "samsung,s3c2440-i2c"; | |
573 | reg = <0x12C80000 0x100>; | |
574 | interrupts = <0 58 0>; | |
575 | #address-cells = <1>; | |
576 | #size-cells = <0>; | |
1dd4e599 | 577 | clocks = <&clock CLK_I2C2>; |
f49e347b AB |
578 | clock-names = "i2c"; |
579 | pinctrl-names = "default"; | |
580 | pinctrl-0 = <&i2c2_bus>; | |
1888eb75 | 581 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
f49e347b AB |
582 | status = "disabled"; |
583 | }; | |
584 | ||
585 | i2c_3: i2c@12C90000 { | |
586 | compatible = "samsung,s3c2440-i2c"; | |
587 | reg = <0x12C90000 0x100>; | |
588 | interrupts = <0 59 0>; | |
589 | #address-cells = <1>; | |
590 | #size-cells = <0>; | |
1dd4e599 | 591 | clocks = <&clock CLK_I2C3>; |
f49e347b AB |
592 | clock-names = "i2c"; |
593 | pinctrl-names = "default"; | |
594 | pinctrl-0 = <&i2c3_bus>; | |
1888eb75 | 595 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
f49e347b AB |
596 | status = "disabled"; |
597 | }; | |
b0e505ce | 598 | |
1a9110d6 SK |
599 | hsi2c_4: i2c@12CA0000 { |
600 | compatible = "samsung,exynos5-hsi2c"; | |
601 | reg = <0x12CA0000 0x1000>; | |
602 | interrupts = <0 60 0>; | |
603 | #address-cells = <1>; | |
604 | #size-cells = <0>; | |
605 | pinctrl-names = "default"; | |
606 | pinctrl-0 = <&i2c4_hs_bus>; | |
faec151b | 607 | clocks = <&clock CLK_USI0>; |
1a9110d6 SK |
608 | clock-names = "hsi2c"; |
609 | status = "disabled"; | |
610 | }; | |
611 | ||
612 | hsi2c_5: i2c@12CB0000 { | |
613 | compatible = "samsung,exynos5-hsi2c"; | |
614 | reg = <0x12CB0000 0x1000>; | |
615 | interrupts = <0 61 0>; | |
616 | #address-cells = <1>; | |
617 | #size-cells = <0>; | |
618 | pinctrl-names = "default"; | |
619 | pinctrl-0 = <&i2c5_hs_bus>; | |
faec151b | 620 | clocks = <&clock CLK_USI1>; |
1a9110d6 SK |
621 | clock-names = "hsi2c"; |
622 | status = "disabled"; | |
623 | }; | |
624 | ||
625 | hsi2c_6: i2c@12CC0000 { | |
626 | compatible = "samsung,exynos5-hsi2c"; | |
627 | reg = <0x12CC0000 0x1000>; | |
628 | interrupts = <0 62 0>; | |
629 | #address-cells = <1>; | |
630 | #size-cells = <0>; | |
631 | pinctrl-names = "default"; | |
632 | pinctrl-0 = <&i2c6_hs_bus>; | |
faec151b | 633 | clocks = <&clock CLK_USI2>; |
1a9110d6 SK |
634 | clock-names = "hsi2c"; |
635 | status = "disabled"; | |
636 | }; | |
637 | ||
638 | hsi2c_7: i2c@12CD0000 { | |
639 | compatible = "samsung,exynos5-hsi2c"; | |
640 | reg = <0x12CD0000 0x1000>; | |
641 | interrupts = <0 63 0>; | |
642 | #address-cells = <1>; | |
643 | #size-cells = <0>; | |
644 | pinctrl-names = "default"; | |
645 | pinctrl-0 = <&i2c7_hs_bus>; | |
faec151b | 646 | clocks = <&clock CLK_USI3>; |
1a9110d6 SK |
647 | clock-names = "hsi2c"; |
648 | status = "disabled"; | |
649 | }; | |
650 | ||
651 | hsi2c_8: i2c@12E00000 { | |
652 | compatible = "samsung,exynos5-hsi2c"; | |
653 | reg = <0x12E00000 0x1000>; | |
654 | interrupts = <0 87 0>; | |
655 | #address-cells = <1>; | |
656 | #size-cells = <0>; | |
657 | pinctrl-names = "default"; | |
658 | pinctrl-0 = <&i2c8_hs_bus>; | |
faec151b | 659 | clocks = <&clock CLK_USI4>; |
1a9110d6 SK |
660 | clock-names = "hsi2c"; |
661 | status = "disabled"; | |
662 | }; | |
663 | ||
664 | hsi2c_9: i2c@12E10000 { | |
665 | compatible = "samsung,exynos5-hsi2c"; | |
666 | reg = <0x12E10000 0x1000>; | |
667 | interrupts = <0 88 0>; | |
668 | #address-cells = <1>; | |
669 | #size-cells = <0>; | |
670 | pinctrl-names = "default"; | |
671 | pinctrl-0 = <&i2c9_hs_bus>; | |
faec151b | 672 | clocks = <&clock CLK_USI5>; |
1a9110d6 SK |
673 | clock-names = "hsi2c"; |
674 | status = "disabled"; | |
675 | }; | |
676 | ||
677 | hsi2c_10: i2c@12E20000 { | |
678 | compatible = "samsung,exynos5-hsi2c"; | |
679 | reg = <0x12E20000 0x1000>; | |
680 | interrupts = <0 203 0>; | |
681 | #address-cells = <1>; | |
682 | #size-cells = <0>; | |
683 | pinctrl-names = "default"; | |
684 | pinctrl-0 = <&i2c10_hs_bus>; | |
faec151b | 685 | clocks = <&clock CLK_USI6>; |
1a9110d6 SK |
686 | clock-names = "hsi2c"; |
687 | status = "disabled"; | |
688 | }; | |
689 | ||
8e371a91 | 690 | hdmi: hdmi@14530000 { |
2963c554 | 691 | compatible = "samsung,exynos5420-hdmi"; |
b0e505ce RS |
692 | reg = <0x14530000 0x70000>; |
693 | interrupts = <0 95 0>; | |
1dd4e599 AH |
694 | clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, |
695 | <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, | |
696 | <&clock CLK_MOUT_HDMI>; | |
b0e505ce RS |
697 | clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", |
698 | "sclk_hdmiphy", "mout_hdmi"; | |
6ac189fc | 699 | phy = <&hdmiphy>; |
3a7e5dd5 | 700 | samsung,syscon-phandle = <&pmu_system_controller>; |
b0e505ce | 701 | status = "disabled"; |
ea08de16 | 702 | power-domains = <&disp_pd>; |
b0e505ce RS |
703 | }; |
704 | ||
6ac189fc RS |
705 | hdmiphy: hdmiphy@145D0000 { |
706 | reg = <0x145D0000 0x20>; | |
707 | }; | |
708 | ||
8e371a91 | 709 | mixer: mixer@14450000 { |
b0e505ce RS |
710 | compatible = "samsung,exynos5420-mixer"; |
711 | reg = <0x14450000 0x10000>; | |
712 | interrupts = <0 94 0>; | |
c950ea68 MS |
713 | clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, |
714 | <&clock CLK_SCLK_HDMI>; | |
715 | clock-names = "mixer", "hdmi", "sclk_hdmi"; | |
ea08de16 | 716 | power-domains = <&disp_pd>; |
b7004516 | 717 | iommus = <&sysmmu_tv>; |
b0e505ce | 718 | }; |
01eb4636 | 719 | |
e8769d3a MS |
720 | rotator: rotator@11C00000 { |
721 | compatible = "samsung,exynos5250-rotator"; | |
722 | reg = <0x11C00000 0x64>; | |
723 | interrupts = <0 84 0>; | |
724 | clocks = <&clock CLK_ROTATOR>; | |
725 | clock-names = "rotator"; | |
726 | iommus = <&sysmmu_rotator>; | |
727 | }; | |
728 | ||
01eb4636 LKA |
729 | gsc_0: video-scaler@13e00000 { |
730 | compatible = "samsung,exynos5-gsc"; | |
731 | reg = <0x13e00000 0x1000>; | |
732 | interrupts = <0 85 0>; | |
1dd4e599 | 733 | clocks = <&clock CLK_GSCL0>; |
01eb4636 | 734 | clock-names = "gscl"; |
0da65870 | 735 | power-domains = <&gsc_pd>; |
b7004516 | 736 | iommus = <&sysmmu_gscl0>; |
01eb4636 LKA |
737 | }; |
738 | ||
739 | gsc_1: video-scaler@13e10000 { | |
740 | compatible = "samsung,exynos5-gsc"; | |
741 | reg = <0x13e10000 0x1000>; | |
742 | interrupts = <0 86 0>; | |
1dd4e599 | 743 | clocks = <&clock CLK_GSCL1>; |
01eb4636 | 744 | clock-names = "gscl"; |
0da65870 | 745 | power-domains = <&gsc_pd>; |
b7004516 | 746 | iommus = <&sysmmu_gscl1>; |
01eb4636 | 747 | }; |
655de648 | 748 | |
15b7f087 AP |
749 | jpeg_0: jpeg@11F50000 { |
750 | compatible = "samsung,exynos5420-jpeg"; | |
751 | reg = <0x11F50000 0x1000>; | |
752 | interrupts = <0 89 0>; | |
753 | clock-names = "jpeg"; | |
754 | clocks = <&clock CLK_JPEG>; | |
b7004516 | 755 | iommus = <&sysmmu_jpeg0>; |
15b7f087 AP |
756 | }; |
757 | ||
758 | jpeg_1: jpeg@11F60000 { | |
759 | compatible = "samsung,exynos5420-jpeg"; | |
760 | reg = <0x11F60000 0x1000>; | |
761 | interrupts = <0 168 0>; | |
762 | clock-names = "jpeg"; | |
763 | clocks = <&clock CLK_JPEG2>; | |
b7004516 | 764 | iommus = <&sysmmu_jpeg1>; |
15b7f087 AP |
765 | }; |
766 | ||
c680036a LKA |
767 | pmu_system_controller: system-controller@10040000 { |
768 | compatible = "samsung,exynos5420-pmu", "syscon"; | |
769 | reg = <0x10040000 0x5000>; | |
d19bb397 TF |
770 | clock-names = "clkout16"; |
771 | clocks = <&clock CLK_FIN_PLL>; | |
772 | #clock-cells = <1>; | |
8b283c02 MZ |
773 | interrupt-controller; |
774 | #interrupt-cells = <3>; | |
775 | interrupt-parent = <&gic>; | |
c680036a LKA |
776 | }; |
777 | ||
dfbbdbf4 VG |
778 | sysreg_system_controller: syscon@10050000 { |
779 | compatible = "samsung,exynos5-sysreg", "syscon"; | |
780 | reg = <0x10050000 0x5000>; | |
781 | }; | |
782 | ||
655de648 NKC |
783 | tmu_cpu0: tmu@10060000 { |
784 | compatible = "samsung,exynos5420-tmu"; | |
785 | reg = <0x10060000 0x100>; | |
786 | interrupts = <0 65 0>; | |
1dd4e599 | 787 | clocks = <&clock CLK_TMU>; |
655de648 | 788 | clock-names = "tmu_apbif"; |
9843a223 | 789 | #include "exynos4412-tmu-sensor-conf.dtsi" |
655de648 NKC |
790 | }; |
791 | ||
792 | tmu_cpu1: tmu@10064000 { | |
793 | compatible = "samsung,exynos5420-tmu"; | |
794 | reg = <0x10064000 0x100>; | |
795 | interrupts = <0 183 0>; | |
1dd4e599 | 796 | clocks = <&clock CLK_TMU>; |
655de648 | 797 | clock-names = "tmu_apbif"; |
9843a223 | 798 | #include "exynos4412-tmu-sensor-conf.dtsi" |
655de648 NKC |
799 | }; |
800 | ||
801 | tmu_cpu2: tmu@10068000 { | |
802 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; | |
803 | reg = <0x10068000 0x100>, <0x1006c000 0x4>; | |
804 | interrupts = <0 184 0>; | |
1dd4e599 | 805 | clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; |
655de648 | 806 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; |
9843a223 | 807 | #include "exynos4412-tmu-sensor-conf.dtsi" |
655de648 NKC |
808 | }; |
809 | ||
810 | tmu_cpu3: tmu@1006c000 { | |
811 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; | |
812 | reg = <0x1006c000 0x100>, <0x100a0000 0x4>; | |
813 | interrupts = <0 185 0>; | |
1dd4e599 | 814 | clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; |
655de648 | 815 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; |
9843a223 | 816 | #include "exynos4412-tmu-sensor-conf.dtsi" |
655de648 NKC |
817 | }; |
818 | ||
819 | tmu_gpu: tmu@100a0000 { | |
820 | compatible = "samsung,exynos5420-tmu-ext-triminfo"; | |
821 | reg = <0x100a0000 0x100>, <0x10068000 0x4>; | |
822 | interrupts = <0 215 0>; | |
1dd4e599 | 823 | clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; |
655de648 | 824 | clock-names = "tmu_apbif", "tmu_triminfo_apbif"; |
9843a223 LM |
825 | #include "exynos4412-tmu-sensor-conf.dtsi" |
826 | }; | |
827 | ||
828 | thermal-zones { | |
829 | cpu0_thermal: cpu0-thermal { | |
830 | thermal-sensors = <&tmu_cpu0>; | |
831 | #include "exynos5420-trip-points.dtsi" | |
832 | }; | |
833 | cpu1_thermal: cpu1-thermal { | |
834 | thermal-sensors = <&tmu_cpu1>; | |
835 | #include "exynos5420-trip-points.dtsi" | |
836 | }; | |
837 | cpu2_thermal: cpu2-thermal { | |
838 | thermal-sensors = <&tmu_cpu2>; | |
839 | #include "exynos5420-trip-points.dtsi" | |
840 | }; | |
841 | cpu3_thermal: cpu3-thermal { | |
842 | thermal-sensors = <&tmu_cpu3>; | |
843 | #include "exynos5420-trip-points.dtsi" | |
844 | }; | |
845 | gpu_thermal: gpu-thermal { | |
846 | thermal-sensors = <&tmu_gpu>; | |
847 | #include "exynos5420-trip-points.dtsi" | |
848 | }; | |
655de648 | 849 | }; |
1d287620 | 850 | |
8e371a91 | 851 | watchdog: watchdog@101D0000 { |
1d287620 LKA |
852 | compatible = "samsung,exynos5420-wdt"; |
853 | reg = <0x101D0000 0x100>; | |
854 | interrupts = <0 42 0>; | |
1dd4e599 | 855 | clocks = <&clock CLK_WDT>; |
1d287620 LKA |
856 | clock-names = "watchdog"; |
857 | samsung,syscon-phandle = <&pmu_system_controller>; | |
858 | }; | |
183af252 | 859 | |
8e371a91 | 860 | sss: sss@10830000 { |
183af252 | 861 | compatible = "samsung,exynos4210-secss"; |
cb4f2d75 | 862 | reg = <0x10830000 0x300>; |
183af252 | 863 | interrupts = <0 112 0>; |
ab3a158c | 864 | clocks = <&clock CLK_SSS>; |
183af252 | 865 | clock-names = "secss"; |
183af252 | 866 | }; |
3cb7d1cd | 867 | |
f070267b VG |
868 | usbdrd3_0: usb@12000000 { |
869 | compatible = "samsung,exynos5250-dwusb3"; | |
870 | clocks = <&clock CLK_USBD300>; | |
871 | clock-names = "usbdrd30"; | |
872 | #address-cells = <1>; | |
873 | #size-cells = <1>; | |
874 | ranges; | |
875 | ||
e1c69efc | 876 | usbdrd_dwc3_0: dwc3 { |
f070267b VG |
877 | compatible = "snps,dwc3"; |
878 | reg = <0x12000000 0x10000>; | |
879 | interrupts = <0 72 0>; | |
880 | phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; | |
881 | phy-names = "usb2-phy", "usb3-phy"; | |
882 | }; | |
883 | }; | |
884 | ||
3cb7d1cd VG |
885 | usbdrd_phy0: phy@12100000 { |
886 | compatible = "samsung,exynos5420-usbdrd-phy"; | |
887 | reg = <0x12100000 0x100>; | |
888 | clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; | |
889 | clock-names = "phy", "ref"; | |
890 | samsung,pmu-syscon = <&pmu_system_controller>; | |
891 | #phy-cells = <1>; | |
892 | }; | |
893 | ||
f070267b VG |
894 | usbdrd3_1: usb@12400000 { |
895 | compatible = "samsung,exynos5250-dwusb3"; | |
896 | clocks = <&clock CLK_USBD301>; | |
897 | clock-names = "usbdrd30"; | |
898 | #address-cells = <1>; | |
899 | #size-cells = <1>; | |
900 | ranges; | |
901 | ||
e1c69efc | 902 | usbdrd_dwc3_1: dwc3 { |
f070267b VG |
903 | compatible = "snps,dwc3"; |
904 | reg = <0x12400000 0x10000>; | |
905 | interrupts = <0 73 0>; | |
906 | phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; | |
907 | phy-names = "usb2-phy", "usb3-phy"; | |
908 | }; | |
909 | }; | |
910 | ||
3cb7d1cd VG |
911 | usbdrd_phy1: phy@12500000 { |
912 | compatible = "samsung,exynos5420-usbdrd-phy"; | |
913 | reg = <0x12500000 0x100>; | |
914 | clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; | |
915 | clock-names = "phy", "ref"; | |
916 | samsung,pmu-syscon = <&pmu_system_controller>; | |
917 | #phy-cells = <1>; | |
918 | }; | |
8d53526f | 919 | |
6674fd92 VG |
920 | usbhost2: usb@12110000 { |
921 | compatible = "samsung,exynos4210-ehci"; | |
922 | reg = <0x12110000 0x100>; | |
923 | interrupts = <0 71 0>; | |
924 | ||
925 | clocks = <&clock CLK_USBH20>; | |
926 | clock-names = "usbhost"; | |
927 | #address-cells = <1>; | |
928 | #size-cells = <0>; | |
929 | port@0 { | |
930 | reg = <0>; | |
931 | phys = <&usb2_phy 1>; | |
932 | }; | |
933 | }; | |
934 | ||
935 | usbhost1: usb@12120000 { | |
936 | compatible = "samsung,exynos4210-ohci"; | |
937 | reg = <0x12120000 0x100>; | |
938 | interrupts = <0 71 0>; | |
939 | ||
940 | clocks = <&clock CLK_USBH20>; | |
941 | clock-names = "usbhost"; | |
942 | #address-cells = <1>; | |
943 | #size-cells = <0>; | |
944 | port@0 { | |
945 | reg = <0>; | |
946 | phys = <&usb2_phy 1>; | |
947 | }; | |
948 | }; | |
949 | ||
8d53526f VG |
950 | usb2_phy: phy@12130000 { |
951 | compatible = "samsung,exynos5250-usb2-phy"; | |
952 | reg = <0x12130000 0x100>; | |
953 | clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; | |
954 | clock-names = "phy", "ref"; | |
955 | #phy-cells = <1>; | |
956 | samsung,sysreg-phandle = <&sysreg_system_controller>; | |
957 | samsung,pmureg-phandle = <&pmu_system_controller>; | |
958 | }; | |
b7004516 MS |
959 | |
960 | sysmmu_g2dr: sysmmu@0x10A60000 { | |
961 | compatible = "samsung,exynos-sysmmu"; | |
962 | reg = <0x10A60000 0x1000>; | |
963 | interrupt-parent = <&combiner>; | |
964 | interrupts = <24 5>; | |
965 | clock-names = "sysmmu", "master"; | |
966 | clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; | |
967 | #iommu-cells = <0>; | |
968 | }; | |
969 | ||
970 | sysmmu_g2dw: sysmmu@0x10A70000 { | |
971 | compatible = "samsung,exynos-sysmmu"; | |
972 | reg = <0x10A70000 0x1000>; | |
973 | interrupt-parent = <&combiner>; | |
974 | interrupts = <22 2>; | |
975 | clock-names = "sysmmu", "master"; | |
976 | clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; | |
977 | #iommu-cells = <0>; | |
978 | }; | |
979 | ||
980 | sysmmu_tv: sysmmu@0x14650000 { | |
981 | compatible = "samsung,exynos-sysmmu"; | |
982 | reg = <0x14650000 0x1000>; | |
983 | interrupt-parent = <&combiner>; | |
984 | interrupts = <7 4>; | |
985 | clock-names = "sysmmu", "master"; | |
986 | clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; | |
987 | power-domains = <&disp_pd>; | |
988 | #iommu-cells = <0>; | |
989 | }; | |
990 | ||
991 | sysmmu_gscl0: sysmmu@0x13E80000 { | |
992 | compatible = "samsung,exynos-sysmmu"; | |
993 | reg = <0x13E80000 0x1000>; | |
994 | interrupt-parent = <&combiner>; | |
995 | interrupts = <2 0>; | |
996 | clock-names = "sysmmu", "master"; | |
997 | clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; | |
998 | power-domains = <&gsc_pd>; | |
999 | #iommu-cells = <0>; | |
1000 | }; | |
1001 | ||
1002 | sysmmu_gscl1: sysmmu@0x13E90000 { | |
1003 | compatible = "samsung,exynos-sysmmu"; | |
1004 | reg = <0x13E90000 0x1000>; | |
1005 | interrupt-parent = <&combiner>; | |
1006 | interrupts = <2 2>; | |
1007 | clock-names = "sysmmu", "master"; | |
1008 | clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; | |
1009 | power-domains = <&gsc_pd>; | |
1010 | #iommu-cells = <0>; | |
1011 | }; | |
1012 | ||
1013 | sysmmu_scaler0r: sysmmu@0x12880000 { | |
1014 | compatible = "samsung,exynos-sysmmu"; | |
1015 | reg = <0x12880000 0x1000>; | |
1016 | interrupt-parent = <&combiner>; | |
1017 | interrupts = <22 4>; | |
1018 | clock-names = "sysmmu", "master"; | |
1019 | clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; | |
1020 | #iommu-cells = <0>; | |
1021 | }; | |
1022 | ||
1023 | sysmmu_scaler1r: sysmmu@0x12890000 { | |
1024 | compatible = "samsung,exynos-sysmmu"; | |
1025 | reg = <0x12890000 0x1000>; | |
1026 | interrupts = <0 186 0>; | |
1027 | clock-names = "sysmmu", "master"; | |
1028 | clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; | |
1029 | #iommu-cells = <0>; | |
1030 | }; | |
1031 | ||
1032 | sysmmu_scaler2r: sysmmu@0x128A0000 { | |
1033 | compatible = "samsung,exynos-sysmmu"; | |
1034 | reg = <0x128A0000 0x1000>; | |
1035 | interrupts = <0 188 0>; | |
1036 | clock-names = "sysmmu", "master"; | |
1037 | clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; | |
1038 | #iommu-cells = <0>; | |
1039 | }; | |
1040 | ||
1041 | sysmmu_scaler0w: sysmmu@0x128C0000 { | |
1042 | compatible = "samsung,exynos-sysmmu"; | |
1043 | reg = <0x128C0000 0x1000>; | |
1044 | interrupt-parent = <&combiner>; | |
1045 | interrupts = <27 2>; | |
1046 | clock-names = "sysmmu", "master"; | |
1047 | clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; | |
1048 | #iommu-cells = <0>; | |
1049 | }; | |
1050 | ||
1051 | sysmmu_scaler1w: sysmmu@0x128D0000 { | |
1052 | compatible = "samsung,exynos-sysmmu"; | |
1053 | reg = <0x128D0000 0x1000>; | |
1054 | interrupt-parent = <&combiner>; | |
1055 | interrupts = <22 6>; | |
1056 | clock-names = "sysmmu", "master"; | |
1057 | clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; | |
1058 | #iommu-cells = <0>; | |
1059 | }; | |
1060 | ||
1061 | sysmmu_scaler2w: sysmmu@0x128E0000 { | |
1062 | compatible = "samsung,exynos-sysmmu"; | |
1063 | reg = <0x128E0000 0x1000>; | |
1064 | interrupt-parent = <&combiner>; | |
1065 | interrupts = <19 6>; | |
1066 | clock-names = "sysmmu", "master"; | |
1067 | clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; | |
1068 | #iommu-cells = <0>; | |
1069 | }; | |
1070 | ||
e8769d3a MS |
1071 | sysmmu_rotator: sysmmu@0x11D40000 { |
1072 | compatible = "samsung,exynos-sysmmu"; | |
1073 | reg = <0x11D40000 0x1000>; | |
1074 | interrupt-parent = <&combiner>; | |
1075 | interrupts = <4 0>; | |
1076 | clock-names = "sysmmu", "master"; | |
1077 | clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; | |
1078 | #iommu-cells = <0>; | |
1079 | }; | |
1080 | ||
b7004516 MS |
1081 | sysmmu_jpeg0: sysmmu@0x11F10000 { |
1082 | compatible = "samsung,exynos-sysmmu"; | |
1083 | reg = <0x11F10000 0x1000>; | |
1084 | interrupt-parent = <&combiner>; | |
1085 | interrupts = <4 2>; | |
1086 | clock-names = "sysmmu", "master"; | |
1087 | clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; | |
1088 | #iommu-cells = <0>; | |
1089 | }; | |
1090 | ||
1091 | sysmmu_jpeg1: sysmmu@0x11F20000 { | |
1092 | compatible = "samsung,exynos-sysmmu"; | |
1093 | reg = <0x11F20000 0x1000>; | |
1094 | interrupts = <0 169 0>; | |
1095 | clock-names = "sysmmu", "master"; | |
1096 | clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; | |
1097 | #iommu-cells = <0>; | |
1098 | }; | |
1099 | ||
1100 | sysmmu_mfc_l: sysmmu@0x11200000 { | |
1101 | compatible = "samsung,exynos-sysmmu"; | |
1102 | reg = <0x11200000 0x1000>; | |
1103 | interrupt-parent = <&combiner>; | |
1104 | interrupts = <6 2>; | |
1105 | clock-names = "sysmmu", "master"; | |
1106 | clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; | |
1107 | power-domains = <&mfc_pd>; | |
1108 | #iommu-cells = <0>; | |
1109 | }; | |
1110 | ||
1111 | sysmmu_mfc_r: sysmmu@0x11210000 { | |
1112 | compatible = "samsung,exynos-sysmmu"; | |
1113 | reg = <0x11210000 0x1000>; | |
1114 | interrupt-parent = <&combiner>; | |
1115 | interrupts = <8 5>; | |
1116 | clock-names = "sysmmu", "master"; | |
1117 | clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; | |
1118 | power-domains = <&mfc_pd>; | |
1119 | #iommu-cells = <0>; | |
1120 | }; | |
1121 | ||
1122 | sysmmu_fimd1_0: sysmmu@0x14640000 { | |
1123 | compatible = "samsung,exynos-sysmmu"; | |
1124 | reg = <0x14640000 0x1000>; | |
1125 | interrupt-parent = <&combiner>; | |
1126 | interrupts = <3 2>; | |
1127 | clock-names = "sysmmu", "master"; | |
1128 | clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; | |
1129 | power-domains = <&disp_pd>; | |
1130 | #iommu-cells = <0>; | |
1131 | }; | |
1132 | ||
1133 | sysmmu_fimd1_1: sysmmu@0x14680000 { | |
1134 | compatible = "samsung,exynos-sysmmu"; | |
1135 | reg = <0x14680000 0x1000>; | |
1136 | interrupt-parent = <&combiner>; | |
1137 | interrupts = <3 0>; | |
1138 | clock-names = "sysmmu", "master"; | |
c7d2ecd9 | 1139 | clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; |
b7004516 MS |
1140 | power-domains = <&disp_pd>; |
1141 | #iommu-cells = <0>; | |
1142 | }; | |
34dcedfb | 1143 | }; |
3a3cf6c4 KK |
1144 | |
1145 | &dp { | |
1146 | clocks = <&clock CLK_DP1>; | |
1147 | clock-names = "dp"; | |
1148 | phys = <&dp_phy>; | |
1149 | phy-names = "dp"; | |
1150 | power-domains = <&disp_pd>; | |
1151 | }; | |
1152 | ||
1153 | &fimd { | |
1154 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; | |
1155 | clock-names = "sclk_fimd", "fimd"; | |
1156 | power-domains = <&disp_pd>; | |
b7004516 MS |
1157 | iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>; |
1158 | iommu-names = "m0", "m1"; | |
3a3cf6c4 KK |
1159 | }; |
1160 | ||
1161 | &rtc { | |
1162 | clocks = <&clock CLK_RTC>; | |
1163 | clock-names = "rtc"; | |
1164 | interrupt-parent = <&pmu_system_controller>; | |
1165 | status = "disabled"; | |
1166 | }; | |
1167 | ||
1168 | &serial_0 { | |
1169 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; | |
1170 | clock-names = "uart", "clk_uart_baud0"; | |
1171 | }; | |
1172 | ||
1173 | &serial_1 { | |
1174 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; | |
1175 | clock-names = "uart", "clk_uart_baud0"; | |
1176 | }; | |
1177 | ||
1178 | &serial_2 { | |
1179 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; | |
1180 | clock-names = "uart", "clk_uart_baud0"; | |
1181 | }; | |
1182 | ||
1183 | &serial_3 { | |
1184 | clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; | |
1185 | clock-names = "uart", "clk_uart_baud0"; | |
1186 | }; | |
c07f8270 JMC |
1187 | |
1188 | #include "exynos5420-pinctrl.dtsi" |