[deliverable/linux.git] / arch / arm / boot / dts / exynos5440.dtsi

/*
 * SAMSUNG EXYNOS5440 SoC device tree source
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <dt-bindings/clock/exynos5440.h>
#include "skeleton.dtsi"

/ {
	compatible = "samsung,exynos5440", "samsung,exynos5";

	interrupt-parent = <&gic>;

	aliases {
		spi0 = &spi_0;
		tmuctrl0 = &tmuctrl_0;
		tmuctrl1 = &tmuctrl_1;
		tmuctrl2 = &tmuctrl_2;
	};

	clock: clock-controller@160000 {
		compatible = "samsung,exynos5440-clock";
		reg = <0x160000 0x1000>;
		#clock-cells = <1>;
	};

	gic: interrupt-controller@2E0000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg =	<0x2E1000 0x1000>,
			<0x2E2000 0x1000>,
			<0x2E4000 0x2000>,
			<0x2E6000 0x2000>;
		interrupts = <1 9 0xf04>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <3>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
		interrupts = <0 52 4>,
			     <0 53 4>,
			     <0 54 4>,
			     <0 55 4>;
	};

	timer {
		compatible = "arm,cortex-a15-timer",
			     "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
		clock-frequency = <50000000>;
	};

	cpufreq@160000 {
		compatible = "samsung,exynos5440-cpufreq";
		reg = <0x160000 0x1000>;
		interrupts = <0 57 0>;
		operating-points = <
				/* KHz	  uV */
				1500000 1100000
				1400000 1075000
				1300000 1050000
				1200000 1025000
				1100000 1000000
				1000000 975000
				900000  950000
				800000  925000
		>;
	};

	serial@B0000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0xB0000 0x1000>;
		interrupts = <0 2 0>;
		clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
		clock-names = "uart", "clk_uart_baud0";
	};

	serial@C0000 {
		compatible = "samsung,exynos4210-uart";
		reg = <0xC0000 0x1000>;
		interrupts = <0 3 0>;
		clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
		clock-names = "uart", "clk_uart_baud0";
	};

	spi_0: spi@D0000 {
		compatible = "samsung,exynos5440-spi";
		reg = <0xD0000 0x100>;
		interrupts = <0 4 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		samsung,spi-src-clk = <0>;
		num-cs = <1>;
		clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
		clock-names = "spi", "spi_busclk0";
	};

	pin_ctrl: pinctrl {
		compatible = "samsung,exynos5440-pinctrl";
		reg = <0xE0000 0x1000>;
		interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
			     <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
		interrupt-controller;
		#interrupt-cells = <2>;
		#gpio-cells = <2>;

		fan: fan {
			samsung,exynos5440-pin-function = <1>;
		};

		hdd_led0: hdd_led0 {
			samsung,exynos5440-pin-function = <2>;
		};

		hdd_led1: hdd_led1 {
			samsung,exynos5440-pin-function = <3>;
		};

		uart1: uart1 {
			samsung,exynos5440-pin-function = <4>;
		};
	};

	i2c@F0000 {
		compatible = "samsung,exynos5440-i2c";
		reg = <0xF0000 0x1000>;
		interrupts = <0 5 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "i2c";
	};

	i2c@100000 {
		compatible = "samsung,exynos5440-i2c";
		reg = <0x100000 0x1000>;
		interrupts = <0 6 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "i2c";
	};

	watchdog@110000 {
		compatible = "samsung,s3c2410-wdt";
		reg = <0x110000 0x1000>;
		interrupts = <0 1 0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "watchdog";
	};

	gmac: ethernet@00230000 {
		compatible = "snps,dwmac-3.70a";
		reg = <0x00230000 0x8000>;
		interrupt-parent = <&gic>;
		interrupts = <0 31 4>;
		interrupt-names = "macirq";
		phy-mode = "sgmii";
		clocks = <&clock CLK_GMAC0>;
		clock-names = "stmmaceth";
	};

	amba {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "arm,amba-bus";
		interrupt-parent = <&gic>;
		ranges;
	};

	rtc {
		compatible = "samsung,s3c6410-rtc";
		reg = <0x130000 0x1000>;
		interrupts = <0 17 0>, <0 16 0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "rtc";
	};

	tmuctrl_0: tmuctrl@160118 {
		compatible = "samsung,exynos5440-tmu";
		reg = <0x160118 0x230>, <0x160368 0x10>;
		interrupts = <0 58 0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "tmu_apbif";
	};

	tmuctrl_1: tmuctrl@16011C {
		compatible = "samsung,exynos5440-tmu";
		reg = <0x16011C 0x230>, <0x160368 0x10>;
		interrupts = <0 58 0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "tmu_apbif";
	};

	tmuctrl_2: tmuctrl@160120 {
		compatible = "samsung,exynos5440-tmu";
		reg = <0x160120 0x230>, <0x160368 0x10>;
		interrupts = <0 58 0>;
		clocks = <&clock CLK_B_125>;
		clock-names = "tmu_apbif";
	};

	sata@210000 {
		compatible = "snps,exynos5440-ahci";
		reg = <0x210000 0x10000>;
		interrupts = <0 30 0>;
		clocks = <&clock CLK_SATA>;
		clock-names = "sata";
	};

	ohci@220000 {
		compatible = "samsung,exynos5440-ohci";
		reg = <0x220000 0x1000>;
		interrupts = <0 29 0>;
		clocks = <&clock CLK_USB>;
		clock-names = "usbhost";
	};

	ehci@221000 {
		compatible = "samsung,exynos5440-ehci";
		reg = <0x221000 0x1000>;
		interrupts = <0 29 0>;
		clocks = <&clock CLK_USB>;
		clock-names = "usbhost";
	};

	pcie@290000 {
		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
		reg = <0x290000 0x1000
			0x270000 0x1000
			0x271000 0x40>;
		interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
		clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
		clock-names = "pcie", "pcie_bus";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */
			  0x81000000 0 0	  0x40001000 0 0x00010000   /* downstream I/O */
			  0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0x0 0 &gic 53>;
		num-lanes = <4>;
		status = "disabled";
	};

	pcie@2a0000 {
		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
		reg = <0x2a0000 0x1000
			0x272000 0x1000
			0x271040 0x40>;
		interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
		clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
		clock-names = "pcie", "pcie_bus";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */
			  0x81000000 0 0	  0x60001000 0 0x00010000   /* downstream I/O */
			  0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0x0 0 &gic 56>;
		num-lanes = <4>;
		status = "disabled";
	};
};
Commit	Line	Data
1355bbc4 KK	1	/*
	2	* SAMSUNG EXYNOS5440 SoC device tree source
	3	*
	4	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
86feafeb	12	#include <dt-bindings/clock/exynos5440.h>
3799279f	13	#include "skeleton.dtsi"
1355bbc4 KK	14
1355bbc4 KK	15	/ {
8bdb31b4	16	compatible = "samsung,exynos5440", "samsung,exynos5";
1355bbc4 KK	17
	18	interrupt-parent = <&gic>;
	19
dabd3f9d G	20	aliases {
dabd3f9d G	21	spi0 = &spi_0;
5c7311b5 ADK	22	tmuctrl0 = &tmuctrl_0;
	23	tmuctrl1 = &tmuctrl_1;
	24	tmuctrl2 = &tmuctrl_2;
dabd3f9d G	25	};
dabd3f9d G	26
644a79a8	27	clock: clock-controller@160000 {
d8bafc87 TA	28	compatible = "samsung,exynos5440-clock";
	29	reg = <0x160000 0x1000>;
	30	#clock-cells = <1>;
	31	};
	32
0572b725	33	gic: interrupt-controller@2E0000 {
1355bbc4 KK	34	compatible = "arm,cortex-a15-gic";
	35	#interrupt-cells = <3>;
	36	interrupt-controller;
3279dd36 GM	37	reg = <0x2E1000 0x1000>,
	38	<0x2E2000 0x1000>,
	39	<0x2E4000 0x2000>,
	40	<0x2E6000 0x2000>;
	41	interrupts = <1 9 0xf04>;
1355bbc4 KK	42	};
	43
	44	cpus {
f5108e1c KK	45	#address-cells = <1>;
	46	#size-cells = <0>;
	47
1355bbc4	48	cpu@0 {
88e41848	49	device_type = "cpu";
1355bbc4	50	compatible = "arm,cortex-a15";
f5108e1c	51	reg = <0>;
1355bbc4 KK	52	};
1355bbc4 KK	53	cpu@1 {
88e41848	54	device_type = "cpu";
1355bbc4	55	compatible = "arm,cortex-a15";
f5108e1c	56	reg = <1>;
1355bbc4 KK	57	};
1355bbc4 KK	58	cpu@2 {
88e41848	59	device_type = "cpu";
1355bbc4	60	compatible = "arm,cortex-a15";
f5108e1c	61	reg = <2>;
1355bbc4 KK	62	};
1355bbc4 KK	63	cpu@3 {
88e41848	64	device_type = "cpu";
1355bbc4	65	compatible = "arm,cortex-a15";
f5108e1c	66	reg = <3>;
1355bbc4 KK	67	};
	68	};
	69
4c46f51a SP	70	arm-pmu {
	71	compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
	72	interrupts = <0 52 4>,
	73	<0 53 4>,
	74	<0 54 4>,
	75	<0 55 4>;
	76	};
	77
f5108e1c KK	78	timer {
	79	compatible = "arm,cortex-a15-timer",
	80	"arm,armv7-timer";
	81	interrupts = <1 13 0xf08>,
	82	<1 14 0xf08>,
	83	<1 11 0xf08>,
	84	<1 10 0xf08>;
	85	clock-frequency = <50000000>;
	86	};
	87
7f7b8ed0 ADK	88	cpufreq@160000 {
	89	compatible = "samsung,exynos5440-cpufreq";
	90	reg = <0x160000 0x1000>;
	91	interrupts = <0 57 0>;
	92	operating-points = <
	93	/* KHz uV */
afbbf927 ADK	94	1500000 1100000
	95	1400000 1075000
	96	1300000 1050000
7f7b8ed0	97	1200000 1025000
afbbf927	98	1100000 1000000
7f7b8ed0	99	1000000 975000
afbbf927	100	900000 950000
7f7b8ed0 ADK	101	800000 925000
	102	>;
	103	};
	104
1355bbc4 KK	105	serial@B0000 {
	106	compatible = "samsung,exynos4210-uart";
	107	reg = <0xB0000 0x1000>;
	108	interrupts = <0 2 0>;
86feafeb	109	clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
6a0338c2	110	clock-names = "uart", "clk_uart_baud0";
1355bbc4 KK	111	};
	112
	113	serial@C0000 {
	114	compatible = "samsung,exynos4210-uart";
	115	reg = <0xC0000 0x1000>;
	116	interrupts = <0 3 0>;
86feafeb	117	clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
6a0338c2	118	clock-names = "uart", "clk_uart_baud0";
1355bbc4 KK	119	};
1355bbc4 KK	120
dabd3f9d G	121	spi_0: spi@D0000 {
	122	compatible = "samsung,exynos5440-spi";
	123	reg = <0xD0000 0x100>;
1355bbc4	124	interrupts = <0 4 0>;
1355bbc4 KK	125	#address-cells = <1>;
1355bbc4 KK	126	#size-cells = <0>;
dabd3f9d G	127	samsung,spi-src-clk = <0>;
dabd3f9d G	128	num-cs = <1>;
86feafeb	129	clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
6a0338c2	130	clock-names = "spi", "spi_busclk0";
1355bbc4 KK	131	};
1355bbc4 KK	132
b342e64c	133	pin_ctrl: pinctrl {
f6925432	134	compatible = "samsung,exynos5440-pinctrl";
1355bbc4	135	reg = <0xE0000 0x1000>;
71d87da3 TA	136	interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
71d87da3 TA	137	<0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
1355bbc4 KK	138	interrupt-controller;
1355bbc4 KK	139	#interrupt-cells = <2>;
b1ce101b TA	140	#gpio-cells = <2>;
	141
	142	fan: fan {
	143	samsung,exynos5440-pin-function = <1>;
	144	};
	145
	146	hdd_led0: hdd_led0 {
	147	samsung,exynos5440-pin-function = <2>;
	148	};
	149
	150	hdd_led1: hdd_led1 {
	151	samsung,exynos5440-pin-function = <3>;
	152	};
	153
	154	uart1: uart1 {
	155	samsung,exynos5440-pin-function = <4>;
	156	};
1355bbc4 KK	157	};
	158
	159	i2c@F0000 {
49498c56	160	compatible = "samsung,exynos5440-i2c";
1355bbc4 KK	161	reg = <0xF0000 0x1000>;
	162	interrupts = <0 5 0>;
	163	#address-cells = <1>;
	164	#size-cells = <0>;
86feafeb	165	clocks = <&clock CLK_B_125>;
6a0338c2	166	clock-names = "i2c";
1355bbc4 KK	167	};
	168
	169	i2c@100000 {
49498c56	170	compatible = "samsung,exynos5440-i2c";
1355bbc4 KK	171	reg = <0x100000 0x1000>;
	172	interrupts = <0 6 0>;
	173	#address-cells = <1>;
	174	#size-cells = <0>;
86feafeb	175	clocks = <&clock CLK_B_125>;
6a0338c2	176	clock-names = "i2c";
1355bbc4 KK	177	};
1355bbc4 KK	178
64f5d1eb	179	watchdog@110000 {
1355bbc4 KK	180	compatible = "samsung,s3c2410-wdt";
	181	reg = <0x110000 0x1000>;
	182	interrupts = <0 1 0>;
86feafeb	183	clocks = <&clock CLK_B_125>;
6a0338c2	184	clock-names = "watchdog";
1355bbc4 KK	185	};
1355bbc4 KK	186
c038c4d8 BA	187	gmac: ethernet@00230000 {
	188	compatible = "snps,dwmac-3.70a";
	189	reg = <0x00230000 0x8000>;
	190	interrupt-parent = <&gic>;
	191	interrupts = <0 31 4>;
	192	interrupt-names = "macirq";
	193	phy-mode = "sgmii";
86feafeb	194	clocks = <&clock CLK_GMAC0>;
c038c4d8 BA	195	clock-names = "stmmaceth";
	196	};
	197
1355bbc4 KK	198	amba {
	199	#address-cells = <1>;
	200	#size-cells = <1>;
	201	compatible = "arm,amba-bus";
	202	interrupt-parent = <&gic>;
	203	ranges;
1355bbc4 KK	204	};
	205
	206	rtc {
	207	compatible = "samsung,s3c6410-rtc";
	208	reg = <0x130000 0x1000>;
e877a5aa	209	interrupts = <0 17 0>, <0 16 0>;
86feafeb	210	clocks = <&clock CLK_B_125>;
6a0338c2	211	clock-names = "rtc";
1355bbc4	212	};
1a12f52e	213
5c7311b5 ADK	214	tmuctrl_0: tmuctrl@160118 {
	215	compatible = "samsung,exynos5440-tmu";
	216	reg = <0x160118 0x230>, <0x160368 0x10>;
	217	interrupts = <0 58 0>;
86feafeb	218	clocks = <&clock CLK_B_125>;
5c7311b5 ADK	219	clock-names = "tmu_apbif";
	220	};
	221
	222	tmuctrl_1: tmuctrl@16011C {
	223	compatible = "samsung,exynos5440-tmu";
	224	reg = <0x16011C 0x230>, <0x160368 0x10>;
	225	interrupts = <0 58 0>;
86feafeb	226	clocks = <&clock CLK_B_125>;
5c7311b5 ADK	227	clock-names = "tmu_apbif";
	228	};
	229
	230	tmuctrl_2: tmuctrl@160120 {
	231	compatible = "samsung,exynos5440-tmu";
	232	reg = <0x160120 0x230>, <0x160368 0x10>;
	233	interrupts = <0 58 0>;
86feafeb	234	clocks = <&clock CLK_B_125>;
5c7311b5 ADK	235	clock-names = "tmu_apbif";
	236	};
	237
1a12f52e G	238	sata@210000 {
	239	compatible = "snps,exynos5440-ahci";
	240	reg = <0x210000 0x10000>;
	241	interrupts = <0 30 0>;
86feafeb	242	clocks = <&clock CLK_SATA>;
1a12f52e G	243	clock-names = "sata";
	244	};
	245
a3808905 TA	246	ohci@220000 {
	247	compatible = "samsung,exynos5440-ohci";
	248	reg = <0x220000 0x1000>;
	249	interrupts = <0 29 0>;
86feafeb	250	clocks = <&clock CLK_USB>;
a3808905 TA	251	clock-names = "usbhost";
	252	};
	253
	254	ehci@221000 {
	255	compatible = "samsung,exynos5440-ehci";
	256	reg = <0x221000 0x1000>;
	257	interrupts = <0 29 0>;
86feafeb	258	clocks = <&clock CLK_USB>;
a3808905	259	clock-names = "usbhost";
1355bbc4	260	};
406a9324 JH	261
	262	pcie@290000 {
	263	compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
	264	reg = <0x290000 0x1000
	265	0x270000 0x1000
	266	0x271000 0x40>;
	267	interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
86feafeb	268	clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
406a9324 JH	269	clock-names = "pcie", "pcie_bus";
	270	#address-cells = <3>;
	271	#size-cells = <2>;
	272	device_type = "pci";
	273	ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
	274	0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
	275	0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
	276	#interrupt-cells = <1>;
	277	interrupt-map-mask = <0 0 0 0>;
	278	interrupt-map = <0x0 0 &gic 53>;
4b1ced84	279	num-lanes = <4>;
331d7d6a	280	status = "disabled";
406a9324 JH	281	};
	282
	283	pcie@2a0000 {
	284	compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
	285	reg = <0x2a0000 0x1000
	286	0x272000 0x1000
	287	0x271040 0x40>;
	288	interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
86feafeb	289	clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
406a9324 JH	290	clock-names = "pcie", "pcie_bus";
	291	#address-cells = <3>;
	292	#size-cells = <2>;
	293	device_type = "pci";
	294	ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
	295	0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
	296	0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
	297	#interrupt-cells = <1>;
	298	interrupt-map-mask = <0 0 0 0>;
	299	interrupt-map = <0x0 0 &gic 56>;
4b1ced84	300	num-lanes = <4>;
331d7d6a	301	status = "disabled";
406a9324	302	};
1355bbc4	303	};