[deliverable/linux.git] / arch / arm / boot / dts / highbank.dts

/*
 * Copyright 2011-2012 Calxeda, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

/dts-v1/;

/* First 4KB has pen for secondary cores. */
/memreserve/ 0x00000000 0x0001000;

/ {
	model = "Calxeda Highbank";
	compatible = "calxeda,highbank";
	#address-cells = <1>;
	#size-cells = <1>;
	clock-ranges;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			reg = <0>;
			next-level-cache = <&L2>;
			clocks = <&a9pll>;
			clock-names = "cpu";
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			reg = <1>;
			next-level-cache = <&L2>;
			clocks = <&a9pll>;
			clock-names = "cpu";
		};

		cpu@2 {
			compatible = "arm,cortex-a9";
			reg = <2>;
			next-level-cache = <&L2>;
			clocks = <&a9pll>;
			clock-names = "cpu";
		};

		cpu@3 {
			compatible = "arm,cortex-a9";
			reg = <3>;
			next-level-cache = <&L2>;
			clocks = <&a9pll>;
			clock-names = "cpu";
		};
	};

	memory {
		name = "memory";
		device_type = "memory";
		reg = <0x00000000 0xff900000>;
	};

	soc {
		ranges = <0x00000000 0x00000000 0xffffffff>;

		timer@fff10600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xfff10600 0x20>;
			interrupts = <1 13 0xf01>;
			clocks = <&a9periphclk>;
		};

		watchdog@fff10620 {
			compatible = "arm,cortex-a9-twd-wdt";
			reg = <0xfff10620 0x20>;
			interrupts = <1 14 0xf01>;
			clocks = <&a9periphclk>;
		};

		intc: interrupt-controller@fff11000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#size-cells = <0>;
			#address-cells = <1>;
			interrupt-controller;
			reg = <0xfff11000 0x1000>,
			      <0xfff10100 0x100>;
		};

		L2: l2-cache {
			compatible = "arm,pl310-cache";
			reg = <0xfff12000 0x1000>;
			interrupts = <0 70 4>;
			cache-unified;
			cache-level = <2>;
		};

		pmu {
			compatible = "arm,cortex-a9-pmu";
			interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
		};


		sregs@fff3c200 {
			compatible = "calxeda,hb-sregs-l2-ecc";
			reg = <0xfff3c200 0x100>;
			interrupts = <0 71 4  0 72 4>;
		};

	};
};

/include/ "ecx-common.dtsi"
Commit	Line	Data
253d7add	1	/*
8d4d9f52	2	* Copyright 2011-2012 Calxeda, Inc.
253d7add RH	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License along with
	14	* this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	/dts-v1/;
	18
	19	/* First 4KB has pen for secondary cores. */
	20	/memreserve/ 0x00000000 0x0001000;
	21
	22	/ {
	23	model = "Calxeda Highbank";
	24	compatible = "calxeda,highbank";
	25	#address-cells = <1>;
	26	#size-cells = <1>;
8d4d9f52	27	clock-ranges;
253d7add RH	28
	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
	33	cpu@0 {
	34	compatible = "arm,cortex-a9";
	35	reg = <0>;
	36	next-level-cache = <&L2>;
8d4d9f52 RH	37	clocks = <&a9pll>;
8d4d9f52 RH	38	clock-names = "cpu";
253d7add RH	39	};
	40
	41	cpu@1 {
	42	compatible = "arm,cortex-a9";
	43	reg = <1>;
	44	next-level-cache = <&L2>;
8d4d9f52 RH	45	clocks = <&a9pll>;
8d4d9f52 RH	46	clock-names = "cpu";
253d7add RH	47	};
	48
	49	cpu@2 {
	50	compatible = "arm,cortex-a9";
	51	reg = <2>;
	52	next-level-cache = <&L2>;
8d4d9f52 RH	53	clocks = <&a9pll>;
8d4d9f52 RH	54	clock-names = "cpu";
253d7add RH	55	};
	56
	57	cpu@3 {
	58	compatible = "arm,cortex-a9";
	59	reg = <3>;
	60	next-level-cache = <&L2>;
8d4d9f52 RH	61	clocks = <&a9pll>;
8d4d9f52 RH	62	clock-names = "cpu";
253d7add RH	63	};
	64	};
	65
	66	memory {
	67	name = "memory";
	68	device_type = "memory";
	69	reg = <0x00000000 0xff900000>;
	70	};
	71
253d7add	72	soc {
7d6ab9b8	73	ranges = <0x00000000 0x00000000 0xffffffff>;
253d7add RH	74
253d7add RH	75	timer@fff10600 {
7ac9b9eb	76	compatible = "arm,cortex-a9-twd-timer";
253d7add	77	reg = <0xfff10600 0x20>;
7ac9b9eb	78	interrupts = <1 13 0xf01>;
8d4d9f52	79	clocks = <&a9periphclk>;
253d7add RH	80	};
	81
	82	watchdog@fff10620 {
7ac9b9eb	83	compatible = "arm,cortex-a9-twd-wdt";
253d7add	84	reg = <0xfff10620 0x20>;
7ac9b9eb	85	interrupts = <1 14 0xf01>;
8d4d9f52	86	clocks = <&a9periphclk>;
253d7add RH	87	};
	88
	89	intc: interrupt-controller@fff11000 {
	90	compatible = "arm,cortex-a9-gic";
	91	#interrupt-cells = <3>;
	92	#size-cells = <0>;
	93	#address-cells = <1>;
	94	interrupt-controller;
253d7add RH	95	reg = <0xfff11000 0x1000>,
	96	<0xfff10100 0x100>;
	97	};
	98
	99	L2: l2-cache {
	100	compatible = "arm,pl310-cache";
	101	reg = <0xfff12000 0x1000>;
	102	interrupts = <0 70 4>;
	103	cache-unified;
	104	cache-level = <2>;
	105	};
	106
	107	pmu {
	108	compatible = "arm,cortex-a9-pmu";
	109	interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
	110	};
	111
253d7add	112
69154d06 RH	113	sregs@fff3c200 {
	114	compatible = "calxeda,hb-sregs-l2-ecc";
	115	reg = <0xfff3c200 0x100>;
	116	interrupts = <0 71 4 0 72 4>;
	117	};
	118
253d7add RH	119	};
253d7add RH	120	};
7d6ab9b8 RH	121
7d6ab9b8 RH	122	/include/ "ecx-common.dtsi"