[deliverable/linux.git] / arch / arm / boot / dts / hip04.dtsi

/*
 * Hisilicon Ltd. HiP04 SoC
 *
 * Copyright (C) 2013-2014 Hisilicon Ltd.
 * Copyright (C) 2013-2014 Linaro Ltd.
 *
 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/ {
	/* memory bus is 64-bit */
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
	};

	bootwrapper {
		compatible = "hisilicon,hip04-bootwrapper";
		boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};
				core1 {
					cpu = <&CPU1>;
				};
				core2 {
					cpu = <&CPU2>;
				};
				core3 {
					cpu = <&CPU3>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};
				core1 {
					cpu = <&CPU5>;
				};
				core2 {
					cpu = <&CPU6>;
				};
				core3 {
					cpu = <&CPU7>;
				};
			};
			cluster2 {
				core0 {
					cpu = <&CPU8>;
				};
				core1 {
					cpu = <&CPU9>;
				};
				core2 {
					cpu = <&CPU10>;
				};
				core3 {
					cpu = <&CPU11>;
				};
			};
			cluster3 {
				core0 {
					cpu = <&CPU12>;
				};
				core1 {
					cpu = <&CPU13>;
				};
				core2 {
					cpu = <&CPU14>;
				};
				core3 {
					cpu = <&CPU15>;
				};
			};
		};
		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};
		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
		};
		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <2>;
		};
		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <3>;
		};
		CPU4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x100>;
		};
		CPU5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x101>;
		};
		CPU6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x102>;
		};
		CPU7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x103>;
		};
		CPU8: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x200>;
		};
		CPU9: cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x201>;
		};
		CPU10: cpu@202 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x202>;
		};
		CPU11: cpu@203 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x203>;
		};
		CPU12: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x300>;
		};
		CPU13: cpu@301 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x301>;
		};
		CPU14: cpu@302 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x302>;
		};
		CPU15: cpu@303 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x303>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&gic>;
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
	};

	clk_50m: clk_50m {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <50000000>;
	};

	clk_168m: clk_168m {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <168000000>;
	};

	soc {
		/* It's a 32-bit SoC. */
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges = <0 0 0xe0000000 0x10000000>;

		gic: interrupt-controller@c01000 {
			compatible = "hisilicon,hip04-intc";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			interrupts = <1 9 0xf04>;

			reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
			      <0xc04000 0x2000>, <0xc06000 0x2000>;
		};

		sysctrl: sysctrl {
			compatible = "hisilicon,sysctrl";
			reg = <0x3e00000 0x00100000>;
		};

		fabric: fabric {
			compatible = "hisilicon,hip04-fabric";
			reg = <0x302a000 0x1000>;
		};

		dual_timer0: dual_timer@3000000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x3000000 0x1000>;
			interrupts = <0 224 4>;
			clocks = <&clk_50m>, <&clk_50m>;
			clock-names = "apb_pclk";
		};

		arm-pmu {
			compatible = "arm,cortex-a15-pmu";
			interrupts = <0 64 4>,
				     <0 65 4>,
				     <0 66 4>,
				     <0 67 4>,
				     <0 68 4>,
				     <0 69 4>,
				     <0 70 4>,
				     <0 71 4>,
				     <0 72 4>,
				     <0 73 4>,
				     <0 74 4>,
				     <0 75 4>,
				     <0 76 4>,
				     <0 77 4>,
				     <0 78 4>,
				     <0 79 4>;
		};

		uart0: uart@4007000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x4007000 0x1000>;
			interrupts = <0 381 4>;
			clocks = <&clk_168m>;
			clock-names = "uartclk";
			reg-shift = <2>;
			status = "disabled";
		};

		sata0: sata@a000000 {
			compatible = "hisilicon,hisi-ahci";
			reg = <0xa000000 0x1000000>;
			interrupts = <0 372 4>;
		};

	};
};
Commit	Line	Data
40c7d441 HZ	1	/*
	2	* Hisilicon Ltd. HiP04 SoC
	3	*
	4	* Copyright (C) 2013-2014 Hisilicon Ltd.
	5	* Copyright (C) 2013-2014 Linaro Ltd.
	6	*
	7	* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	/ {
	15	/* memory bus is 64-bit */
	16	#address-cells = <2>;
	17	#size-cells = <2>;
	18
	19	aliases {
	20	serial0 = &uart0;
	21	};
	22
	23	bootwrapper {
	24	compatible = "hisilicon,hip04-bootwrapper";
	25	boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
	26	};
	27
	28	cpus {
	29	#address-cells = <1>;
	30	#size-cells = <0>;
	31
	32	cpu-map {
	33	cluster0 {
	34	core0 {
	35	cpu = <&CPU0>;
	36	};
	37	core1 {
	38	cpu = <&CPU1>;
	39	};
	40	core2 {
	41	cpu = <&CPU2>;
	42	};
	43	core3 {
	44	cpu = <&CPU3>;
	45	};
	46	};
	47	cluster1 {
	48	core0 {
	49	cpu = <&CPU4>;
	50	};
	51	core1 {
	52	cpu = <&CPU5>;
	53	};
	54	core2 {
	55	cpu = <&CPU6>;
	56	};
	57	core3 {
	58	cpu = <&CPU7>;
	59	};
	60	};
	61	cluster2 {
	62	core0 {
	63	cpu = <&CPU8>;
	64	};
65	core1 {
66	cpu = <&CPU9>;
67	};
68	core2 {
69	cpu = <&CPU10>;
70	};
71	core3 {
72	cpu = <&CPU11>;
73	};
74	};
75	cluster3 {
76	core0 {
77	cpu = <&CPU12>;
78	};
79	core1 {
80	cpu = <&CPU13>;
81	};
82	core2 {
83	cpu = <&CPU14>;
84	};
85	core3 {
86	cpu = <&CPU15>;
87	};
88	};
89	};
90	CPU0: cpu@0 {
91	device_type = "cpu";
92	compatible = "arm,cortex-a15";
93	reg = <0>;
94	};
95	CPU1: cpu@1 {
96	device_type = "cpu";
97	compatible = "arm,cortex-a15";
98	reg = <1>;
99	};
100	CPU2: cpu@2 {
101	device_type = "cpu";
102	compatible = "arm,cortex-a15";
103	reg = <2>;
104	};
105	CPU3: cpu@3 {
106	device_type = "cpu";
107	compatible = "arm,cortex-a15";
108	reg = <3>;
109	};
110	CPU4: cpu@100 {
111	device_type = "cpu";
112	compatible = "arm,cortex-a15";
113	reg = <0x100>;
114	};
115	CPU5: cpu@101 {
116	device_type = "cpu";
117	compatible = "arm,cortex-a15";
118	reg = <0x101>;
119	};
120	CPU6: cpu@102 {
121	device_type = "cpu";
122	compatible = "arm,cortex-a15";
123	reg = <0x102>;
124	};
125	CPU7: cpu@103 {
126	device_type = "cpu";
127	compatible = "arm,cortex-a15";
128	reg = <0x103>;
129	};
130	CPU8: cpu@200 {
131	device_type = "cpu";
132	compatible = "arm,cortex-a15";
133	reg = <0x200>;
134	};
135	CPU9: cpu@201 {
136	device_type = "cpu";
137	compatible = "arm,cortex-a15";
138	reg = <0x201>;
139	};
140	CPU10: cpu@202 {
141	device_type = "cpu";
142	compatible = "arm,cortex-a15";
143	reg = <0x202>;
144	};
145	CPU11: cpu@203 {
146	device_type = "cpu";
147	compatible = "arm,cortex-a15";
148	reg = <0x203>;
149	};
150	CPU12: cpu@300 {
151	device_type = "cpu";
152	compatible = "arm,cortex-a15";
153	reg = <0x300>;
154	};
155	CPU13: cpu@301 {
156	device_type = "cpu";
157	compatible = "arm,cortex-a15";
158	reg = <0x301>;
159	};
160	CPU14: cpu@302 {
161	device_type = "cpu";
162	compatible = "arm,cortex-a15";
163	reg = <0x302>;
164	};
165	CPU15: cpu@303 {
166	device_type = "cpu";
167	compatible = "arm,cortex-a15";
168	reg = <0x303>;
169	};
170	};
171
172	timer {
173	compatible = "arm,armv7-timer";
174	interrupt-parent = <&gic>;
175	interrupts = <1 13 0xf08>,
176	<1 14 0xf08>,
177	<1 11 0xf08>,
178	<1 10 0xf08>;
179	};
180
181	clk_50m: clk_50m {
182	#clock-cells = <0>;
183	compatible = "fixed-clock";
184	clock-frequency = <50000000>;
185	};
186
187	clk_168m: clk_168m {
188	#clock-cells = <0>;
189	compatible = "fixed-clock";
190	clock-frequency = <168000000>;
191	};
192
193	soc {
194	/* It's a 32-bit SoC. */
195	#address-cells = <1>;
196	#size-cells = <1>;
197	compatible = "simple-bus";
198	interrupt-parent = <&gic>;
199	ranges = <0 0 0xe0000000 0x10000000>;
200
201	gic: interrupt-controller@c01000 {
202	compatible = "hisilicon,hip04-intc";
203	#interrupt-cells = <3>;
204	#address-cells = <0>;
205	interrupt-controller;
206	interrupts = <1 9 0xf04>;
207
208	reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
209	<0xc04000 0x2000>, <0xc06000 0x2000>;
210	};
211
212	sysctrl: sysctrl {
213	compatible = "hisilicon,sysctrl";
214	reg = <0x3e00000 0x00100000>;
215	};
216
217	fabric: fabric {
218	compatible = "hisilicon,hip04-fabric";
219	reg = <0x302a000 0x1000>;
220	};
221
222	dual_timer0: dual_timer@3000000 {
223	compatible = "arm,sp804", "arm,primecell";
224	reg = <0x3000000 0x1000>;
225	interrupts = <0 224 4>;
226	clocks = <&clk_50m>, <&clk_50m>;
227	clock-names = "apb_pclk";
228	};
229
230	arm-pmu {
231	compatible = "arm,cortex-a15-pmu";
232	interrupts = <0 64 4>,
233	<0 65 4>,
234	<0 66 4>,
235	<0 67 4>,
236	<0 68 4>,
237	<0 69 4>,
238	<0 70 4>,
239	<0 71 4>,
240	<0 72 4>,
241	<0 73 4>,
242	<0 74 4>,
243	<0 75 4>,
244	<0 76 4>,
245	<0 77 4>,
246	<0 78 4>,
247	<0 79 4>;
248	};
249
250	uart0: uart@4007000 {
251	compatible = "snps,dw-apb-uart";
252	reg = <0x4007000 0x1000>;
253	interrupts = <0 381 4>;
254	clocks = <&clk_168m>;
255	clock-names = "uartclk";
256	reg-shift = <2>;
257	status = "disabled";
258	};
259
260	sata0: sata@a000000 {
261	compatible = "hisilicon,hisi-ahci";
262	reg = <0xa000000 0x1000000>;
263	interrupts = <0 372 4>;
264	};
265
266	};
267	};