[deliverable/linux.git] / arch / arm / boot / dts / imx27-phytec-phycore-som.dts

/*
 * Copyright 2012 Sascha Hauer, Pengutronix
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include "imx27.dtsi"

/ {
	model = "Phytec pcm038";
	compatible = "phytec,imx27-pcm038", "fsl,imx27";

	memory {
		reg = <0xa0000000 0x08000000>;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_3v3: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "3V3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};
	};
};

&audmux {
	status = "okay";

	/* SSI0 <=> PINS_4 (MC13783 Audio) */
	ssi0 {
		fsl,audmux-port = <0>;
		fsl,port-config = <0xcb205000>;
	};

	pins4 {
		fsl,audmux-port = <2>;
		fsl,port-config = <0x00001000>;
	};
};

&cspi1 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
	status = "okay";

	pmic: mc13783@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,mc13783";
		spi-max-frequency = <20000000>;
		reg = <0>;
		interrupt-parent = <&gpio2>;
		interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
		fsl,mc13xxx-uses-adc;
		fsl,mc13xxx-uses-rtc;

		regulators {
			/* SW1A and SW1B joined operation */
			sw1_reg: sw1a {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1520000>;
				regulator-always-on;
				regulator-boot-on;
			};

			/* SW2A and SW2B joined operation */
			sw2_reg: sw2a {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			sw3_reg: sw3 {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5000000>;
				regulator-always-on;
				regulator-boot-on;
			};

			vaudio_reg: vaudio {
				regulator-always-on;
				regulator-boot-on;
			};

			violo_reg: violo {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			viohi_reg: viohi {
				regulator-always-on;
				regulator-boot-on;
			};

			vgen_reg: vgen {
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <1500000>;
				regulator-always-on;
				regulator-boot-on;
			};

			vcam_reg: vcam {
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
			};

			vrf1_reg: vrf1 {
				regulator-min-microvolt = <2775000>;
				regulator-max-microvolt = <2775000>;
				regulator-always-on;
				regulator-boot-on;
			};

			vrf2_reg: vrf2 {
				regulator-min-microvolt = <2775000>;
				regulator-max-microvolt = <2775000>;
				regulator-always-on;
				regulator-boot-on;
			};

			vmmc1_reg: vmmc1 {
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3000000>;
			};

			gpo1_reg: gpo1 { };

			pwgt1spi_reg: pwgt1spi {
				regulator-always-on;
			};
		};
	};
};

&fec {
	phy-mode = "mii";
	phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
	phy-supply = <&reg_3v3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	at24@52 {
		compatible = "at,24c32";
		pagesize = <32>;
		reg = <0x52>;
	};

	pcf8563@51 {
		compatible = "nxp,pcf8563";
		reg = <0x51>;
	};

	lm75@4a {
		compatible = "national,lm75";
		reg = <0x4a>;
	};
};

&iomuxc {
	imx27_phycore_som {
		pinctrl_fec1: fec1grp {
			fsl,pins = <
				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
				MX27_PAD_ATA_DATA13__FEC_COL 0x0
				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
				MX27_PAD_SSI3_TXDAT__GPIO3_30	0x0 /* FEC RST */
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
			>;
		};
	};
};

&nfc {
	nand-bus-width = <8>;
	nand-ecc-mode = "hw";
	nand-on-flash-bbt;
	status = "okay";
};

&weim {
	status = "okay";

	nor: nor@c0000000 {
		compatible = "cfi-flash";
		reg = <0 0x00000000 0x02000000>;
		bank-width = <2>;
		linux,mtd-name = "physmap-flash.0";
		fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
		#address-cells = <1>;
		#size-cells = <1>;
	};

	sram: sram@c8000000 {
		compatible = "mtd-ram";
		reg = <1 0x00000000 0x00800000>;
		bank-width = <2>;
		linux,mtd-name = "mtd-ram.0";
		fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};
Commit	Line	Data
10a9ba05 SH	1	/*
	2	* Copyright 2012 Sascha Hauer, Pengutronix
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
	12	/dts-v1/;
36dffd8f	13	#include "imx27.dtsi"
10a9ba05 SH	14
	15	/ {
	16	model = "Phytec pcm038";
	17	compatible = "phytec,imx27-pcm038", "fsl,imx27";
	18
	19	memory {
999f6818	20	reg = <0xa0000000 0x08000000>;
10a9ba05	21	};
f64ba746 AS	22
	23	regulators {
	24	compatible = "simple-bus";
	25	#address-cells = <1>;
	26	#size-cells = <0>;
	27
	28	reg_3v3: regulator@0 {
	29	compatible = "regulator-fixed";
	30	reg = <0>;
	31	regulator-name = "3V3";
	32	regulator-min-microvolt = <3300000>;
	33	regulator-max-microvolt = <3300000>;
	34	};
	35	};
10a9ba05	36	};
1b45aceb	37
a919c69c AS	38	&audmux {
	39	status = "okay";
	40
	41	/* SSI0 <=> PINS_4 (MC13783 Audio) */
	42	ssi0 {
	43	fsl,audmux-port = <0>;
	44	fsl,port-config = <0xcb205000>;
	45	};
	46
	47	pins4 {
	48	fsl,audmux-port = <2>;
	49	fsl,port-config = <0x00001000>;
	50	};
	51	};
	52
5d3503cd AS	53	&cspi1 {
5d3503cd AS	54	fsl,spi-num-chipselects = <1>;
6ece55b3	55	cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
5d3503cd AS	56	status = "okay";
	57
	58	pmic: mc13783@0 {
	59	#address-cells = <1>;
	60	#size-cells = <0>;
	61	compatible = "fsl,mc13783";
	62	spi-max-frequency = <20000000>;
	63	reg = <0>;
	64	interrupt-parent = <&gpio2>;
6ece55b3	65	interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
5d3503cd AS	66	fsl,mc13xxx-uses-adc;
	67	fsl,mc13xxx-uses-rtc;
	68
	69	regulators {
e9c17866 AS	70	/* SW1A and SW1B joined operation */
e9c17866 AS	71	sw1_reg: sw1a {
5d3503cd	72	regulator-min-microvolt = <1200000>;
e9c17866	73	regulator-max-microvolt = <1520000>;
5d3503cd AS	74	regulator-always-on;
	75	regulator-boot-on;
	76	};
	77
e9c17866 AS	78	/* SW2A and SW2B joined operation */
e9c17866 AS	79	sw2_reg: sw2a {
5d3503cd AS	80	regulator-min-microvolt = <1800000>;
	81	regulator-max-microvolt = <1800000>;
	82	regulator-always-on;
	83	regulator-boot-on;
	84	};
	85
	86	sw3_reg: sw3 {
	87	regulator-min-microvolt = <5000000>;
	88	regulator-max-microvolt = <5000000>;
	89	regulator-always-on;
	90	regulator-boot-on;
	91	};
	92
	93	vaudio_reg: vaudio {
	94	regulator-always-on;
	95	regulator-boot-on;
	96	};
	97
	98	violo_reg: violo {
	99	regulator-min-microvolt = <1800000>;
	100	regulator-max-microvolt = <1800000>;
	101	regulator-always-on;
	102	regulator-boot-on;
	103	};
	104
	105	viohi_reg: viohi {
	106	regulator-always-on;
	107	regulator-boot-on;
	108	};
	109
	110	vgen_reg: vgen {
	111	regulator-min-microvolt = <1500000>;
	112	regulator-max-microvolt = <1500000>;
	113	regulator-always-on;
	114	regulator-boot-on;
	115	};
	116
	117	vcam_reg: vcam {
	118	regulator-min-microvolt = <2800000>;
	119	regulator-max-microvolt = <2800000>;
	120	};
	121
	122	vrf1_reg: vrf1 {
	123	regulator-min-microvolt = <2775000>;
	124	regulator-max-microvolt = <2775000>;
	125	regulator-always-on;
	126	regulator-boot-on;
	127	};
	128
	129	vrf2_reg: vrf2 {
	130	regulator-min-microvolt = <2775000>;
	131	regulator-max-microvolt = <2775000>;
	132	regulator-always-on;
	133	regulator-boot-on;
	134	};
	135
	136	vmmc1_reg: vmmc1 {
	137	regulator-min-microvolt = <1600000>;
	138	regulator-max-microvolt = <3000000>;
	139	};
	140
	141	gpo1_reg: gpo1 { };
	142
	143	pwgt1spi_reg: pwgt1spi {
144	regulator-always-on;
145	};
146	};
147	};
148	};
149
f0d8e3f1	150	&fec {
f64ba746	151	phy-mode = "mii";
6ece55b3	152	phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
f64ba746	153	phy-supply = <&reg_3v3>;
26508cb7 MP	154	pinctrl-names = "default";
26508cb7 MP	155	pinctrl-0 = <&pinctrl_fec1>;
f0d8e3f1 AS	156	status = "okay";
	157	};
	158
	159	&i2c2 {
	160	clock-frequency = <400000>;
26508cb7 MP	161	pinctrl-names = "default";
26508cb7 MP	162	pinctrl-0 = <&pinctrl_i2c2>;
f0d8e3f1 AS	163	status = "okay";
	164
	165	at24@52 {
	166	compatible = "at,24c32";
	167	pagesize = <32>;
	168	reg = <0x52>;
	169	};
	170
	171	pcf8563@51 {
	172	compatible = "nxp,pcf8563";
	173	reg = <0x51>;
	174	};
	175
	176	lm75@4a {
	177	compatible = "national,lm75";
	178	reg = <0x4a>;
	179	};
	180	};
	181
26508cb7 MP	182	&iomuxc {
	183	imx27_phycore_som {
	184	pinctrl_fec1: fec1grp {
	185	fsl,pins = <
	186	MX27_PAD_SD3_CMD__FEC_TXD0 0x0
	187	MX27_PAD_SD3_CLK__FEC_TXD1 0x0
	188	MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
	189	MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
	190	MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
	191	MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
	192	MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
	193	MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
	194	MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
	195	MX27_PAD_ATA_DATA7__FEC_MDC 0x0
	196	MX27_PAD_ATA_DATA8__FEC_CRS 0x0
	197	MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
	198	MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
	199	MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
	200	MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
	201	MX27_PAD_ATA_DATA13__FEC_COL 0x0
	202	MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
	203	MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
	204	MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */
	205	>;
	206	};
	207
	208	pinctrl_i2c2: i2c2grp {
	209	fsl,pins = <
	210	MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
	211	MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
	212	>;
	213	};
	214	};
	215	};
	216
1b45aceb AS	217	&nfc {
	218	nand-bus-width = <8>;
	219	nand-ecc-mode = "hw";
d9a57aaf	220	nand-on-flash-bbt;
1b45aceb AS	221	status = "okay";
1b45aceb AS	222	};
984d6fc3 AS	223
	224	&weim {
	225	status = "okay";
	226
	227	nor: nor@c0000000 {
	228	compatible = "cfi-flash";
	229	reg = <0 0x00000000 0x02000000>;
	230	bank-width = <2>;
	231	linux,mtd-name = "physmap-flash.0";
	232	fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
	233	#address-cells = <1>;
	234	#size-cells = <1>;
	235	};
cff2a713 AS	236
	237	sram: sram@c8000000 {
	238	compatible = "mtd-ram";
	239	reg = <1 0x00000000 0x00800000>;
	240	bank-width = <2>;
	241	linux,mtd-name = "mtd-ram.0";
	242	fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
	243	#address-cells = <1>;
	244	#size-cells = <1>;
	245	};
984d6fc3	246	};