ARM: dts: imx27-phytec-phycore-rdk: Add CAN node
[deliverable/linux.git] / arch / arm / boot / dts / imx27-phytec-phycore-som.dts
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1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
36dffd8f 13#include "imx27.dtsi"
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14
15/ {
16 model = "Phytec pcm038";
17 compatible = "phytec,imx27-pcm038", "fsl,imx27";
18
19 memory {
999f6818 20 reg = <0xa0000000 0x08000000>;
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21 };
22
23 soc {
3e24b05b 24 aipi@10000000 { /* aipi1 */
0c456cfa 25 serial@1000a000 {
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26 status = "okay";
27 };
28
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29 i2c@1001d000 {
30 clock-frequency = <400000>;
31 status = "okay";
8b23f513 32 at24@52 {
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33 compatible = "at,24c32";
34 pagesize = <32>;
35 reg = <0x52>;
36 };
37 pcf8563@51 {
38 compatible = "nxp,pcf8563";
39 reg = <0x51>;
40 };
41 lm75@4a {
42 compatible = "national,lm75";
43 reg = <0x4a>;
44 };
45 };
46 };
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47
48 aipi@10020000 { /* aipi2 */
49 ethernet@1002b000 {
44673d6b 50 phy-reset-gpios = <&gpio3 30 0>;
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51 status = "okay";
52 };
53 };
10a9ba05 54 };
10a9ba05 55};
1b45aceb 56
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57&cspi1 {
58 fsl,spi-num-chipselects = <1>;
59 cs-gpios = <&gpio4 28 0>;
60 status = "okay";
61
62 pmic: mc13783@0 {
63 #address-cells = <1>;
64 #size-cells = <0>;
65 compatible = "fsl,mc13783";
66 spi-max-frequency = <20000000>;
67 reg = <0>;
68 interrupt-parent = <&gpio2>;
69 interrupts = <23 0x4>;
70 fsl,mc13xxx-uses-adc;
71 fsl,mc13xxx-uses-rtc;
72
73 regulators {
74 sw1a_reg: sw1a {
75 regulator-min-microvolt = <1200000>;
76 regulator-max-microvolt = <1200000>;
77 regulator-always-on;
78 regulator-boot-on;
79 };
80
81 sw1b_reg: sw1b {
82 regulator-min-microvolt = <1200000>;
83 regulator-max-microvolt = <1200000>;
84 regulator-always-on;
85 regulator-boot-on;
86 };
87
88 sw2a_reg: sw2a {
89 regulator-min-microvolt = <1800000>;
90 regulator-max-microvolt = <1800000>;
91 regulator-always-on;
92 regulator-boot-on;
93 };
94
95 sw2b_reg: sw2b {
96 regulator-min-microvolt = <1800000>;
97 regulator-max-microvolt = <1800000>;
98 regulator-always-on;
99 regulator-boot-on;
100 };
101
102 sw3_reg: sw3 {
103 regulator-min-microvolt = <5000000>;
104 regulator-max-microvolt = <5000000>;
105 regulator-always-on;
106 regulator-boot-on;
107 };
108
109 vaudio_reg: vaudio {
110 regulator-always-on;
111 regulator-boot-on;
112 };
113
114 violo_reg: violo {
115 regulator-min-microvolt = <1800000>;
116 regulator-max-microvolt = <1800000>;
117 regulator-always-on;
118 regulator-boot-on;
119 };
120
121 viohi_reg: viohi {
122 regulator-always-on;
123 regulator-boot-on;
124 };
125
126 vgen_reg: vgen {
127 regulator-min-microvolt = <1500000>;
128 regulator-max-microvolt = <1500000>;
129 regulator-always-on;
130 regulator-boot-on;
131 };
132
133 vcam_reg: vcam {
134 regulator-min-microvolt = <2800000>;
135 regulator-max-microvolt = <2800000>;
136 };
137
138 vrf1_reg: vrf1 {
139 regulator-min-microvolt = <2775000>;
140 regulator-max-microvolt = <2775000>;
141 regulator-always-on;
142 regulator-boot-on;
143 };
144
145 vrf2_reg: vrf2 {
146 regulator-min-microvolt = <2775000>;
147 regulator-max-microvolt = <2775000>;
148 regulator-always-on;
149 regulator-boot-on;
150 };
151
152 vmmc1_reg: vmmc1 {
153 regulator-min-microvolt = <1600000>;
154 regulator-max-microvolt = <3000000>;
155 };
156
157 gpo1_reg: gpo1 { };
158
159 pwgt1spi_reg: pwgt1spi {
160 regulator-always-on;
161 };
162 };
163 };
164};
165
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166&nfc {
167 nand-bus-width = <8>;
168 nand-ecc-mode = "hw";
169 status = "okay";
170};
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171
172&weim {
173 status = "okay";
174
175 nor: nor@c0000000 {
176 compatible = "cfi-flash";
177 reg = <0 0x00000000 0x02000000>;
178 bank-width = <2>;
179 linux,mtd-name = "physmap-flash.0";
180 fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
181 #address-cells = <1>;
182 #size-cells = <1>;
183 };
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184
185 sram: sram@c8000000 {
186 compatible = "mtd-ram";
187 reg = <1 0x00000000 0x00800000>;
188 bank-width = <2>;
189 linux,mtd-name = "mtd-ram.0";
190 fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
191 #address-cells = <1>;
192 #size-cells = <1>;
193 };
984d6fc3 194};
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