projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 9f0749e3 SH |
1 | /* |
| 2 | * Copyright 2012 Sascha Hauer, Pengutronix | |
| 3 | * | |
| 4 | * The code contained herein is licensed under the GNU General Public | |
| 5 | * License. You may obtain a copy of the GNU General Public License | |
| 6 | * Version 2 or later at the following locations: | |
| 7 | * | |
| 8 | * http://www.opensource.org/licenses/gpl-license.html | |
| 9 | * http://www.gnu.org/copyleft/gpl.html | |
| 10 | */ | |
| 11 | ||
| 36dffd8f | 12 | #include "skeleton.dtsi" |
| 9f0749e3 SH |
13 | |
| 14 | / { | |
| 15 | aliases { | |
| 16 | serial0 = &uart1; | |
| 17 | serial1 = &uart2; | |
| 18 | serial2 = &uart3; | |
| 19 | serial3 = &uart4; | |
| 20 | serial4 = &uart5; | |
| 21 | serial5 = &uart6; | |
| 5230f8fe SG |
22 | gpio0 = &gpio1; |
| 23 | gpio1 = &gpio2; | |
| 24 | gpio2 = &gpio3; | |
| 25 | gpio3 = &gpio4; | |
| 26 | gpio4 = &gpio5; | |
| 27 | gpio5 = &gpio6; | |
| a5a641a1 AS |
28 | spi0 = &cspi1; |
| 29 | spi1 = &cspi2; | |
| 30 | spi2 = &cspi3; | |
| 9f0749e3 SH |
31 | }; |
| 32 | ||
| 33 | avic: avic-interrupt-controller@e0000000 { | |
| 34 | compatible = "fsl,imx27-avic", "fsl,avic"; | |
| 35 | interrupt-controller; | |
| 36 | #interrupt-cells = <1>; | |
| 37 | reg = <0x10040000 0x1000>; | |
| 38 | }; | |
| 39 | ||
| 40 | clocks { | |
| 41 | #address-cells = <1>; | |
| 42 | #size-cells = <0>; | |
| 43 | ||
| 44 | osc26m { | |
| 45 | compatible = "fsl,imx-osc26m", "fixed-clock"; | |
| 46 | clock-frequency = <26000000>; | |
| 47 | }; | |
| 48 | }; | |
| 49 | ||
| 50 | soc { | |
| 51 | #address-cells = <1>; | |
| 52 | #size-cells = <1>; | |
| 53 | compatible = "simple-bus"; | |
| 54 | interrupt-parent = <&avic>; | |
| 55 | ranges; | |
| 56 | ||
| 57 | aipi@10000000 { /* AIPI1 */ | |
| 58 | compatible = "fsl,aipi-bus", "simple-bus"; | |
| 59 | #address-cells = <1>; | |
| 60 | #size-cells = <1>; | |
| 3e24b05b | 61 | reg = <0x10000000 0x20000>; |
| 9f0749e3 SH |
62 | ranges; |
| 63 | ||
| b858c34f AS |
64 | dma: dma@10001000 { |
| 65 | compatible = "fsl,imx27-dma"; | |
| 66 | reg = <0x10001000 0x1000>; | |
| 67 | interrupts = <32>; | |
| 68 | clocks = <&clks 50>, <&clks 70>; | |
| 69 | clock-names = "ipg", "ahb"; | |
| 70 | #dma-cells = <1>; | |
| 71 | #dma-channels = <16>; | |
| 72 | }; | |
| 73 | ||
| 7b7d6727 | 74 | wdog: wdog@10002000 { |
| 9f0749e3 | 75 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; |
| ca26d041 | 76 | reg = <0x10002000 0x1000>; |
| 9f0749e3 | 77 | interrupts = <27>; |
| c20736f1 | 78 | clocks = <&clks 0>; |
| 9f0749e3 SH |
79 | }; |
| 80 | ||
| ca26d041 SH |
81 | gpt1: timer@10003000 { |
| 82 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
| 83 | reg = <0x10003000 0x1000>; | |
| 84 | interrupts = <26>; | |
| b700c119 SH |
85 | clocks = <&clks 46>, <&clks 61>; |
| 86 | clock-names = "ipg", "per"; | |
| ca26d041 SH |
87 | }; |
| 88 | ||
| 89 | gpt2: timer@10004000 { | |
| 90 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
| 91 | reg = <0x10004000 0x1000>; | |
| 92 | interrupts = <25>; | |
| b700c119 SH |
93 | clocks = <&clks 45>, <&clks 61>; |
| 94 | clock-names = "ipg", "per"; | |
| ca26d041 SH |
95 | }; |
| 96 | ||
| 97 | gpt3: timer@10005000 { | |
| 98 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
| 99 | reg = <0x10005000 0x1000>; | |
| 100 | interrupts = <24>; | |
| b700c119 SH |
101 | clocks = <&clks 44>, <&clks 61>; |
| 102 | clock-names = "ipg", "per"; | |
| ca26d041 SH |
103 | }; |
| 104 | ||
| 08f4881a GGM |
105 | pwm0: pwm@10006000 { |
| 106 | compatible = "fsl,imx27-pwm"; | |
| 107 | reg = <0x10006000 0x1000>; | |
| 108 | interrupts = <23>; | |
| 109 | clocks = <&clks 34>, <&clks 61>; | |
| 110 | clock-names = "ipg", "per"; | |
| 111 | }; | |
| 112 | ||
| 0c456cfa | 113 | uart1: serial@1000a000 { |
| 9f0749e3 SH |
114 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 115 | reg = <0x1000a000 0x1000>; | |
| 116 | interrupts = <20>; | |
| c20736f1 FE |
117 | clocks = <&clks 81>, <&clks 61>; |
| 118 | clock-names = "ipg", "per"; | |
| 9f0749e3 SH |
119 | status = "disabled"; |
| 120 | }; | |
| 121 | ||
| 0c456cfa | 122 | uart2: serial@1000b000 { |
| 9f0749e3 SH |
123 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 124 | reg = <0x1000b000 0x1000>; | |
| 125 | interrupts = <19>; | |
| c20736f1 FE |
126 | clocks = <&clks 80>, <&clks 61>; |
| 127 | clock-names = "ipg", "per"; | |
| 9f0749e3 SH |
128 | status = "disabled"; |
| 129 | }; | |
| 130 | ||
| 0c456cfa | 131 | uart3: serial@1000c000 { |
| 9f0749e3 SH |
132 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 133 | reg = <0x1000c000 0x1000>; | |
| 134 | interrupts = <18>; | |
| c20736f1 FE |
135 | clocks = <&clks 79>, <&clks 61>; |
| 136 | clock-names = "ipg", "per"; | |
| 9f0749e3 SH |
137 | status = "disabled"; |
| 138 | }; | |
| 139 | ||
| 0c456cfa | 140 | uart4: serial@1000d000 { |
| 9f0749e3 SH |
141 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 142 | reg = <0x1000d000 0x1000>; | |
| 143 | interrupts = <17>; | |
| c20736f1 FE |
144 | clocks = <&clks 78>, <&clks 61>; |
| 145 | clock-names = "ipg", "per"; | |
| 9f0749e3 SH |
146 | status = "disabled"; |
| 147 | }; | |
| 148 | ||
| 149 | cspi1: cspi@1000e000 { | |
| 150 | #address-cells = <1>; | |
| 151 | #size-cells = <0>; | |
| 152 | compatible = "fsl,imx27-cspi"; | |
| 153 | reg = <0x1000e000 0x1000>; | |
| 154 | interrupts = <16>; | |
| 37523dc5 | 155 | clocks = <&clks 53>, <&clks 53>; |
| c20736f1 | 156 | clock-names = "ipg", "per"; |
| 9f0749e3 SH |
157 | status = "disabled"; |
| 158 | }; | |
| 159 | ||
| 160 | cspi2: cspi@1000f000 { | |
| 161 | #address-cells = <1>; | |
| 162 | #size-cells = <0>; | |
| 163 | compatible = "fsl,imx27-cspi"; | |
| 164 | reg = <0x1000f000 0x1000>; | |
| 165 | interrupts = <15>; | |
| 37523dc5 | 166 | clocks = <&clks 52>, <&clks 52>; |
| c20736f1 | 167 | clock-names = "ipg", "per"; |
| 9f0749e3 SH |
168 | status = "disabled"; |
| 169 | }; | |
| 170 | ||
| 171 | i2c1: i2c@10012000 { | |
| 172 | #address-cells = <1>; | |
| 173 | #size-cells = <0>; | |
| 5bdfba29 | 174 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
| 9f0749e3 SH |
175 | reg = <0x10012000 0x1000>; |
| 176 | interrupts = <12>; | |
| c20736f1 | 177 | clocks = <&clks 40>; |
| 9f0749e3 SH |
178 | status = "disabled"; |
| 179 | }; | |
| 180 | ||
| 0e7b01aa AS |
181 | sdhci1: sdhci@10013000 { |
| 182 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; | |
| 183 | reg = <0x10013000 0x1000>; | |
| 184 | interrupts = <11>; | |
| 185 | clocks = <&clks 30>, <&clks 60>; | |
| 186 | clock-names = "ipg", "per"; | |
| 187 | dmas = <&dma 7>; | |
| 188 | dma-names = "rx-tx"; | |
| 189 | status = "disabled"; | |
| 190 | }; | |
| 191 | ||
| 192 | sdhci2: sdhci@10014000 { | |
| 193 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; | |
| 194 | reg = <0x10014000 0x1000>; | |
| 195 | interrupts = <10>; | |
| 196 | clocks = <&clks 29>, <&clks 60>; | |
| 197 | clock-names = "ipg", "per"; | |
| 198 | dmas = <&dma 6>; | |
| 199 | dma-names = "rx-tx"; | |
| 200 | status = "disabled"; | |
| 201 | }; | |
| 202 | ||
| 9f0749e3 SH |
203 | gpio1: gpio@10015000 { |
| 204 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
| 205 | reg = <0x10015000 0x100>; | |
| 206 | interrupts = <8>; | |
| 207 | gpio-controller; | |
| 208 | #gpio-cells = <2>; | |
| 209 | interrupt-controller; | |
| 88cde8b7 | 210 | #interrupt-cells = <2>; |
| 9f0749e3 SH |
211 | }; |
| 212 | ||
| 213 | gpio2: gpio@10015100 { | |
| 214 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
| 215 | reg = <0x10015100 0x100>; | |
| 216 | interrupts = <8>; | |
| 217 | gpio-controller; | |
| 218 | #gpio-cells = <2>; | |
| 219 | interrupt-controller; | |
| 88cde8b7 | 220 | #interrupt-cells = <2>; |
| 9f0749e3 SH |
221 | }; |
| 222 | ||
| 223 | gpio3: gpio@10015200 { | |
| 224 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
| 225 | reg = <0x10015200 0x100>; | |
| 226 | interrupts = <8>; | |
| 227 | gpio-controller; | |
| 228 | #gpio-cells = <2>; | |
| 229 | interrupt-controller; | |
| 88cde8b7 | 230 | #interrupt-cells = <2>; |
| 9f0749e3 SH |
231 | }; |
| 232 | ||
| 233 | gpio4: gpio@10015300 { | |
| 234 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
| 235 | reg = <0x10015300 0x100>; | |
| 236 | interrupts = <8>; | |
| 237 | gpio-controller; | |
| 238 | #gpio-cells = <2>; | |
| 239 | interrupt-controller; | |
| 88cde8b7 | 240 | #interrupt-cells = <2>; |
| 9f0749e3 SH |
241 | }; |
| 242 | ||
| 243 | gpio5: gpio@10015400 { | |
| 244 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
| 245 | reg = <0x10015400 0x100>; | |
| 246 | interrupts = <8>; | |
| 247 | gpio-controller; | |
| 248 | #gpio-cells = <2>; | |
| 249 | interrupt-controller; | |
| 88cde8b7 | 250 | #interrupt-cells = <2>; |
| 9f0749e3 SH |
251 | }; |
| 252 | ||
| 253 | gpio6: gpio@10015500 { | |
| 254 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
| 255 | reg = <0x10015500 0x100>; | |
| 256 | interrupts = <8>; | |
| 257 | gpio-controller; | |
| 258 | #gpio-cells = <2>; | |
| 259 | interrupt-controller; | |
| 88cde8b7 | 260 | #interrupt-cells = <2>; |
| 9f0749e3 SH |
261 | }; |
| 262 | ||
| 263 | cspi3: cspi@10017000 { | |
| 264 | #address-cells = <1>; | |
| 265 | #size-cells = <0>; | |
| 266 | compatible = "fsl,imx27-cspi"; | |
| 267 | reg = <0x10017000 0x1000>; | |
| 268 | interrupts = <6>; | |
| 37523dc5 | 269 | clocks = <&clks 51>, <&clks 51>; |
| c20736f1 | 270 | clock-names = "ipg", "per"; |
| 9f0749e3 SH |
271 | status = "disabled"; |
| 272 | }; | |
| 273 | ||
| ca26d041 SH |
274 | gpt4: timer@10019000 { |
| 275 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
| 276 | reg = <0x10019000 0x1000>; | |
| 277 | interrupts = <4>; | |
| b700c119 SH |
278 | clocks = <&clks 43>, <&clks 61>; |
| 279 | clock-names = "ipg", "per"; | |
| ca26d041 SH |
280 | }; |
| 281 | ||
| 282 | gpt5: timer@1001a000 { | |
| 283 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
| 284 | reg = <0x1001a000 0x1000>; | |
| 285 | interrupts = <3>; | |
| b700c119 SH |
286 | clocks = <&clks 42>, <&clks 61>; |
| 287 | clock-names = "ipg", "per"; | |
| ca26d041 SH |
288 | }; |
| 289 | ||
| 0c456cfa | 290 | uart5: serial@1001b000 { |
| 9f0749e3 SH |
291 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 292 | reg = <0x1001b000 0x1000>; | |
| 293 | interrupts = <49>; | |
| c20736f1 FE |
294 | clocks = <&clks 77>, <&clks 61>; |
| 295 | clock-names = "ipg", "per"; | |
| 9f0749e3 SH |
296 | status = "disabled"; |
| 297 | }; | |
| 298 | ||
| 0c456cfa | 299 | uart6: serial@1001c000 { |
| 9f0749e3 SH |
300 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 301 | reg = <0x1001c000 0x1000>; | |
| 302 | interrupts = <48>; | |
| c20736f1 FE |
303 | clocks = <&clks 78>, <&clks 61>; |
| 304 | clock-names = "ipg", "per"; | |
| 9f0749e3 SH |
305 | status = "disabled"; |
| 306 | }; | |
| 307 | ||
| 308 | i2c2: i2c@1001d000 { | |
| 309 | #address-cells = <1>; | |
| 310 | #size-cells = <0>; | |
| 5bdfba29 | 311 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
| 9f0749e3 SH |
312 | reg = <0x1001d000 0x1000>; |
| 313 | interrupts = <1>; | |
| c20736f1 | 314 | clocks = <&clks 39>; |
| 9f0749e3 SH |
315 | status = "disabled"; |
| 316 | }; | |
| 317 | ||
| 0e7b01aa AS |
318 | sdhci3: sdhci@1001e000 { |
| 319 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; | |
| 320 | reg = <0x1001e000 0x1000>; | |
| 321 | interrupts = <9>; | |
| 322 | clocks = <&clks 28>, <&clks 60>; | |
| 323 | clock-names = "ipg", "per"; | |
| 324 | dmas = <&dma 36>; | |
| 325 | dma-names = "rx-tx"; | |
| 326 | status = "disabled"; | |
| 327 | }; | |
| 328 | ||
| ca26d041 SH |
329 | gpt6: timer@1001f000 { |
| 330 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | |
| 331 | reg = <0x1001f000 0x1000>; | |
| 332 | interrupts = <2>; | |
| b700c119 SH |
333 | clocks = <&clks 41>, <&clks 61>; |
| 334 | clock-names = "ipg", "per"; | |
| ca26d041 | 335 | }; |
| 3e24b05b FE |
336 | }; |
| 337 | ||
| 338 | aipi@10020000 { /* AIPI2 */ | |
| 339 | compatible = "fsl,aipi-bus", "simple-bus"; | |
| 340 | #address-cells = <1>; | |
| 341 | #size-cells = <1>; | |
| 342 | reg = <0x10020000 0x20000>; | |
| 343 | ranges; | |
| 344 | ||
| 0c456cfa | 345 | fec: ethernet@1002b000 { |
| 9f0749e3 SH |
346 | compatible = "fsl,imx27-fec"; |
| 347 | reg = <0x1002b000 0x4000>; | |
| 348 | interrupts = <50>; | |
| c20736f1 FE |
349 | clocks = <&clks 48>, <&clks 67>, <&clks 0>; |
| 350 | clock-names = "ipg", "ahb", "ptp"; | |
| 9f0749e3 SH |
351 | status = "disabled"; |
| 352 | }; | |
| c20736f1 FE |
353 | |
| 354 | clks: ccm@10027000{ | |
| 355 | compatible = "fsl,imx27-ccm"; | |
| 356 | reg = <0x10027000 0x1000>; | |
| 357 | #clock-cells = <1>; | |
| 358 | }; | |
| 9f0749e3 | 359 | }; |
| 7b7d6727 | 360 | |
| c20736f1 | 361 | |
| 7b7d6727 | 362 | nfc: nand@d8000000 { |
| 37787360 UKK |
363 | #address-cells = <1>; |
| 364 | #size-cells = <1>; | |
| 365 | ||
| 366 | compatible = "fsl,imx27-nand"; | |
| 367 | reg = <0xd8000000 0x1000>; | |
| 368 | interrupts = <29>; | |
| c20736f1 | 369 | clocks = <&clks 54>; |
| 37787360 UKK |
370 | status = "disabled"; |
| 371 | }; | |
| 9f0749e3 SH |
372 | }; |
| 373 | }; |