[deliverable/linux.git] / arch / arm / boot / dts / imx27.dtsi

/*
 * Copyright 2012 Sascha Hauer, Pengutronix
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"

/ {
	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		spi0 = &cspi1;
		spi1 = &cspi2;
		spi2 = &cspi3;
	};

	aitc: aitc-interrupt-controller@e0000000 {
		compatible = "fsl,imx27-aitc", "fsl,avic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x10040000 0x1000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		osc26m {
			compatible = "fsl,imx-osc26m", "fixed-clock";
			clock-frequency = <26000000>;
		};
	};

	cpus {
		#size-cells = <0>;
		#address-cells = <1>;

		cpu {
			device_type = "cpu";
			compatible = "arm,arm926ej-s";
			operating-points = <
				/* kHz  uV (No regulator support) */
				133000  0
				399000  0
			>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clks 18>;
			clock-names = "cpu";
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&aitc>;
		ranges;

		aipi@10000000 { /* AIPI1 */
			compatible = "fsl,aipi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x10000000 0x20000>;
			ranges;

			dma: dma@10001000 {
				compatible = "fsl,imx27-dma";
				reg = <0x10001000 0x1000>;
				interrupts = <32>;
				clocks = <&clks 50>, <&clks 70>;
				clock-names = "ipg", "ahb";
				#dma-cells = <1>;
				#dma-channels = <16>;
			};

			wdog: wdog@10002000 {
				compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
				reg = <0x10002000 0x1000>;
				interrupts = <27>;
				clocks = <&clks 0>;
			};

			gpt1: timer@10003000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10003000 0x1000>;
				interrupts = <26>;
				clocks = <&clks 46>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			gpt2: timer@10004000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10004000 0x1000>;
				interrupts = <25>;
				clocks = <&clks 45>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			gpt3: timer@10005000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10005000 0x1000>;
				interrupts = <24>;
				clocks = <&clks 44>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			pwm: pwm@10006000 {
				compatible = "fsl,imx27-pwm";
				reg = <0x10006000 0x1000>;
				interrupts = <23>;
				clocks = <&clks 34>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			kpp: kpp@10008000 {
				compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
				reg = <0x10008000 0x1000>;
				interrupts = <21>;
				clocks = <&clks 37>;
				status = "disabled";
			};

			owire: owire@10009000 {
				compatible = "fsl,imx27-owire", "fsl,imx21-owire";
				reg = <0x10009000 0x1000>;
				clocks = <&clks 35>;
				status = "disabled";
			};

			uart1: serial@1000a000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000a000 0x1000>;
				interrupts = <20>;
				clocks = <&clks 81>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@1000b000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000b000 0x1000>;
				interrupts = <19>;
				clocks = <&clks 80>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart3: serial@1000c000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000c000 0x1000>;
				interrupts = <18>;
				clocks = <&clks 79>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart4: serial@1000d000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1000d000 0x1000>;
				interrupts = <17>;
				clocks = <&clks 78>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			cspi1: cspi@1000e000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-cspi";
				reg = <0x1000e000 0x1000>;
				interrupts = <16>;
				clocks = <&clks 53>, <&clks 53>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			cspi2: cspi@1000f000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-cspi";
				reg = <0x1000f000 0x1000>;
				interrupts = <15>;
				clocks = <&clks 52>, <&clks 52>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c1: i2c@10012000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
				reg = <0x10012000 0x1000>;
				interrupts = <12>;
				clocks = <&clks 40>;
				status = "disabled";
			};

			sdhci1: sdhci@10013000 {
				compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
				reg = <0x10013000 0x1000>;
				interrupts = <11>;
				clocks = <&clks 30>, <&clks 60>;
				clock-names = "ipg", "per";
				dmas = <&dma 7>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			sdhci2: sdhci@10014000 {
				compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
				reg = <0x10014000 0x1000>;
				interrupts = <10>;
				clocks = <&clks 29>, <&clks 60>;
				clock-names = "ipg", "per";
				dmas = <&dma 6>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			gpio1: gpio@10015000 {
				compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
				reg = <0x10015000 0x100>;
				interrupts = <8>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@10015100 {
				compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
				reg = <0x10015100 0x100>;
				interrupts = <8>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@10015200 {
				compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
				reg = <0x10015200 0x100>;
				interrupts = <8>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@10015300 {
				compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
				reg = <0x10015300 0x100>;
				interrupts = <8>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio5: gpio@10015400 {
				compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
				reg = <0x10015400 0x100>;
				interrupts = <8>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio6: gpio@10015500 {
				compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
				reg = <0x10015500 0x100>;
				interrupts = <8>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			audmux: audmux@10016000 {
				compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
				reg = <0x10016000 0x1000>;
				clocks = <&clks 0>;
				clock-names = "audmux";
			};

			cspi3: cspi@10017000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-cspi";
				reg = <0x10017000 0x1000>;
				interrupts = <6>;
				clocks = <&clks 51>, <&clks 51>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			gpt4: timer@10019000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x10019000 0x1000>;
				interrupts = <4>;
				clocks = <&clks 43>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			gpt5: timer@1001a000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x1001a000 0x1000>;
				interrupts = <3>;
				clocks = <&clks 42>, <&clks 61>;
				clock-names = "ipg", "per";
			};

			uart5: serial@1001b000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1001b000 0x1000>;
				interrupts = <49>;
				clocks = <&clks 77>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart6: serial@1001c000 {
				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
				reg = <0x1001c000 0x1000>;
				interrupts = <48>;
				clocks = <&clks 78>, <&clks 61>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@1001d000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
				reg = <0x1001d000 0x1000>;
				interrupts = <1>;
				clocks = <&clks 39>;
				status = "disabled";
			};

			sdhci3: sdhci@1001e000 {
				compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
				reg = <0x1001e000 0x1000>;
				interrupts = <9>;
				clocks = <&clks 28>, <&clks 60>;
				clock-names = "ipg", "per";
				dmas = <&dma 36>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			gpt6: timer@1001f000 {
				compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
				reg = <0x1001f000 0x1000>;
				interrupts = <2>;
				clocks = <&clks 41>, <&clks 61>;
				clock-names = "ipg", "per";
			};
		};

		aipi@10020000 { /* AIPI2 */
			compatible = "fsl,aipi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x10020000 0x20000>;
			ranges;

			fb: fb@10021000 {
				compatible = "fsl,imx27-fb", "fsl,imx21-fb";
				interrupts = <61>;
				reg = <0x10021000 0x1000>;
				clocks = <&clks 36>, <&clks 65>, <&clks 59>;
				clock-names = "ipg", "ahb", "per";
				status = "disabled";
			};

			coda: coda@10023000 {
				compatible = "fsl,imx27-vpu";
				reg = <0x10023000 0x0200>;
				interrupts = <53>;
				clocks = <&clks 57>, <&clks 66>;
				clock-names = "per", "ahb";
				iram = <&iram>;
			};

			sahara2: sahara@10025000 {
				compatible = "fsl,imx27-sahara";
				reg = <0x10025000 0x1000>;
				interrupts = <59>;
				clocks = <&clks 32>, <&clks 64>;
				clock-names = "ipg", "ahb";
			};

			clks: ccm@10027000{
				compatible = "fsl,imx27-ccm";
				reg = <0x10027000 0x1000>;
				#clock-cells = <1>;
			};

			iim: iim@10028000 {
				compatible = "fsl,imx27-iim";
				reg = <0x10028000 0x1000>;
				interrupts = <62>;
				clocks = <&clks 38>;
			};

			fec: ethernet@1002b000 {
				compatible = "fsl,imx27-fec";
				reg = <0x1002b000 0x4000>;
				interrupts = <50>;
				clocks = <&clks 48>, <&clks 67>, <&clks 0>;
				clock-names = "ipg", "ahb", "ptp";
				status = "disabled";
			};
		};

		nfc: nand@d8000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,imx27-nand";
			reg = <0xd8000000 0x1000>;
			interrupts = <29>;
			clocks = <&clks 54>;
			status = "disabled";
		};

		weim: weim@d8002000 {
			#address-cells = <2>;
			#size-cells = <1>;
			compatible = "fsl,imx27-weim";
			reg = <0xd8002000 0x1000>;
			clocks = <&clks 0>;
			ranges = <
				0 0 0xc0000000 0x08000000
				1 0 0xc8000000 0x08000000
				2 0 0xd0000000 0x02000000
				3 0 0xd2000000 0x02000000
				4 0 0xd4000000 0x02000000
				5 0 0xd6000000 0x02000000
			>;
			status = "disabled";
		};

		iram: iram@ffff4c00 {
			compatible = "mmio-sram";
			reg = <0xffff4c00 0xb400>;
		};
	};
};
Commit	Line	Data
9f0749e3 SH	1	/*
	2	* Copyright 2012 Sascha Hauer, Pengutronix
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
36dffd8f	12	#include "skeleton.dtsi"
9f0749e3 SH	13
	14	/ {
	15	aliases {
5230f8fe SG	16	gpio0 = &gpio1;
	17	gpio1 = &gpio2;
	18	gpio2 = &gpio3;
	19	gpio3 = &gpio4;
	20	gpio4 = &gpio5;
	21	gpio5 = &gpio6;
6a3c0b39 SH	22	i2c0 = &i2c1;
	23	i2c1 = &i2c2;
	24	serial0 = &uart1;
	25	serial1 = &uart2;
	26	serial2 = &uart3;
	27	serial3 = &uart4;
	28	serial4 = &uart5;
	29	serial5 = &uart6;
a5a641a1 AS	30	spi0 = &cspi1;
	31	spi1 = &cspi2;
	32	spi2 = &cspi3;
9f0749e3 SH	33	};
9f0749e3 SH	34
6189bc34 FE	35	aitc: aitc-interrupt-controller@e0000000 {
6189bc34 FE	36	compatible = "fsl,imx27-aitc", "fsl,avic";
9f0749e3 SH	37	interrupt-controller;
	38	#interrupt-cells = <1>;
	39	reg = <0x10040000 0x1000>;
	40	};
	41
	42	clocks {
	43	#address-cells = <1>;
	44	#size-cells = <0>;
	45
	46	osc26m {
	47	compatible = "fsl,imx-osc26m", "fixed-clock";
	48	clock-frequency = <26000000>;
	49	};
	50	};
	51
dc1d0f91 MP	52	cpus {
	53	#size-cells = <0>;
	54	#address-cells = <1>;
	55
	56	cpu {
	57	device_type = "cpu";
	58	compatible = "arm,arm926ej-s";
	59	operating-points = <
	60	/* kHz uV (No regulator support) */
	61	133000 0
	62	399000 0
	63	>;
	64	clock-latency = <61036>; /* two CLK32 periods */
	65	clocks = <&clks 18>;
	66	clock-names = "cpu";
	67	};
	68	};
	69
9f0749e3 SH	70	soc {
	71	#address-cells = <1>;
	72	#size-cells = <1>;
	73	compatible = "simple-bus";
6189bc34	74	interrupt-parent = <&aitc>;
9f0749e3 SH	75	ranges;
	76
	77	aipi@10000000 { /* AIPI1 */
	78	compatible = "fsl,aipi-bus", "simple-bus";
	79	#address-cells = <1>;
	80	#size-cells = <1>;
3e24b05b	81	reg = <0x10000000 0x20000>;
9f0749e3 SH	82	ranges;
9f0749e3 SH	83
b858c34f AS	84	dma: dma@10001000 {
	85	compatible = "fsl,imx27-dma";
	86	reg = <0x10001000 0x1000>;
	87	interrupts = <32>;
	88	clocks = <&clks 50>, <&clks 70>;
	89	clock-names = "ipg", "ahb";
	90	#dma-cells = <1>;
	91	#dma-channels = <16>;
	92	};
	93
7b7d6727	94	wdog: wdog@10002000 {
9f0749e3	95	compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
ca26d041	96	reg = <0x10002000 0x1000>;
9f0749e3	97	interrupts = <27>;
c20736f1	98	clocks = <&clks 0>;
9f0749e3 SH	99	};
9f0749e3 SH	100
ca26d041 SH	101	gpt1: timer@10003000 {
	102	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	103	reg = <0x10003000 0x1000>;
	104	interrupts = <26>;
b700c119 SH	105	clocks = <&clks 46>, <&clks 61>;
b700c119 SH	106	clock-names = "ipg", "per";
ca26d041 SH	107	};
	108
	109	gpt2: timer@10004000 {
	110	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	111	reg = <0x10004000 0x1000>;
	112	interrupts = <25>;
b700c119 SH	113	clocks = <&clks 45>, <&clks 61>;
b700c119 SH	114	clock-names = "ipg", "per";
ca26d041 SH	115	};
	116
	117	gpt3: timer@10005000 {
	118	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	119	reg = <0x10005000 0x1000>;
	120	interrupts = <24>;
b700c119 SH	121	clocks = <&clks 44>, <&clks 61>;
b700c119 SH	122	clock-names = "ipg", "per";
ca26d041 SH	123	};
ca26d041 SH	124
a392d044	125	pwm: pwm@10006000 {
08f4881a GGM	126	compatible = "fsl,imx27-pwm";
	127	reg = <0x10006000 0x1000>;
	128	interrupts = <23>;
	129	clocks = <&clks 34>, <&clks 61>;
	130	clock-names = "ipg", "per";
	131	};
	132
6c04ad22 AS	133	kpp: kpp@10008000 {
	134	compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
	135	reg = <0x10008000 0x1000>;
	136	interrupts = <21>;
	137	clocks = <&clks 37>;
	138	status = "disabled";
	139	};
	140
6a486b7e MP	141	owire: owire@10009000 {
	142	compatible = "fsl,imx27-owire", "fsl,imx21-owire";
	143	reg = <0x10009000 0x1000>;
	144	clocks = <&clks 35>;
	145	status = "disabled";
	146	};
	147
0c456cfa	148	uart1: serial@1000a000 {
9f0749e3 SH	149	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	150	reg = <0x1000a000 0x1000>;
	151	interrupts = <20>;
c20736f1 FE	152	clocks = <&clks 81>, <&clks 61>;
c20736f1 FE	153	clock-names = "ipg", "per";
9f0749e3 SH	154	status = "disabled";
	155	};
	156
0c456cfa	157	uart2: serial@1000b000 {
9f0749e3 SH	158	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	159	reg = <0x1000b000 0x1000>;
	160	interrupts = <19>;
c20736f1 FE	161	clocks = <&clks 80>, <&clks 61>;
c20736f1 FE	162	clock-names = "ipg", "per";
9f0749e3 SH	163	status = "disabled";
	164	};
	165
0c456cfa	166	uart3: serial@1000c000 {
9f0749e3 SH	167	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	168	reg = <0x1000c000 0x1000>;
	169	interrupts = <18>;
c20736f1 FE	170	clocks = <&clks 79>, <&clks 61>;
c20736f1 FE	171	clock-names = "ipg", "per";
9f0749e3 SH	172	status = "disabled";
	173	};
	174
0c456cfa	175	uart4: serial@1000d000 {
9f0749e3 SH	176	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	177	reg = <0x1000d000 0x1000>;
	178	interrupts = <17>;
c20736f1 FE	179	clocks = <&clks 78>, <&clks 61>;
c20736f1 FE	180	clock-names = "ipg", "per";
9f0749e3 SH	181	status = "disabled";
	182	};
	183
	184	cspi1: cspi@1000e000 {
	185	#address-cells = <1>;
	186	#size-cells = <0>;
	187	compatible = "fsl,imx27-cspi";
	188	reg = <0x1000e000 0x1000>;
	189	interrupts = <16>;
37523dc5	190	clocks = <&clks 53>, <&clks 53>;
c20736f1	191	clock-names = "ipg", "per";
9f0749e3 SH	192	status = "disabled";
	193	};
	194
	195	cspi2: cspi@1000f000 {
	196	#address-cells = <1>;
	197	#size-cells = <0>;
	198	compatible = "fsl,imx27-cspi";
	199	reg = <0x1000f000 0x1000>;
	200	interrupts = <15>;
37523dc5	201	clocks = <&clks 52>, <&clks 52>;
c20736f1	202	clock-names = "ipg", "per";
9f0749e3 SH	203	status = "disabled";
	204	};
	205
	206	i2c1: i2c@10012000 {
	207	#address-cells = <1>;
	208	#size-cells = <0>;
5bdfba29	209	compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
9f0749e3 SH	210	reg = <0x10012000 0x1000>;
9f0749e3 SH	211	interrupts = <12>;
c20736f1	212	clocks = <&clks 40>;
9f0749e3 SH	213	status = "disabled";
	214	};
	215
0e7b01aa AS	216	sdhci1: sdhci@10013000 {
	217	compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
	218	reg = <0x10013000 0x1000>;
	219	interrupts = <11>;
	220	clocks = <&clks 30>, <&clks 60>;
	221	clock-names = "ipg", "per";
	222	dmas = <&dma 7>;
	223	dma-names = "rx-tx";
	224	status = "disabled";
	225	};
	226
	227	sdhci2: sdhci@10014000 {
	228	compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
	229	reg = <0x10014000 0x1000>;
	230	interrupts = <10>;
	231	clocks = <&clks 29>, <&clks 60>;
	232	clock-names = "ipg", "per";
	233	dmas = <&dma 6>;
	234	dma-names = "rx-tx";
	235	status = "disabled";
	236	};
	237
9f0749e3 SH	238	gpio1: gpio@10015000 {
	239	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	240	reg = <0x10015000 0x100>;
	241	interrupts = <8>;
	242	gpio-controller;
	243	#gpio-cells = <2>;
	244	interrupt-controller;
88cde8b7	245	#interrupt-cells = <2>;
9f0749e3 SH	246	};
	247
	248	gpio2: gpio@10015100 {
	249	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	250	reg = <0x10015100 0x100>;
	251	interrupts = <8>;
	252	gpio-controller;
	253	#gpio-cells = <2>;
	254	interrupt-controller;
88cde8b7	255	#interrupt-cells = <2>;
9f0749e3 SH	256	};
	257
	258	gpio3: gpio@10015200 {
	259	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	260	reg = <0x10015200 0x100>;
	261	interrupts = <8>;
	262	gpio-controller;
	263	#gpio-cells = <2>;
	264	interrupt-controller;
88cde8b7	265	#interrupt-cells = <2>;
9f0749e3 SH	266	};
	267
	268	gpio4: gpio@10015300 {
	269	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	270	reg = <0x10015300 0x100>;
	271	interrupts = <8>;
	272	gpio-controller;
	273	#gpio-cells = <2>;
	274	interrupt-controller;
88cde8b7	275	#interrupt-cells = <2>;
9f0749e3 SH	276	};
	277
	278	gpio5: gpio@10015400 {
	279	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	280	reg = <0x10015400 0x100>;
	281	interrupts = <8>;
	282	gpio-controller;
	283	#gpio-cells = <2>;
	284	interrupt-controller;
88cde8b7	285	#interrupt-cells = <2>;
9f0749e3 SH	286	};
	287
	288	gpio6: gpio@10015500 {
	289	compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
	290	reg = <0x10015500 0x100>;
	291	interrupts = <8>;
	292	gpio-controller;
	293	#gpio-cells = <2>;
	294	interrupt-controller;
88cde8b7	295	#interrupt-cells = <2>;
9f0749e3 SH	296	};
9f0749e3 SH	297
6e228e80 AS	298	audmux: audmux@10016000 {
	299	compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
	300	reg = <0x10016000 0x1000>;
	301	clocks = <&clks 0>;
	302	clock-names = "audmux";
	303	};
	304
9f0749e3 SH	305	cspi3: cspi@10017000 {
	306	#address-cells = <1>;
	307	#size-cells = <0>;
	308	compatible = "fsl,imx27-cspi";
	309	reg = <0x10017000 0x1000>;
	310	interrupts = <6>;
37523dc5	311	clocks = <&clks 51>, <&clks 51>;
c20736f1	312	clock-names = "ipg", "per";
9f0749e3 SH	313	status = "disabled";
	314	};
	315
ca26d041 SH	316	gpt4: timer@10019000 {
	317	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	318	reg = <0x10019000 0x1000>;
	319	interrupts = <4>;
b700c119 SH	320	clocks = <&clks 43>, <&clks 61>;
b700c119 SH	321	clock-names = "ipg", "per";
ca26d041 SH	322	};
	323
	324	gpt5: timer@1001a000 {
	325	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	326	reg = <0x1001a000 0x1000>;
	327	interrupts = <3>;
b700c119 SH	328	clocks = <&clks 42>, <&clks 61>;
b700c119 SH	329	clock-names = "ipg", "per";
ca26d041 SH	330	};
ca26d041 SH	331
0c456cfa	332	uart5: serial@1001b000 {
9f0749e3 SH	333	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	334	reg = <0x1001b000 0x1000>;
	335	interrupts = <49>;
c20736f1 FE	336	clocks = <&clks 77>, <&clks 61>;
c20736f1 FE	337	clock-names = "ipg", "per";
9f0749e3 SH	338	status = "disabled";
	339	};
	340
0c456cfa	341	uart6: serial@1001c000 {
9f0749e3 SH	342	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
	343	reg = <0x1001c000 0x1000>;
	344	interrupts = <48>;
c20736f1 FE	345	clocks = <&clks 78>, <&clks 61>;
c20736f1 FE	346	clock-names = "ipg", "per";
9f0749e3 SH	347	status = "disabled";
	348	};
	349
	350	i2c2: i2c@1001d000 {
	351	#address-cells = <1>;
	352	#size-cells = <0>;
5bdfba29	353	compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
9f0749e3 SH	354	reg = <0x1001d000 0x1000>;
9f0749e3 SH	355	interrupts = <1>;
c20736f1	356	clocks = <&clks 39>;
9f0749e3 SH	357	status = "disabled";
	358	};
	359
0e7b01aa AS	360	sdhci3: sdhci@1001e000 {
	361	compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
	362	reg = <0x1001e000 0x1000>;
	363	interrupts = <9>;
	364	clocks = <&clks 28>, <&clks 60>;
	365	clock-names = "ipg", "per";
	366	dmas = <&dma 36>;
	367	dma-names = "rx-tx";
	368	status = "disabled";
	369	};
	370
ca26d041 SH	371	gpt6: timer@1001f000 {
	372	compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
	373	reg = <0x1001f000 0x1000>;
	374	interrupts = <2>;
b700c119 SH	375	clocks = <&clks 41>, <&clks 61>;
b700c119 SH	376	clock-names = "ipg", "per";
ca26d041	377	};
3e24b05b FE	378	};
	379
	380	aipi@10020000 { /* AIPI2 */
	381	compatible = "fsl,aipi-bus", "simple-bus";
	382	#address-cells = <1>;
	383	#size-cells = <1>;
	384	reg = <0x10020000 0x20000>;
	385	ranges;
	386
5e57b241 MP	387	fb: fb@10021000 {
	388	compatible = "fsl,imx27-fb", "fsl,imx21-fb";
	389	interrupts = <61>;
	390	reg = <0x10021000 0x1000>;
	391	clocks = <&clks 36>, <&clks 65>, <&clks 59>;
	392	clock-names = "ipg", "ahb", "per";
	393	status = "disabled";
	394	};
	395
93b331ce AS	396	coda: coda@10023000 {
	397	compatible = "fsl,imx27-vpu";
	398	reg = <0x10023000 0x0200>;
	399	interrupts = <53>;
	400	clocks = <&clks 57>, <&clks 66>;
	401	clock-names = "per", "ahb";
	402	iram = <&iram>;
	403	};
	404
e4b6a056 AS	405	sahara2: sahara@10025000 {
	406	compatible = "fsl,imx27-sahara";
	407	reg = <0x10025000 0x1000>;
	408	interrupts = <59>;
	409	clocks = <&clks 32>, <&clks 64>;
	410	clock-names = "ipg", "ahb";
	411	};
	412
93b331ce AS	413	clks: ccm@10027000{
	414	compatible = "fsl,imx27-ccm";
	415	reg = <0x10027000 0x1000>;
	416	#clock-cells = <1>;
	417	};
	418
d36afcd4 AS	419	iim: iim@10028000 {
	420	compatible = "fsl,imx27-iim";
	421	reg = <0x10028000 0x1000>;
	422	interrupts = <62>;
	423	clocks = <&clks 38>;
	424	};
	425
0c456cfa	426	fec: ethernet@1002b000 {
9f0749e3 SH	427	compatible = "fsl,imx27-fec";
	428	reg = <0x1002b000 0x4000>;
	429	interrupts = <50>;
c20736f1 FE	430	clocks = <&clks 48>, <&clks 67>, <&clks 0>;
c20736f1 FE	431	clock-names = "ipg", "ahb", "ptp";
9f0749e3 SH	432	status = "disabled";
	433	};
	434	};
7b7d6727 SH	435
7b7d6727 SH	436	nfc: nand@d8000000 {
37787360 UKK	437	#address-cells = <1>;
37787360 UKK	438	#size-cells = <1>;
37787360 UKK	439	compatible = "fsl,imx27-nand";
	440	reg = <0xd8000000 0x1000>;
	441	interrupts = <29>;
c20736f1	442	clocks = <&clks 54>;
37787360 UKK	443	status = "disabled";
37787360 UKK	444	};
ff1450f6	445
0912f594 AS	446	weim: weim@d8002000 {
	447	#address-cells = <2>;
	448	#size-cells = <1>;
	449	compatible = "fsl,imx27-weim";
	450	reg = <0xd8002000 0x1000>;
	451	clocks = <&clks 0>;
	452	ranges = <
	453	0 0 0xc0000000 0x08000000
	454	1 0 0xc8000000 0x08000000
	455	2 0 0xd0000000 0x02000000
	456	3 0 0xd2000000 0x02000000
	457	4 0 0xd4000000 0x02000000
	458	5 0 0xd6000000 0x02000000
	459	>;
	460	status = "disabled";
	461	};
	462
ff1450f6 AS	463	iram: iram@ffff4c00 {
	464	compatible = "mmio-sram";
	465	reg = <0xffff4c00 0xb400>;
	466	};
9f0749e3 SH	467	};
9f0749e3 SH	468	};